/**
 @file sys_tmm_mac.c

 @author  Copyright (C) 2019 Centec Networks Inc.  All rights reserved.

 @date 2019-6-19

 @version v2.0

*/

/// TEMP COMMENT
/// mac.c content :
///  #1, mac pcs fec config/reset
///  #2, port API
///  #3, dynamic switch
/****************************************************************************
 *
* Header Files
*
****************************************************************************/
#include "sal.h"
#include "ctc_error.h"
#include "ctc_debug.h"
#include "ctc_interrupt.h"
#include "ctc_warmboot.h"

#include "sys_usw_common.h"
#include "sys_usw_chip.h"
#include "sys_usw_peri.h"
#include "sys_usw_stats_api.h"
#include "sys_usw_dmps.h"
#include "sys_usw_interrupt.h"
#include "sys_usw_port.h"
#include "sys_usw_wb_common.h"
#include "sys_usw_mcu.h"
#include "sys_usw_flexe.h"
#include "sys_usw_register.h"
#include "sys_usw_phy.h"

#include "sys_tmm_datapath.h"
#include "sys_tmm_mac.h"
#include "sys_tmm_serdes.h"
#include "sys_tmm_serdes_reg.h"
#include "sys_tmm_flexe.h"

#include "drv_api.h"
#include "usw/include/drv_common.h"
#include "sys_usw_register.h"

/****************************************************************************
 *
* Defines and Macros
*
*****************************************************************************/

extern int32
sys_usw_mac_set_3ap_training_en(uint8 lchip, uint32 gport, uint32 enable);

extern int16
sys_tmm_serdes_set_serdes_auto_neg_ability(uint8 lchip, uint16 serdes_id, sys_datapath_an_ability_t* p_ability);

extern int32
sys_tmm_datapath_get_serdes_loopback(uint8 lchip, void* p_data);

extern int16
sys_tmm_serdes_set_serdes_auto_neg_en(uint8 lchip, uint16 serdes_id, uint32 enable);

extern int16
sys_tmm_serdes_get_serdes_auto_neg_remote_ability(uint8 lchip, uint16 serdes_id, sys_datapath_an_ability_t* p_ability);

extern int16
sys_tmm_serdes_get_serdes_auto_neg_local_ability(uint8 lchip, uint16 serdes_id, sys_datapath_an_ability_t* p_ability);

extern int32
_sys_usw_mac_get_speed_mode_capability(uint8 lchip, uint16 lport, uint32* speed_mode_bitmap);

extern int32
_sys_usw_mac_get_if_type_capability(uint8 lchip, uint16 lport, uint32* if_type_bitmap);

extern int32 
sys_tmm_serdes_write_reg(uint8 lchip, uint8 serdes_id, uint16 addr, uint16 mask, uint16 data);

extern int32 
sys_tmm_serdes_read_reg(uint8 lchip, uint8 serdes_id, uint16 addr, uint16 mask, uint16 *data);

extern int32
_sys_tmm_serdes_fw_config(uint8 lchip, sys_tmm_serdes_fw_config_param_t *p_data);

extern int32
sys_tmm_datapath_get_serdes_ffe(uint8 lchip, void *p_data);

extern int32
sys_tmm_datapath_set_serdes_ffe(uint8 lchip, void* p_data);

extern int32
sys_tmm_serdes_set_power_en(uint8 lchip, uint16 serdes_id, uint8 enable);

extern int32
sys_tmm_serdes_set_link_training_en(uint8 lchip, uint16 serdes_id, uint8 enable);

extern int32
sys_tmm_serdes_set_domain_reset(uint8 lchip, uint8 serdes_id, uint8 rst_type);

STATIC int32
_sys_tmm_cpumac_set_sgmii_config(uint8 lchip, uint16 lport);

STATIC int32
_sys_tmm_cpumac_get_sgmii_link_status(uint8 lchip, uint8 type, uint16 lport, uint32* p_value, uint32 unidir_en);

int32
_sys_tmm_dynamic_switch_serdes_cfg(uint8 lchip, uint8 phy_serdes_id, uint8 logic_serdes_id, uint8 src_mode, uint8 dst_mode, uint8 ovclk_flag);

extern int32
_sys_usw_mac_get_cl73_auto_neg(uint8 lchip, uint16 lport, uint32 type, uint32* p_value);

extern int32
_sys_usw_mac_get_3ap_training_en(uint8 lchip, uint16 lport, uint32* p_status);

int32
_sys_tmm_mac_pcs_rx_rst(uint8 lchip, uint16 lport, uint8 reset);

int32
_sys_tmm_mac_mii_rx_rst(uint8 lchip, uint16 lport, uint8 reset);

extern int32
_sys_usw_mac_get_cl37_an_remote_status(uint8 lchip, uint16 lport, uint32 auto_neg_mode, uint32* p_speed, uint32* p_link);

extern int32
sys_tmm_flexe_check_serdes_bind_group(uint8 lchip, uint16 serdes_id, uint32 *is_bind);

extern int32
sys_tmm_serdes_set_tx_prbs(uint8 lchip, ctc_chip_serdes_prbs_t *p_prbs);

extern int32 
sys_tmm_serdes_get_glb_info(uint8 lchip, uint8 physic_serdes_id, sys_tmm_serdes_glb_info_type_t type, uint8 *value);

extern int32
sys_tmm_datapath_set_serdes_loopback(uint8 lchip, void* p_data);

int32
_sys_tmm_mac_get_fec_type_capability(uint8 pcs_mode, uint32* p_value);

extern int32
_sys_tmm_serdes_fw_deconfig(uint8 lchip, uint16 serdes_id);

extern int32
sys_tmm_serdes_set_mode(uint8 lchip, ctc_chip_serdes_info_t* p_serdes_info);

extern int32
sys_tmm_datapath_serdes_clktree_cpumac_cfg(uint8 lchip, uint8 lane_id, uint8 mode);

extern int32
sys_usw_mac_wb_restore(uint8 lchip);
int32
_sys_tmm_cpumac_set_ipg(uint8 lchip, uint16 lport, uint32 value);
int32
_sys_tmm_cpumac_set_internal_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 value);
int32
_sys_tmm_mac_get_pcs_link_status(uint8 lchip, uint16 lport, uint32* p_is_up);

extern int32
sys_tmm_serdes_get_phyready(uint8 lchip, uint8 physic_serdes_id, uint32* value);

extern int32
sys_tmm_serdes_get_signal_detect(uint8 lchip, uint8 physic_serdes_id, uint8* p_is_detect, uint8* p_raw_sigdet);

extern int32
sys_tmm_calendar_speed_info_collect(uint8 lchip, sys_cal_info_collect_t cal_info[], uint8 dp_id, uint8 dp_txqm_id, uint8 cal_type);

extern int32
_sys_tmm_datapath_calculate_general_calendar_parser(uint8 lchip, uint8 dp_id, uint8 is_cpumac_cal, uint16* cal, 
                                                    uint16* walk_end, sys_cal_info_collect_t* cal_info);

extern int32
_sys_tmm_flexe_check_mac_en_condition(uint8 lchip, uint16 mac_id, uint8 dir, uint8 enable);

extern int32
sys_tmm_serdes_set_tx_en(uint8 lchip, uint8 serdes_id, uint8 enable);

extern int32
_sys_tmm_mac_sgmii_get_parallel_detect_en(uint8 lchip, uint16 lport, uint32 *value);

extern int32
_sys_tmm_mac_sgmii_set_parallel_detect_en(uint8 lchip, uint16 lport, uint8 enable);

extern int32
_sys_tmm_mac_qsgmii_get_parallel_detect_en(uint8 lchip, uint16 lport, uint32 *value);

extern int32
_sys_tmm_mac_qsgmii_set_parallel_detect_en(uint8 lchip, uint16 lport, uint8 enable);

extern int32
sys_tmm_flexe_phy_link_up_event(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr);

extern int32
sys_tmm_flexe_phy_link_down_event(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr);

int32
_sys_tmm_cpumac_sgmii_20T_clock_toggle(uint8 lchip, uint8 lport);

extern int32
_sys_tmm_datapath_set_internal_loopback_pcs(uint8 lchip, uint8 physic_serdes_id, uint8 enable);

extern int32
_sys_tmm_datapath_check_credit_sum(uint8 lchip, uint8 dp_id);

extern int32
_sys_tmm_datapath_get_serdes_loopback(uint8 lchip, ctc_chip_serdes_loopback_t* p_loopback);

extern int32
_sys_tmm_datapath_set_serdes_loopback(uint8 lchip, ctc_chip_serdes_loopback_t* p_loopback);

extern int32
sys_tmm_serdes_get_internal_loopback_pcs(uint8 lchip, uint8 physic_serdes_id, uint8 *p_enable);

extern int32
_sys_tmm_serdes_fw_tuning_recover(uint8 lchip, uint16 lport, uint8 serdes_id, uint8 pcs_mode);

extern int32
sys_tmm_flexe_alarm_lpf(uint8 lchip, uint8 logical_serdes_id, uint32 link_stat);

extern int32
_sys_tmm_serdes_set_mode_proc(uint8 lchip, ctc_chip_serdes_info_t* p_serdes_info);

extern int32
_sys_tmm_mac_set_tx_force_fault(uint8 lchip, uint16 lport, uint32 fault_bmp);

extern int32
_sys_tmm_mac_set_tx_force_fault_by_mac_id(uint8 lchip, uint16 mac_id, uint32 fault_bmp);

extern int32
_sys_tmm_mac_get_fec_en(uint8 lchip, uint16 lport, uint32* p_value);

extern int32
_sys_tmm_flexe_client_lookup_by_mac(uint8 lchip, uint16 mac_id, sys_flexe_client_t** pp_client);

extern int32
_sys_tmm_flexe_get_client_slot_cnt(uint8 lchip, sys_flexe_client_t *client_node, uint8 dir, uint8 act_flag, uint8 *p_cnt);

extern int32
_sys_tmm_flexe_get_phy_status_by_lport(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr, uint8 lock_type, uint8* p_status);

extern int32
sys_tmm_flexe_check_client_match(uint8 lchip, sys_flexe_client_t *client_node, uint8 *p_match);

extern int32
sys_tmm_flexe_phy_link_up_event(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr);

extern int32
sys_tmm_flexe_phy_link_down_event(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr);

extern int32
sys_tmm_flexe_alarm_phy_link_down(uint8 lchip, uint8 logical_serdes_id);

extern sys_flexe_phy_t*
_sys_tmm_flexe_get_phy_node(uint8 lchip, uint8 logical_serdes_id);

extern int32 
_sys_tmm_flexe_alarm_ohlock_ohmflock_isr(uint8 lchip, uint32 flexe_shim_id, uint8 asic_inst, uint8 intr, uint8 event_type);

extern int32
_sys_tmm_flexe_get_hw_enable(uint8 lchip, uint8 txqm_id, uint8 *p_enable);

extern int32
sys_tmm_serdes_get_tx_en(uint8 lchip, uint8 serdes_id, uint8* p_en);

extern sal_file_t g_tm_dump_fp;
extern const uint8 g_dmps_dbg_sw;

extern sys_datapath_master_t* p_usw_datapath_master[];
extern const sys_logic_lane_to_pcs_mac_map_t g_lane_2_pcs_mac_map[];

/* DRV_IOW_FIELD extender, for index Not Zero */
#define DRV_IOW_FIELD_NZ(lchip, memid, fieldid, value, ptr, inst, index) \
    DRV_IOW_FIELD(lchip, memid, fieldid, value, ptr) 

#define DRV_IOW_PRINT_NZ(lchip, memid, fieldid, value, inst, index) \
    do\
    {\
        char   fld_str[64] = {0};\
        if(MaxTblId_t <= memid) return CTC_E_INTR_INVALID_PARAM;\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            sal_fprintf(g_tm_dump_fp, "write  %s  %d  %s     0x%x inst %d\n", \
                TABLE_NAME(lchip, memid),index, fld_str, value, inst); \
        }\
    }\
    while(0)

#define DRV_IOW_PRINT(lchip, memid, fieldid, value) \
    do\
    {\
        char   fld_str[64] = {0};\
        if(MaxTblId_t <= memid) return CTC_E_INTR_INVALID_PARAM;\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            sal_fprintf(g_tm_dump_fp, "write  %s  0  %s     0x%x\n", \
                TABLE_NAME(lchip, memid), fld_str, value); \
        }\
    }\
    while(0)

#define TSINGMA_DUMP_PRINT  if(g_dmps_dbg_sw && g_tm_dump_fp) sal_fprintf

/****************************************************************************
 *
* Global and Declaration
*
*****************************************************************************/
extern sys_mac_master_t* p_usw_mac_master[CTC_MAX_LOCAL_CHIP_NUM_PP];

const uint8 g_hata_sgmii_en = FALSE; /*default DISABLE SGMII HATA*/

int32
_sys_tmm_print_config_list(uint8 lchip, uint32 item_cnt, sys_macpcs_config_item_t* p_list);


/************************* McMac info resgiter tables *************************/
const uint32 g_mcmac_cfg_flag[McMac_TOTAL_CNT] = {
    ITEM_WRITE_CONST,    /*0 McMac_cfgMcMacTxSpeed*/   
    ITEM_WRITE_CONST,    /*1 McMac_cfgTxAmInsertEn*/   
    ITEM_WRITE_CONST,    /*2 McMac_cfgTxAmInterval*/   
    ITEM_WRITE_CONST,    /*3 McMac_cfgMcMacTxIpgDelEn*/
    ITEM_WRITE_CONST,    /*4 McMac_cfgTxRsFecEn*/      
    ITEM_WRITE_CONST,    /*5 McMac_cfgTxRsFecMode*/    
    ITEM_WRITE_CONST,    /*6 McMac_cfgTxChanIdLane*/   
    ITEM_WRITE_CONST,    /*7 McMac_TxPortMap*/         
    ITEM_WRITE_CONST,    /*8 McMac_RxChanMap*/         
    ITEM_WRITE_CONST,    /*9 McMac_cfgTxCreditThrd*/   
    ITEM_WRITE_CONST,    /*10 McMac_cfgMcMacSgmiiTxNotUsePortMap*/
    ITEM_NO_WRITE,       /*11 McMac_cfgMcMacMacTxSoftReset*/
    ITEM_WRITE_CONST,    /*12 McMac_cfgMcMacTxThreshold*/
    ITEM_WRITE_CONST,    /*13 McMac_cfgMcMacMiiSgmiiMod*/
    ITEM_WRITE_CONST,    /*14 McMac_cfgMcMacMiiQsgmiiMod*/
    ITEM_WRITE_CONST,    /*15 McMac_cfgMiiRxSampleCnt*/
    ITEM_WRITE_CONST,    /*16 McMac_cfgMcMacTxReplicateCnt*/
    ITEM_WRITE_CONST,    /*17 McMac_cfgMcMacMiiRxBuffMaxDepth*/
    ITEM_WRITE_CONST,    /*18 McMac_cfgMcMacRxUseHataTsEn*/
    ITEM_WRITE_CONST,    /*19 McMac_cfgMcMacPmInterval*/
    ITEM_WRITE_CONST,    /*20 McMac_cfgMcMacMacTxWaitCaptureTs*/
    ITEM_WRITE_CONST,    /*21 McHata_cfgHataRsFecMode*/
    ITEM_WRITE_CONST,    /*22 McMac_cfgMcMacMiiRxForceFault*/
    ITEM_WRITE_CONST,    /*23 McMac_cfgMcMacMiiRxLDForceFault*/
};
const uint32 g_mcmac_tbl_id_base[McMac_TOTAL_CNT] = {
    McMacMiiTxCfg_t,        /*0 McMac_cfgMcMacTxSpeed*/   
    McMacMiiTxCfg_t,        /*1 McMac_cfgTxAmInsertEn*/   
    McMacMiiTxCfg_t,        /*2 McMac_cfgTxAmInterval*/   
    McMacMiiTxCfg_t,        /*3 McMac_cfgMcMacTxIpgDelEn*/
    McMacMiiTxCfg_t,        /*4 McMac_cfgTxRsFecEn*/      
    McMacMiiTxCfg_t,        /*5 McMac_cfgTxRsFecMode*/    
    McMacTxChanIdLaneCfg_t, /*6 McMac_cfgTxChanIdLane*/   
    McMacTxPortMap_t,       /*7 McMac_TxPortMap*/         
    McMacRxChanMap_t,       /*8 McMac_RxChanMap*/         
    McMacCreditCtl_t,       /*9 McMac_cfgTxCreditThrd*/   
    McMacMiiTxCfg_t,        /*10 McMac_cfgMcMacSgmiiTxNotUsePortMap*/
    McMacTxSoftReset_t,     /*11 McMac_cfgMcMacMacTxSoftReset*/
    McMacMiiTxCfg_t,        /*12 McMac_cfgMcMacTxThreshold*/
    McMacMiiRxCfg_t,        /*13 McMac_cfgMcMacMiiSgmiiMod*/
    McMacMiiRxCfg_t,        /*14 McMac_cfgMcMacMiiQsgmiiMod*/
    McMacMiiRxCfg_t,        /*15 McMac_cfgMiiRxSampleCnt*/
    McMacMiiTxCfg_t,        /*16 McMac_cfgMcMacTxReplicateCnt*/
    McMacMiiRxCfg_t,        /*17 McMac_cfgMcMacMiiRxBuffMaxDepth*/
    McMacMacRxCfg_t,        /*18 McMac_cfgMcMacRxUseHataTsEn*/
    McMacMacTxCfg_t,        /*19 McMac_cfgMcMacPmInterval*/
    McMacMacTxCfg_t,        /*20 McMac_cfgMcMacMacTxWaitCaptureTs*/
    McHataEnable_t,         /*21 McHata_cfgHataRsFecMode*/
    McMacMiiRxCfg_t,        /*22 McMac_cfgMcMacMiiRxForceFault*/
    McMacMiiRxCfg_t,        /*23 McMac_cfgMcMacMiiRxLDForceFault*/
};
const uint32 g_mcmac_fld_id_base[McMac_TOTAL_CNT] = {
    McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxSpeed_f         ,    /*0 McMac_cfgMcMacTxSpeed*/   
    McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxAmInsertEn_f    ,    /*1 McMac_cfgTxAmInsertEn*/   
    McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxAmInterval_f    ,    /*2 McMac_cfgTxAmInterval*/   
    McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIpgDelEn_f      ,    /*3 McMac_cfgMcMacTxIpgDelEn*/
    McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxRsFecEn_f       ,    /*4 McMac_cfgTxRsFecEn*/      
    McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxRsFecMode_f     ,    /*5 McMac_cfgTxRsFecMode*/    
    McMacTxChanIdLaneCfg_cfgTxChanIdLane_0_cfgTxChanIdLane_f,    /*6 McMac_cfgTxChanIdLane*/   
    McMacTxPortMap_portMap_f                                ,    /*7 McMac_TxPortMap*/         
    McMacRxChanMap_chanMap_f                                ,    /*8 McMac_RxChanMap*/         
    McMacCreditCtl_cfgTxCreditThrd_0_cfgTxCreditThrd_f      ,    /*9 McMac_cfgTxCreditThrd*/   
    McMacMiiTxCfg_cfgMcMacSgmiiTxNotUsePortMap_f            ,    /*10 McMac_cfgMcMacSgmiiTxNotUsePortMap*/
    McMacTxSoftReset_cfgMcMacMacTxSoftReset_f               ,    /*11 McMac_cfgMcMacMacTxSoftReset*/
    McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxThreshold_f     ,    /*12 McMac_cfgMcMacTxThreshold*/
    McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiSgmiiMod_f     ,    /*13 McMac_cfgMcMacMiiSgmiiMod*/
    McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiQsgmiiMod_f    ,    /*14 McMac_cfgMcMacMiiQsgmiiMod*/
    McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMiiRxSampleCnt_f       ,    /*15 McMac_cfgMiiRxSampleCnt*/
    McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxReplicateCnt_f  ,    /*16 McMac_cfgMcMacTxReplicateCnt*/
    McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxBuffMaxDepth_f,   /*17 McMac_cfgMcMacMiiRxBuffMaxDepth*/
    McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxUseHataTsEn_f   ,    /*18 McMac_cfgMcMacRxUseHataTsEn*/
    McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacPmInterval_f      ,    /*19 McMac_cfgMcMacPmInterval*/
    McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxWaitCaptureTs_f ,    /*20 McMac_cfgMcMacMacTxWaitCaptureTs*/
    McHataEnable_cfgHataRsFecMode0_f                        ,    /*21 McHata_cfgHataRsFecMode*/
    McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault_f ,    /*22 McMac_cfgMcMacMiiRxForceFault*/
    McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkDownForceFault_f,    /*23 McMac_cfgMcMacMiiRxLDForceFault*/
};

const uint32 g_mcmac_field_step[McMac_TOTAL_CNT] = {
    McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxSpeed_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxSpeed_f, /*0 McMac_cfgMcMacTxSpeed*/   
    McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxAmInsertEn_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxAmInsertEn_f, /*1 McMac_cfgTxAmInsertEn*/   
    McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxAmInterval_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxAmInterval_f, /*2 McMac_cfgTxAmInterval*/   
    McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxIpgDelEn_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIpgDelEn_f, /*3 McMac_cfgMcMacTxIpgDelEn*/
    McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxRsFecEn_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxRsFecEn_f, /*4 McMac_cfgTxRsFecEn*/      
    McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxRsFecMode_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxRsFecMode_f, /*5 McMac_cfgTxRsFecMode*/    
    McMacTxChanIdLaneCfg_cfgTxChanIdLane_1_cfgTxChanIdLane_f - McMacTxChanIdLaneCfg_cfgTxChanIdLane_0_cfgTxChanIdLane_f, /*6 McMac_cfgTxChanIdLane*/   
    0, /*7 McMac_TxPortMap*/        
    0, /*8 McMac_RxChanMap*/         
    McMacCreditCtl_cfgTxCreditThrd_1_cfgTxCreditThrd_f - McMacCreditCtl_cfgTxCreditThrd_0_cfgTxCreditThrd_f, /*9 McMac_cfgTxCreditThrd*/     
    0, /*10 McMac_cfgMcMacSgmiiTxNotUsePortMap*/
    0, /*11 McMac_cfgMcMacMacTxSoftReset*/
    McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxThreshold_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxThreshold_f, /*12 McMac_cfgMcMacTxThreshold*/
    McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiSgmiiMod_f - McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiSgmiiMod_f, /*13 McMac_cfgMcMacMiiSgmiiMod*/
    McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiQsgmiiMod_f - McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiQsgmiiMod_f, /*14 McMac_cfgMcMacMiiQsgmiiMod*/
    McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMiiRxSampleCnt_f - McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMiiRxSampleCnt_f, /*15 McMac_cfgMiiRxSampleCnt*/
    McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxReplicateCnt_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxReplicateCnt_f, /*16 McMac_cfgMcMacTxReplicateCnt*/
    McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiRxBuffMaxDepth_f - McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxBuffMaxDepth_f, /*17 McMac_cfgMcMacMiiRxBuffMaxDepth*/
    McMacMacRxCfg_cfgMcMacMacRx_1_cfgMcMacRxUseHataTsEn_f - McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxUseHataTsEn_f, /*18 McMac_cfgMcMacRxUseHataTsEn*/
    McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacPmInterval_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacPmInterval_f, /*19 McMac_cfgMcMacPmInterval*/
    McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxWaitCaptureTs_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxWaitCaptureTs_f, /*20 McMac_cfgMcMacMacTxWaitCaptureTs*/
    McHataEnable_cfgHataRsFecMode1_f - McHataEnable_cfgHataRsFecMode0_f, /*21 McHata_cfgHataRsFecMode*/
    McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiRxForceFault_f - McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault_f, /*22 McMac_cfgMcMacMiiRxForceFault*/
    McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiRxLinkDownForceFault_f - McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkDownForceFault_f, /*23 McMac_cfgMcMacMiiRxLDForceFault*/
};

const uint32 g_mcmac_offset_type[] = {
    OFFSET_TYPE_TXQM_MAC_ID     , /*0 McMac_cfgMcMacTxSpeed*/   
    OFFSET_TYPE_TXQM_MAC_ID     , /*1 McMac_cfgTxAmInsertEn*/   
    OFFSET_TYPE_TXQM_MAC_ID     , /*2 McMac_cfgTxAmInterval*/   
    OFFSET_TYPE_TXQM_MAC_ID     , /*3 McMac_cfgMcMacTxIpgDelEn*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*4 McMac_cfgTxRsFecEn*/      
    OFFSET_TYPE_TXQM_MAC_ID     , /*5 McMac_cfgTxRsFecMode*/    
    OFFSET_TYPE_PHYSICAL_LANE_ID, /*6 McMac_cfgTxChanIdLane*/   
    OFFSET_TYPE_1               , /*7 McMac_TxPortMap*/         
    OFFSET_TYPE_1               , /*8 McMac_RxChanMap*/         
    OFFSET_TYPE_TXQM_MAC_ID     , /*9 McMac_cfgTxCreditThrd*/   
    OFFSET_TYPE_1               , /*10 McMac_cfgMcMacSgmiiTxNotUsePortMap*/
    OFFSET_TYPE_1               , /*11 McMac_cfgMcMacMacTxSoftReset*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*12 McMac_cfgMcMacTxThreshold*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*13 McMac_cfgMcMacMiiSgmiiMod*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*14 McMac_cfgMcMacMiiQsgmiiMod*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*15 McMac_cfgMiiRxSampleCnt*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*16 McMac_cfgMcMacTxReplicateCnt*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*17 McMac_cfgMcMacMiiRxBuffMaxDepth*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*18 McMac_cfgMcMacRxUseHataTsEn*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*19 McMac_cfgMcMacPmInterval*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*20 McMac_cfgMcMacMacTxWaitCaptureTs*/
    OFFSET_TYPE_PCS_ID          , /*21 McHata_cfgHataRsFecMode*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*22 McMac_cfgMcMacMiiRxForceFault*/
    OFFSET_TYPE_TXQM_MAC_ID     , /*23 McMac_cfgMcMacMiiRxLDForceFault*/
};

const uint32 g_mcmac_tbl_idx_type[] = {
    INDEX_TYPE_TXQMID_0    , /*0 McMac_cfgMcMacTxSpeed*/   
    INDEX_TYPE_TXQMID_0    , /*1 McMac_cfgTxAmInsertEn*/   
    INDEX_TYPE_TXQMID_0    , /*2 McMac_cfgTxAmInterval*/   
    INDEX_TYPE_TXQMID_0    , /*3 McMac_cfgMcMacTxIpgDelEn*/
    INDEX_TYPE_TXQMID_0    , /*4 McMac_cfgTxRsFecEn*/      
    INDEX_TYPE_TXQMID_0    , /*5 McMac_cfgTxRsFecMode*/    
    INDEX_TYPE_TXQMID_0    , /*6 McMac_cfgTxChanIdLane*/   
    INDEX_TYPE_TXQMID_MACID, /*7 McMac_TxPortMap*/         
    INDEX_TYPE_TXQMID_PCSID, /*8 McMac_RxChanMap*/         
    INDEX_TYPE_TXQMID_0    , /*9 McMac_cfgTxCreditThrd*/   
    INDEX_TYPE_TXQMID_0    , /*10 McMac_cfgMcMacSgmiiTxNotUsePortMap*/
    INDEX_TYPE_TXQMID_0    , /*11 McMac_cfgMcMacMacTxSoftReset*/
    INDEX_TYPE_TXQMID_0    , /*12 McMac_cfgMcMacTxThreshold*/   
    INDEX_TYPE_TXQMID_0    , /*13 McMac_cfgMcMacMiiSgmiiMod*/
    INDEX_TYPE_TXQMID_0    , /*14 McMac_cfgMcMacMiiQsgmiiMod*/
    INDEX_TYPE_TXQMID_0    , /*15 McMac_cfgMiiRxSampleCnt*/
    INDEX_TYPE_TXQMID_0    , /*16 McMac_cfgMcMacTxReplicateCnt*/
    INDEX_TYPE_TXQMID_0    , /*17 McMac_cfgMcMacMiiRxBuffMaxDepth*/
    INDEX_TYPE_TXQMID_0    , /*18 McMac_cfgMcMacRxUseHataTsEn*/
    INDEX_TYPE_TXQMID_0    , /*19 McMac_cfgMcMacPmInterval*/
    INDEX_TYPE_TXQMID_0    , /*20 McMac_cfgMcMacMacTxWaitCaptureTs*/
    INDEX_TYPE_TXQMID_0    , /*21 McHata_cfgHataRsFecMode*/
    INDEX_TYPE_TXQMID_0    , /*22 McMac_cfgMcMacMiiRxForceFault*/
    INDEX_TYPE_TXQMID_0    , /*23 McMac_cfgMcMacMiiRxLDForceFault*/
};

const uint32 g_mcmac_value_type[] = {
    VALUE_TYPE_NORMAL                 , /*0 McMac_cfgMcMacTxSpeed*/   
    VALUE_TYPE_NORMAL                 , /*1 McMac_cfgTxAmInsertEn*/   
    VALUE_TYPE_NORMAL                 , /*2 McMac_cfgTxAmInterval*/   
    VALUE_TYPE_NORMAL                 , /*3 McMac_cfgMcMacTxIpgDelEn*/
    VALUE_TYPE_NORMAL                 , /*4 McMac_cfgTxRsFecEn*/      
    VALUE_TYPE_NORMAL                 , /*5 McMac_cfgTxRsFecMode*/    
    VALUE_TYPE_TXQM_INNER_MAC_ID      , /*6 McMac_cfgTxChanIdLane*/   
    VALUE_TYPE_PCS_ID                 , /*7 McMac_TxPortMap*/         
    VALUE_TYPE_TXQM_INNER_MAC_ID      , /*8 McMac_RxChanMap*/         
    VALUE_TYPE_NORMAL                 , /*9 McMac_cfgTxCreditThrd*/   
    VALUE_TYPE_PCSX_BASED_1           , /*10 McMac_cfgMcMacSgmiiTxNotUsePortMap*/
    VALUE_TYPE_MAC_ID_BMP             , /*11 McMac_cfgMcMacMacTxSoftReset*/
    VALUE_TYPE_NORMAL                 , /*12 McMac_cfgMcMacTxThreshold*/
    VALUE_TYPE_NORMAL                 , /*13 McMac_cfgMcMacMiiSgmiiMod*/
    VALUE_TYPE_NORMAL                 , /*14 McMac_cfgMcMacMiiQsgmiiMod*/
    VALUE_TYPE_NORMAL                 , /*15 McMac_cfgMiiRxSampleCnt*/
    VALUE_TYPE_NORMAL                 , /*16 McMac_cfgMcMacTxReplicateCnt*/
    VALUE_TYPE_NORMAL                 , /*17 McMac_cfgMcMacMiiRxBuffMaxDepth*/
    VALUE_TYPE_NORMAL                 , /*18 McMac_cfgMcMacRxUseHataTsEn*/
    VALUE_TYPE_NORMAL                 , /*19 McMac_cfgMcMacPmInterval*/
    VALUE_TYPE_NORMAL                 , /*20 McMac_cfgMcMacMacTxWaitCaptureTs*/
    VALUE_TYPE_NORMAL                 , /*21 McHata_cfgHataRsFecMode*/
    VALUE_TYPE_NORMAL                 , /*22 McMac_cfgMcMacMiiRxForceFault*/
    VALUE_TYPE_NORMAL                 , /*23 McMac_cfgMcMacMiiRxLDForceFault*/
};

const uint32 g_mcmac_mode_value_map[McMac_TOTAL_CNT][CTC_CHIP_MAX_SERDES_MODE] = 
{
  /*NONE XFI SGMII NONE QSGMII NONE NONE XLG   CG     2.5G NONE NONE NONE XXVG LG     NONE LG_R1  CG_R2  CCG_R4 CDG_R8*/
    {0,  5,  2,    0,   2,     0,   0,   7,    9,     2,   0,   0,   0,   6,   8,     0,   8,     9,     10,    11   }, /*0 McMac_cfgMcMacTxSpeed*/   
    {0,  0,  0,    0,   0,     0,   0,   1,    1,     0,   0,   0,   0,   0,   1,     0,   1,     1,     1,     1    }, /*1 McMac_cfgTxAmInsertEn*/   
    {0,  0,  0,    0,   0,     0,   0,   8191, 40959, 0,   0,   0,   0,   0,   8191,  0,   10239, 40959, 40959, 81919}, /*2 McMac_cfgTxAmInterval*/   
    {0,  1,  1,    0,   1,     0,   0,   1,    1,     1,   0,   0,   0,   1,   1,     0,   1,     1,     1,     1    }, /*3 McMac_cfgMcMacTxIpgDelEn*/
    {0,  0,  0,    0,   0,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     1,     1    }, /*4 McMac_cfgTxRsFecEn*/      
    {0,  0,  0,    0,   0,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     1,     1    }, /*5 McMac_cfgTxRsFecMode*/    
    {0,  0,  0,    0,   0,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     0,     0    }, /*6 McMac_cfgTxChanIdLane*/   
    {0,  0,  0,    0,   0,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     0,     0    }, /*7 McMac_TxPortMap*/         
    {0,  0,  0,    0,   0,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     0,     0    }, /*8 McMac_RxChanMap*/         
    {0,  24, 64,   0,   64,    0,   0,   54,   64,    64,  0,   0,   0,   24,  54,    0,   24,    44,    120,   192  }, /*9 McMac_cfgTxCreditThrd*/    
    {0,  0,  0,    0,   0,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     0,     0    }, /*10 McMac_cfgMcMacSgmiiTxNotUsePortMap*/
    {0,  0,  0,    0,   0,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     0,     0    }, /*11 McMac_cfgMcMacMacTxSoftReset*/
    {0,  2,  0,    0,   0,     0,   0,   2,    2,     0,   0,   0,   0,   2,   2,     0,   2,     2,     2,     2    }, /*12 McMac_cfgMcMacTxThreshold*/
    {0,  0,  1,    0,   0,     0,   0,   0,    0,     1,   0,   0,   0,   0,   0,     0,   0,     0,     0,     0    }, /*13 McMac_cfgMcMacMiiSgmiiMod*/
    {0,  0,  0,    0,   1,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     0,     0    }, /*14 McMac_cfgMcMacMiiQsgmiiMod*/
    {0,  0,  0,    0,   0,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     0,     0    }, /*15 McMac_cfgMiiRxSampleCnt*/
    {0,  0,  0,    0,   0,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     0,     0    }, /*16 McMac_cfgMcMacTxReplicateCnt*/
    {160,8,  8,    160, 8,     160, 160, 16,   32,    8,   160, 160, 160, 8,   16,    160, 16,    32,    64,    128  }, /*17 McMac_cfgMcMacMiiRxBuffMaxDepth*/
    {1,  1,  1,    1,   0,     1,   1,   1,    1,     1,   1,   1,   1,   1,   1,     1,   1,     1,     1,     1    }, /*18 McMac_cfgMcMacRxUseHataTsEn*/
    {0, 2047,2047, 0,   2047,  0,   0,   8191, 40959, 2047,0,   0,   0,   2047,8191,  0,   10239, 40959, 40959, 81919}, /*19 McMac_cfgMcMacPmInterval*/
    {1,  1,  1,    1,   0,     1,   1,   1,    1,     1,   1,   1,   1,   1,   1,     1,   1,     1,     1,     1    }, /*20 McMac_cfgMcMacMacTxWaitCaptureTs*/
    {0,  0,  0,    0,   0,     0,   0,   0,    0,     0,   0,   0,   0,   0,   0,     0,   0,     0,     0,     0    }, /*21 McHata_cfgHataRsFecMode*/
    {0,  1,  0,    0,   0,     0,   0,   1,    1,     0,   0,   0,   0,   1,   1,     0,   1,     1,     1,     1    }, /*22 McMac_cfgMcMacMiiRxForceFault*/
    {0,  1,  0,    0,   0,     0,   0,   1,    1,     0,   0,   0,   0,   1,   1,     0,   1,     1,     1,     1    }, /*23 McMac_cfgMcMacMiiRxLDForceFault*/
};

const uint32 g_mcmac_fec_value_map[McMac_TOTAL_CNT][MAX_MODE_FEC] = 
{
   /*XFI_FC2112,  XXVG_FC2112, XXVG_RS528,  XLG_FC2112,  LG_R2_RS528, LG_R2_RS544,  LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272, 
    CG_R4_RS528, CG_R4_RS544, CG_R2_RS528, CG_R2_RS544, CG_R2_RS272, CCG_R4_RS544, CCG_R4_RS272, CDG_R8_RS544, CDG_R8_RS272*/
    {5,           6,           6,           7,           8,           8,            8,            8,            8,          
    9,           9,           9,           9,           9,           10,           10,           11,           11   }, /*0 McMac_cfgMcMacTxSpeed*/   
    {0,           0,           1,           1,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*1 McMac_cfgTxAmInsertEn*/   
    {0,           0,           10239,       8191,        10239,       10239,        10239,        10239,        10239,      
    40959,       40959,       40959,       40959,       40959,       40959,        40959,        81919,        81919}, /*2 McMac_cfgTxAmInterval*/   
    {1,           1,           1,           1,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*3 McMac_cfgMcMacTxIpgDelEn*/
    {0,           0,           1,           0,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*4 McMac_cfgTxRsFecEn*/      
    {0,           0,           2,           0,           2,           1,            2,            1,            3,          
    2,           1,           2,           1,           3,           1,            3,            1,            3    }, /*5 McMac_cfgTxRsFecMode*/    
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*6 McMac_cfgTxChanIdLane*/   
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*7 McMac_TxPortMap*/         
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*8 McMac_RxChanMap*/         
    {16,          24,          24,          54,          54,          54,           32,           28,           32,         
    64,          64,          48,          48,          48,          120,          120,          192,          192  }, /*9 McMac_cfgTxCreditThrd*/   
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*10 McMac_cfgMcMacSgmiiTxNotUsePortMap*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*11 McMac_cfgMcMacMacTxSoftReset*/
    {2,           2,           2,           2,           2,           2,            2,            2,            2,          
    2,           2,           2,           2,           2,           2,            2,            2,            2    }, /*12 McMac_cfgMcMacTxThreshold*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*13 McMac_cfgMcMacMiiSgmiiMod*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*14 McMac_cfgMcMacMiiQsgmiiMod*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*15 McMac_cfgMiiRxSampleCnt*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*16 McMac_cfgMcMacTxReplicateCnt*/
    {8,           8,           8,           16,          16,          16,           16,           16,           16,         
    32,          32,          32,          32,          32,          64,           64,           128,          128  }, /*17 McMac_cfgMcMacMiiRxBuffMaxDepth*/
    {0,           0,           1,           0,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*18 McMac_cfgMcMacRxUseHataTsEn*/
    {2047,        2047,        10239,       8191,        10239,       10239,        10239,        10239,        10239, 
    40959,       40959,       40959,       40959,       40959,       40959,        40959,        81919,        81919}, /*19 McMac_cfgMcMacPmInterval*/
    {1,           1,           1,           1,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*20 McMac_cfgMcMacMacTxWaitCaptureTs*/
    {0,           0,           2,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*21 McHata_cfgHataRsFecMode*/
    {1,           1,           1,           1,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*22 McMac_cfgMcMacMiiRxForceFault*/
    {1,           1,           1,           1,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*23 McMac_cfgMcMacMiiRxLDForceFault*/
};

/************************* McPcs info resgiter tables *************************/
const uint32 g_mcpcs_cfg_flag_x8[McPcs_TOTAL_CNT] = {
    ITEM_NO_WRITE       , /*0  logic_lane_num          */
    ITEM_NO_WRITE       , /*1  McPcs_SoftRstRxMcFec    */
    ITEM_NO_WRITE       , /*2  McPcs_SoftRstTxMcFec    */
    ITEM_NO_WRITE       , /*3  McPcs_LaneInit          */
    ITEM_WRITE_VARY     , /*4  McPcs_cfgRxGearboxMode  */
    ITEM_WRITE_VARY     , /*5  McPcs_cfgRxChanId       */
    ITEM_WRITE_VARY     , /*6  McPcs_cfgRxSpeed        */
    ITEM_WRITE_VARY     , /*7  McPcs_cfgRxDskMaxAddr   */
    ITEM_NO_WRITE       , /*8  McPcs_cfgRxLaneswapId   */
    ITEM_WRITE_VARY     , /*9  McPcs_cfgRxAmInterval   */
    ITEM_WRITE_VARY     , /*10 McPcs_cfgRxIsPam4       */
    ITEM_WRITE_VARY     , /*11 McPcs_cfgRxSelRsFec     */
    ITEM_WRITE_VARY     , /*12 McPcs_cfgRxSelFcFec     */
    ITEM_WRITE_CONST    , /*13 McPcs_cfgRxFecMode      */
    ITEM_WRITE_VARY     , /*14 McPcs_cfgTxChanId       */
    ITEM_WRITE_VARY     , /*15 McPcs_cfgTxLaneId       */
    ITEM_WRITE_VARY     , /*16 McPcs_cfgTxPcsMode      */
    ITEM_WRITE_ON_READ  , /*17 McPcs_cfgTxChanIsPam4   */
    ITEM_WRITE_VARY     , /*18 McPcs_cfgTxGearboxMode  */
    ITEM_WRITE_VARY     , /*19 McPcs_cfgTxBufThrd      */
    ITEM_WRITE_VARY     , /*20 McPcs_cfgTxFifoAFullThrd*/
    ITEM_WRITE_CONST    , /*21 McPcs_cfgTxRsFecModeSel */
    ITEM_NO_WRITE       , /*22 McPcs_resetQsgmii_resetCore*/
    ITEM_NO_WRITE       , /*23 McPcs_cfgSgmii_unidirectionEn*/
    ITEM_WRITE_CONST    , /*24 McPcs_cfgSgmii_anEnable*/
    ITEM_WRITE_CONST    , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    ITEM_NO_WRITE       , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    ITEM_NO_WRITE       , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    ITEM_NO_WRITE       , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    ITEM_NO_WRITE       , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    ITEM_WRITE_CONST    , /*30 McPcs_cfgTxDoneMode*/
    ITEM_NO_WRITE       , /*31 McPcs_cfgTxPrimingThrd*/
    ITEM_WRITE_CONST    , /*32 McPcs_cfgRxSgmiiMode*/
    ITEM_WRITE_CONST    , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_tbl_id_base_x8[McPcs_TOTAL_CNT] = {
    0                             , /*0  logic_lane_num          */
    McPcsX8LanesMcFecCfg_t        , /*1  McPcs_SoftRstRxMcFec    */
    McPcsX8LanesMcFecCfg_t        , /*2  McPcs_SoftRstTxMcFec    */
    McPcsX8LanesInit_t            , /*3  McPcs_LaneInit          */
    McPcsX8LanesRxPhyLaneCfg_t    , /*4  McPcs_cfgRxGearboxMode  */
    McPcsX8LanesRxPhyLaneCfg_t    , /*5  McPcs_cfgRxChanId       */
    McPcsX8LanesRxLaneCfg_t       , /*6  McPcs_cfgRxSpeed        */
    McPcsX8LanesRxLaneCfg_t       , /*7  McPcs_cfgRxDskMaxAddr   */
    McPcsX8LanesRxLaneSwapCfg_t   , /*8  McPcs_cfgRxLaneswapId   */
    McPcsX8LanesRxLaneLockCfg_t   , /*9  McPcs_cfgRxAmInterval   */
    McPcsX8LanesRxPam4EnCfg_t     , /*10 McPcs_cfgRxIsPam4       */
    McPcsX8LanesRxLaneModeCfg_t   , /*11 McPcs_cfgRxSelRsFec     */
    McPcsX8LanesRxLaneModeCfg_t   , /*12 McPcs_cfgRxSelFcFec     */
    McPcsX8LanesRxChanDskCfg_t    , /*13 McPcs_cfgRxFecMode      */
    McPcsX8LanesTxLaneMapCfg_t    , /*14 McPcs_cfgTxChanId       */
    McPcsX8LanesTxLaneMapCfg_t    , /*15 McPcs_cfgTxLaneId       */
    McPcsX8LanesTxLaneMapCfg_t    , /*16 McPcs_cfgTxPcsMode      */
    McPcsX8LanesTxPam4EnCfg_t     , /*17 McPcs_cfgTxChanIsPam4   */
    McPcsX8LanesTxLaneGearboxCfg_t, /*18 McPcs_cfgTxGearboxMode  */
    McPcsX8LanesTxLaneGearboxCfg_t, /*19 McPcs_cfgTxBufThrd      */
    McPcsX8LanesTxLaneGearboxCfg_t, /*20 McPcs_cfgTxFifoAFullThrd*/
    McPcsX8LanesTxMiscCfg_t       , /*21 McPcs_cfgTxRsFecModeSel */
    0                             , /*22 McPcs_resetQsgmii_resetCore*/
    McPcsX8LanesSgmiiCfg_t        , /*23 McPcs_cfgSgmii_unidirectionEn*/
    McPcsX8LanesSgmiiCfg_t        , /*24 McPcs_cfgSgmii_anEnable*/
    0                             , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    0                             , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    0                             , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    0                             , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    0                             , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    McPcsX8LanesTxLaneMapCfg_t    , /*30 McPcs_cfgTxDoneMode*/
    0                             , /*31 McPcs_cfgTxPrimingThrd*/
    McPcsX8LanesRxPhyLaneCfg_t    , /*32 McPcs_cfgRxSgmiiMode*/
    McPcsX8LanesSgmiiCfg_t        , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_fld_id_base_x8[McPcs_TOTAL_CNT] = {
    0                                                                   , /*0  logic_lane_num          */
    McPcsX8LanesMcFecCfg_cfgSoftRstRxMcFec_f                            , /*1  McPcs_SoftRstRxMcFec    */
    McPcsX8LanesMcFecCfg_cfgSoftRstTxMcFec_f                            , /*2  McPcs_SoftRstTxMcFec    */
    McPcsX8LanesInit_init_f                                             , /*3  McPcs_LaneInit          */
    McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_0_cfgRxGearboxMode_f          , /*4  McPcs_cfgRxGearboxMode  */
    McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f               , /*5  McPcs_cfgRxChanId       */
    McPcsX8LanesRxLaneCfg_cfgRxLane_0_cfgRxSpeed_f                      , /*6  McPcs_cfgRxSpeed        */
    McPcsX8LanesRxLaneCfg_cfgRxLane_0_cfgRxDskMaxAddr_f                 , /*7  McPcs_cfgRxDskMaxAddr   */
    McPcsX8LanesRxLaneSwapCfg_cfgRxSwapLane_0_cfgRxLaneId_f             , /*8  McPcs_cfgRxLaneswapId   */
    McPcsX8LanesRxLaneLockCfg_cfgRxLockLane_0_cfgRxAmInterval_f         , /*9  McPcs_cfgRxAmInterval   */
    McPcsX8LanesRxPam4EnCfg_cfgRxPam4En_0_cfgRxIsPam4_f                 , /*10 McPcs_cfgRxIsPam4       */
    McPcsX8LanesRxLaneModeCfg_cfgRxLaneMode_0_cfgRxSelRsFec_f           , /*11 McPcs_cfgRxSelRsFec     */
    McPcsX8LanesRxLaneModeCfg_cfgRxLaneMode_0_cfgRxSelFcFec_f           , /*12 McPcs_cfgRxSelFcFec     */
    McPcsX8LanesRxChanDskCfg_cfgRxDskChan_0_cfgRxFecMode_f              , /*13 McPcs_cfgRxFecMode      */
    McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f           , /*14 McPcs_cfgTxChanId       */
    McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxLaneId_f           , /*15 McPcs_cfgTxLaneId       */
    McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxPcsMode_f          , /*16 McPcs_cfgTxPcsMode      */
    McPcsX8LanesTxPam4EnCfg_cfgTxChanIsPam4Bmp_f                        , /*17 McPcs_cfgTxChanIsPam4   */
    McPcsX8LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxGearboxMode_f  , /*18 McPcs_cfgTxGearboxMode  */
    McPcsX8LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxBufThrd_f      , /*19 McPcs_cfgTxBufThrd      */
    McPcsX8LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxFifoAFullThrd_f, /*20 McPcs_cfgTxFifoAFullThrd*/ 
    McPcsX8LanesTxMiscCfg_cfgTxRsFecModeSel_f                           , /*21 McPcs_cfgTxRsFecModeSel */
    0                                                                   , /*22 McPcs_resetQsgmii_resetCore*/
    McPcsX8LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f                    , /*23 McPcs_cfgSgmii_unidirectionEn*/
    McPcsX8LanesSgmiiCfg_cfgSgmii_0_anEnable_f                          , /*24 McPcs_cfgSgmii_anEnable*/
    0                                                                   , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    0                                                                   , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    0                                                                   , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    0                                                                   , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    0                                                                   , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxDoneMode_f         , /*30 McPcs_cfgTxDoneMode*/
    0                                                                   , /*31 McPcs_cfgTxPrimingThrd*/
    McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_0_cfgRxSgmiiMode_f            , /*32 McPcs_cfgRxSgmiiMode*/
    McPcsX8LanesSgmiiCfg_cfgSgmii_0_txXmitLoadUseAsyncFifo_f            , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_field_step_x8[McPcs_TOTAL_CNT] = {
    0                                                                                                                                          , /*0  logic_lane_num          */
    0                                                                                                                                          , /*1  McPcs_SoftRstRxMcFec    */
    0                                                                                                                                          , /*2  McPcs_SoftRstTxMcFec    */
    0                                                                                                                                          , /*3  McPcs_LaneInit          */
    McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_1_cfgRxGearboxMode_f - McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_0_cfgRxGearboxMode_f                    , /*4  McPcs_cfgRxGearboxMode  */
    McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_1_cfgRxChanId_f - McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f                              , /*5  McPcs_cfgRxChanId       */
    McPcsX8LanesRxLaneCfg_cfgRxLane_1_cfgRxSpeed_f - McPcsX8LanesRxLaneCfg_cfgRxLane_0_cfgRxSpeed_f                                            , /*6  McPcs_cfgRxSpeed        */
    McPcsX8LanesRxLaneCfg_cfgRxLane_1_cfgRxDskMaxAddr_f - McPcsX8LanesRxLaneCfg_cfgRxLane_0_cfgRxDskMaxAddr_f                                  , /*7  McPcs_cfgRxDskMaxAddr   */
    McPcsX8LanesRxLaneSwapCfg_cfgRxSwapLane_1_cfgRxLaneId_f - McPcsX8LanesRxLaneSwapCfg_cfgRxSwapLane_0_cfgRxLaneId_f                          , /*8  McPcs_cfgRxLaneswapId   */
    McPcsX8LanesRxLaneLockCfg_cfgRxLockLane_1_cfgRxAmInterval_f - McPcsX8LanesRxLaneLockCfg_cfgRxLockLane_0_cfgRxAmInterval_f                  , /*9  McPcs_cfgRxAmInterval   */
    McPcsX8LanesRxPam4EnCfg_cfgRxPam4En_1_cfgRxIsPam4_f - McPcsX8LanesRxPam4EnCfg_cfgRxPam4En_0_cfgRxIsPam4_f                                  , /*10 McPcs_cfgRxIsPam4       */
    McPcsX8LanesRxLaneModeCfg_cfgRxLaneMode_1_cfgRxSelRsFec_f - McPcsX8LanesRxLaneModeCfg_cfgRxLaneMode_0_cfgRxSelRsFec_f                      , /*11 McPcs_cfgRxSelRsFec     */
    McPcsX8LanesRxLaneModeCfg_cfgRxLaneMode_1_cfgRxSelFcFec_f - McPcsX8LanesRxLaneModeCfg_cfgRxLaneMode_0_cfgRxSelFcFec_f                      , /*12 McPcs_cfgRxSelFcFec     */
    McPcsX8LanesRxChanDskCfg_cfgRxDskChan_1_cfgRxFecMode_f - McPcsX8LanesRxChanDskCfg_cfgRxDskChan_0_cfgRxFecMode_f                            , /*13 McPcs_cfgRxFecMode      */
    McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxChanId_f - McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f                      , /*14 McPcs_cfgTxChanId       */
    McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxLaneId_f - McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxLaneId_f                      , /*15 McPcs_cfgTxLaneId       */
    McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxPcsMode_f - McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxPcsMode_f                    , /*16 McPcs_cfgTxPcsMode      */
    0                                                                                                                                          , /*17 McPcs_cfgTxChanIsPam4   */
    McPcsX8LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxGearboxMode_f - McPcsX8LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxGearboxMode_f    , /*18 McPcs_cfgTxGearboxMode  */
    McPcsX8LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxBufThrd_f - McPcsX8LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxBufThrd_f            , /*19 McPcs_cfgTxBufThrd      */
    McPcsX8LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxFifoAFullThrd_f - McPcsX8LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxFifoAFullThrd_f, /*20 McPcs_cfgTxFifoAFullThrd*/
    0                                                                                                                                          , /*21 McPcs_cfgTxRsFecModeSel */
    0                                                                                                                                          , /*22 McPcs_resetQsgmii_resetCore*/
    McPcsX8LanesSgmiiCfg_cfgSgmii_1_unidirectionEn_f - McPcsX8LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f                                        , /*23 McPcs_cfgSgmii_unidirectionEn*/
    McPcsX8LanesSgmiiCfg_cfgSgmii_1_anEnable_f - McPcsX8LanesSgmiiCfg_cfgSgmii_0_anEnable_f                                                    , /*24 McPcs_cfgSgmii_anEnable*/
    0                                                                                                                                          , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    0                                                                                                                                          , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    0                                                                                                                                          , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    0                                                                                                                                          , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    0                                                                                                                                          , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxDoneMode_f - McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxDoneMode_f                  , /*30 McPcs_cfgTxDoneMode*/
    0                                                                                                                                          , /*31 McPcs_cfgTxPrimingThrd*/
    McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_1_cfgRxSgmiiMode_f - McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_0_cfgRxSgmiiMode_f                        , /*32 McPcs_cfgRxSgmiiMode*/
    McPcsX8LanesSgmiiCfg_cfgSgmii_1_txXmitLoadUseAsyncFifo_f - McPcsX8LanesSgmiiCfg_cfgSgmii_0_txXmitLoadUseAsyncFifo_f                        , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_cfg_flag_x16[McPcs_TOTAL_CNT] = {
    ITEM_NO_WRITE       , /*0  logic_lane_num          */
    ITEM_NO_WRITE       , /*1  McPcs_SoftRstRxMcFec    */
    ITEM_NO_WRITE       , /*2  McPcs_SoftRstTxMcFec    */
    ITEM_NO_WRITE       , /*3  McPcs_LaneInit          */
    ITEM_WRITE_VARY     , /*4  McPcs_cfgRxGearboxMode  */
    ITEM_WRITE_VARY     , /*5  McPcs_cfgRxChanId       */
    ITEM_WRITE_VARY     , /*6  McPcs_cfgRxSpeed        */
    ITEM_WRITE_VARY     , /*7  McPcs_cfgRxDskMaxAddr   */
    ITEM_NO_WRITE       , /*8  McPcs_cfgRxLaneswapId   */
    ITEM_WRITE_VARY     , /*9  McPcs_cfgRxAmInterval   */
    ITEM_WRITE_VARY     , /*10 McPcs_cfgRxIsPam4       */
    ITEM_WRITE_VARY     , /*11 McPcs_cfgRxSelRsFec     */
    ITEM_WRITE_VARY     , /*12 McPcs_cfgRxSelFcFec     */
    ITEM_WRITE_CONST    , /*13 McPcs_cfgRxFecMode      */
    ITEM_WRITE_VARY     , /*14 McPcs_cfgTxChanId       */
    ITEM_WRITE_VARY     , /*15 McPcs_cfgTxLaneId       */
    ITEM_WRITE_VARY     , /*16 McPcs_cfgTxPcsMode      */
    ITEM_WRITE_ON_READ  , /*17 McPcs_cfgTxChanIsPam4   */
    ITEM_WRITE_VARY     , /*18 McPcs_cfgTxGearboxMode  */
    ITEM_WRITE_VARY     , /*19 McPcs_cfgTxBufThrd      */
    ITEM_WRITE_VARY     , /*20 McPcs_cfgTxFifoAFullThrd*/
    ITEM_WRITE_CONST    , /*21 McPcs_cfgTxRsFecModeSel */
    ITEM_WRITE_CONST    , /*22 McPcs_resetQsgmii_resetCore*/
    ITEM_WRITE_CONST    , /*23 McPcs_cfgSgmii_unidirectionEn*/
    ITEM_WRITE_CONST    , /*24 McPcs_cfgSgmii_anEnable*/
    ITEM_WRITE_CONST    , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    ITEM_WRITE_CONST    , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    ITEM_WRITE_CONST    , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    ITEM_WRITE_CONST    , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    ITEM_WRITE_CONST    , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    ITEM_WRITE_CONST    , /*30 McPcs_cfgTxDoneMode*/
    ITEM_WRITE_CONST    , /*31 McPcs_cfgTxPrimingThrd*/
    ITEM_WRITE_CONST    , /*32 McPcs_cfgRxSgmiiMode*/
    ITEM_WRITE_CONST    , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_tbl_id_base_x16a[McPcs_TOTAL_CNT] = {
    0                              , /*0  logic_lane_num          */
    McPcsX16LanesMcFecCfg_t        , /*1  McPcs_SoftRstRxMcFec    */
    McPcsX16LanesMcFecCfg_t        , /*2  McPcs_SoftRstTxMcFec    */
    McPcsX16LanesInit_t            , /*3  McPcs_LaneInit          */
    McPcsX16LanesRxAPhyLaneCfg_t   , /*4  McPcs_cfgRxGearboxMode  */
    McPcsX16LanesRxAPhyLaneCfg_t   , /*5  McPcs_cfgRxChanId       */
    McPcsX16LanesRxALaneCfg_t      , /*6  McPcs_cfgRxSpeed        */
    McPcsX16LanesRxALaneCfg_t      , /*7  McPcs_cfgRxDskMaxAddr   */
    McPcsX16LanesRxALaneSwapCfg_t  , /*8  McPcs_cfgRxLaneswapId   */
    McPcsX16LanesRxALaneLockCfg_t  , /*9  McPcs_cfgRxAmInterval   */
    McPcsX16LanesRxAPam4EnCfg_t    , /*10 McPcs_cfgRxIsPam4       */
    McPcsX16LanesRxALaneModeCfg_t  , /*11 McPcs_cfgRxSelRsFec     */
    McPcsX16LanesRxALaneModeCfg_t  , /*12 McPcs_cfgRxSelFcFec     */
    McPcsX16LanesRxAChanDskCfg_t   , /*13 McPcs_cfgRxFecMode      */
    McPcsX16LanesTxLaneMapCfg_t    , /*14 McPcs_cfgTxChanId       */
    McPcsX16LanesTxLaneMapCfg_t    , /*15 McPcs_cfgTxLaneId       */
    McPcsX16LanesTxLaneMapCfg_t    , /*16 McPcs_cfgTxPcsMode      */
    McPcsX16LanesTxPam4EnCfg_t     , /*17 McPcs_cfgTxChanIsPam4   */
    McPcsX16LanesTxLaneGearboxCfg_t, /*18 McPcs_cfgTxGearboxMode  */
    McPcsX16LanesTxLaneGearboxCfg_t, /*19 McPcs_cfgTxBufThrd      */
    McPcsX16LanesTxLaneGearboxCfg_t, /*20 McPcs_cfgTxFifoAFullThrd*/
    McPcsX16LanesTxMiscCfg_t       , /*21 McPcs_cfgTxRsFecModeSel */
    McPcsX16LanesQsgmiiReset_t     , /*22 McPcs_resetQsgmii_resetCore*/
    McPcsX16LanesSgmiiCfg_t        , /*23 McPcs_cfgSgmii_unidirectionEn*/
    McPcsX16LanesSgmiiCfg_t        , /*24 McPcs_cfgSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_t       , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    McPcsX16LanesQsgmiiCfg_t       , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_t       , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    McPcsX16LanesQsgmiiCfg_t       , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    McPcsX16LanesQsgmiiCfg_t       , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    McPcsX16LanesTxLaneMapCfg_t    , /*30 McPcs_cfgTxDoneMode*/
    McPcsX16LanesTxLaneGearboxCfg_t, /*31 McPcs_cfgTxPrimingThrd*/
    McPcsX16LanesRxAPhyLaneCfg_t   , /*32 McPcs_cfgRxSgmiiMode*/
    McPcsX16LanesSgmiiCfg_t        , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_fld_id_base_x16a[McPcs_TOTAL_CNT] = {
    0                                                                    , /*0  logic_lane_num          */
    McPcsX16LanesMcFecCfg_cfgSoftRstRxMcFec_f                            , /*1  McPcs_SoftRstRxMcFec    */
    McPcsX16LanesMcFecCfg_cfgSoftRstTxMcFec_f                            , /*2  McPcs_SoftRstTxMcFec    */
    McPcsX16LanesInit_init_f                                             , /*3  McPcs_LaneInit          */
    McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_0_cfgRxGearboxMode_f         , /*4  McPcs_cfgRxGearboxMode  */
    McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f              , /*5  McPcs_cfgRxChanId       */
    McPcsX16LanesRxALaneCfg_cfgRxLane_0_cfgRxSpeed_f                     , /*6  McPcs_cfgRxSpeed        */
    McPcsX16LanesRxALaneCfg_cfgRxLane_0_cfgRxDskMaxAddr_f                , /*7  McPcs_cfgRxDskMaxAddr   */
    McPcsX16LanesRxALaneSwapCfg_cfgRxSwapLane_0_cfgRxLaneId_f            , /*8  McPcs_cfgRxLaneswapId   */
    McPcsX16LanesRxALaneLockCfg_cfgRxLockLane_0_cfgRxAmInterval_f        , /*9  McPcs_cfgRxAmInterval   */
    McPcsX16LanesRxAPam4EnCfg_cfgRxPam4En_0_cfgRxIsPam4_f                , /*10 McPcs_cfgRxIsPam4       */
    McPcsX16LanesRxALaneModeCfg_cfgRxLaneMode_0_cfgRxSelRsFec_f          , /*11 McPcs_cfgRxSelRsFec     */
    McPcsX16LanesRxALaneModeCfg_cfgRxLaneMode_0_cfgRxSelFcFec_f          , /*12 McPcs_cfgRxSelFcFec     */
    McPcsX16LanesRxAChanDskCfg_cfgRxDskChan_0_cfgRxFecMode_f             , /*13 McPcs_cfgRxFecMode      */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f           , /*14 McPcs_cfgTxChanId       */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxLaneId_f           , /*15 McPcs_cfgTxLaneId       */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxPcsMode_f          , /*16 McPcs_cfgTxPcsMode      */
    McPcsX16LanesTxPam4EnCfg_cfgTxChanIsPam4Bmp_f                        , /*17 McPcs_cfgTxChanIsPam4   */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxGearboxMode_f  , /*18 McPcs_cfgTxGearboxMode  */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxBufThrd_f      , /*19 McPcs_cfgTxBufThrd      */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxFifoAFullThrd_f, /*20 McPcs_cfgTxFifoAFullThrd*/ 
    McPcsX16LanesTxMiscCfg_cfgTxRsFecModeSel_f                           , /*21 McPcs_cfgTxRsFecModeSel */
    McPcsX16LanesQsgmiiReset_resetQsgmii_0_resetCore_f                   , /*22 McPcs_resetQsgmii_resetCore*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f                    , /*23 McPcs_cfgSgmii_unidirectionEn*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_0_anEnable_f                          , /*24 McPcs_cfgSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_unidirectionEn_f             , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anEnable_f                   , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anegMode_f                   , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmii_0_cfgTxCreditThrd_f                 , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmii_0_reAlignEachEn_f                   , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxDoneMode_f         , /*30 McPcs_cfgTxDoneMode*/
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxPrimingThrd_f  , /*31 McPcs_cfgTxPrimingThrd*/
    McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_0_cfgRxSgmiiMode_f           , /*32 McPcs_cfgRxSgmiiMode*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_0_txXmitLoadUseAsyncFifo_f            , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_field_step_x16a[McPcs_TOTAL_CNT] = {
    0                                                                                                                                            , /*0  logic_lane_num          */
    0                                                                                                                                            , /*1  McPcs_SoftRstRxMcFec    */
    0                                                                                                                                            , /*2  McPcs_SoftRstTxMcFec    */
    0                                                                                                                                            , /*3  McPcs_LaneInit          */
    McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_1_cfgRxGearboxMode_f - McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_0_cfgRxGearboxMode_f                  , /*4  McPcs_cfgRxGearboxMode  */
    McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_1_cfgRxChanId_f - McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f                            , /*5  McPcs_cfgRxChanId       */
    McPcsX16LanesRxALaneCfg_cfgRxLane_1_cfgRxSpeed_f - McPcsX16LanesRxALaneCfg_cfgRxLane_0_cfgRxSpeed_f                                          , /*6  McPcs_cfgRxSpeed        */
    McPcsX16LanesRxALaneCfg_cfgRxLane_1_cfgRxDskMaxAddr_f - McPcsX16LanesRxALaneCfg_cfgRxLane_0_cfgRxDskMaxAddr_f                                , /*7  McPcs_cfgRxDskMaxAddr   */
    McPcsX16LanesRxALaneSwapCfg_cfgRxSwapLane_1_cfgRxLaneId_f - McPcsX16LanesRxALaneSwapCfg_cfgRxSwapLane_0_cfgRxLaneId_f                        , /*8  McPcs_cfgRxLaneswapId   */
    McPcsX16LanesRxALaneLockCfg_cfgRxLockLane_1_cfgRxAmInterval_f - McPcsX16LanesRxALaneLockCfg_cfgRxLockLane_0_cfgRxAmInterval_f                , /*9  McPcs_cfgRxAmInterval   */
    McPcsX16LanesRxAPam4EnCfg_cfgRxPam4En_1_cfgRxIsPam4_f - McPcsX16LanesRxAPam4EnCfg_cfgRxPam4En_0_cfgRxIsPam4_f                                , /*10 McPcs_cfgRxIsPam4       */
    McPcsX16LanesRxALaneModeCfg_cfgRxLaneMode_1_cfgRxSelRsFec_f - McPcsX16LanesRxALaneModeCfg_cfgRxLaneMode_0_cfgRxSelRsFec_f                    , /*11 McPcs_cfgRxSelRsFec     */
    McPcsX16LanesRxALaneModeCfg_cfgRxLaneMode_1_cfgRxSelFcFec_f - McPcsX16LanesRxALaneModeCfg_cfgRxLaneMode_0_cfgRxSelFcFec_f                    , /*12 McPcs_cfgRxSelFcFec     */
    McPcsX16LanesRxAChanDskCfg_cfgRxDskChan_1_cfgRxFecMode_f - McPcsX16LanesRxAChanDskCfg_cfgRxDskChan_0_cfgRxFecMode_f                          , /*13 McPcs_cfgRxFecMode      */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxChanId_f - McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f                      , /*14 McPcs_cfgTxChanId       */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxLaneId_f - McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxLaneId_f                      , /*15 McPcs_cfgTxLaneId       */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxPcsMode_f - McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxPcsMode_f                    , /*16 McPcs_cfgTxPcsMode      */
    0                                                                                                                                            , /*17 McPcs_cfgTxChanIsPam4   */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxGearboxMode_f - McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxGearboxMode_f    , /*18 McPcs_cfgTxGearboxMode  */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxBufThrd_f - McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxBufThrd_f            , /*19 McPcs_cfgTxBufThrd      */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxFifoAFullThrd_f - McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxFifoAFullThrd_f, /*20 McPcs_cfgTxFifoAFullThrd*/
    0                                                                                                                                            , /*21 McPcs_cfgTxRsFecModeSel */
    McPcsX16LanesQsgmiiReset_resetQsgmii_1_resetCore_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_resetCore_f                                      , /*22 McPcs_resetQsgmii_resetCore*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_1_unidirectionEn_f - McPcsX16LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f                                        , /*23 McPcs_cfgSgmii_unidirectionEn*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_1_anEnable_f - McPcsX16LanesSgmiiCfg_cfgSgmii_0_anEnable_f                                                    , /*24 McPcs_cfgSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_unidirectionEn_f - McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_unidirectionEn_f                          , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_anEnable_f - McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anEnable_f                                      , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_anegMode_f - McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anegMode_f                                      , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmii_1_cfgTxCreditThrd_f - McPcsX16LanesQsgmiiCfg_cfgQsgmii_0_cfgTxCreditThrd_f                                  , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmii_1_reAlignEachEn_f - McPcsX16LanesQsgmiiCfg_cfgQsgmii_0_reAlignEachEn_f                                      , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxDoneMode_f - McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxDoneMode_f                  , /*30 McPcs_cfgTxDoneMode*/
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxPrimingThrd_f - McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxPrimingThrd_f    , /*31 McPcs_cfgTxPrimingThrd*/
    McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_1_cfgRxSgmiiMode_f - McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_0_cfgRxSgmiiMode_f                      , /*32 McPcs_cfgRxSgmiiMode*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_1_txXmitLoadUseAsyncFifo_f - McPcsX16LanesSgmiiCfg_cfgSgmii_0_txXmitLoadUseAsyncFifo_f                        , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_tbl_id_base_x16b[McPcs_TOTAL_CNT] = {
    0                              , /*0  logic_lane_num          */
    McPcsX16LanesMcFecCfg_t        , /*1  McPcs_SoftRstRxMcFec    */
    McPcsX16LanesMcFecCfg_t        , /*2  McPcs_SoftRstTxMcFec    */
    McPcsX16LanesInit_t            , /*3  McPcs_LaneInit          */
    McPcsX16LanesRxBPhyLaneCfg_t   , /*4  McPcs_cfgRxGearboxMode  */
    McPcsX16LanesRxBPhyLaneCfg_t   , /*5  McPcs_cfgRxChanId       */
    McPcsX16LanesRxBLaneCfg_t      , /*6  McPcs_cfgRxSpeed        */
    McPcsX16LanesRxBLaneCfg_t      , /*7  McPcs_cfgRxDskMaxAddr   */
    McPcsX16LanesRxBLaneSwapCfg_t  , /*8  McPcs_cfgRxLaneswapId   */
    McPcsX16LanesRxBLaneLockCfg_t  , /*9  McPcs_cfgRxAmInterval   */
    McPcsX16LanesRxBPam4EnCfg_t    , /*10 McPcs_cfgRxIsPam4       */
    McPcsX16LanesRxBLaneModeCfg_t  , /*11 McPcs_cfgRxSelRsFec     */
    McPcsX16LanesRxBLaneModeCfg_t  , /*12 McPcs_cfgRxSelFcFec     */
    McPcsX16LanesRxBChanDskCfg_t   , /*13 McPcs_cfgRxFecMode      */
    McPcsX16LanesTxLaneMapCfg_t    , /*14 McPcs_cfgTxChanId       */
    McPcsX16LanesTxLaneMapCfg_t    , /*15 McPcs_cfgTxLaneId       */
    McPcsX16LanesTxLaneMapCfg_t    , /*16 McPcs_cfgTxPcsMode      */
    McPcsX16LanesTxPam4EnCfg_t     , /*17 McPcs_cfgTxChanIsPam4   */
    McPcsX16LanesTxLaneGearboxCfg_t, /*18 McPcs_cfgTxGearboxMode  */
    McPcsX16LanesTxLaneGearboxCfg_t, /*19 McPcs_cfgTxBufThrd      */
    McPcsX16LanesTxLaneGearboxCfg_t, /*20 McPcs_cfgTxFifoAFullThrd*/
    McPcsX16LanesTxMiscCfg_t       , /*21 McPcs_cfgTxRsFecModeSel */
    McPcsX16LanesQsgmiiReset_t     , /*22 McPcs_resetQsgmii_resetCore*/
    McPcsX16LanesSgmiiCfg_t        , /*23 McPcs_cfgSgmii_unidirectionEn*/
    McPcsX16LanesSgmiiCfg_t        , /*24 McPcs_cfgSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_t       , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    McPcsX16LanesQsgmiiCfg_t       , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_t       , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    McPcsX16LanesQsgmiiCfg_t       , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    McPcsX16LanesQsgmiiCfg_t       , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    McPcsX16LanesTxLaneMapCfg_t    , /*30 McPcs_cfgTxDoneMode*/
    McPcsX16LanesTxLaneGearboxCfg_t, /*31 McPcs_cfgTxPrimingThrd*/
    McPcsX16LanesRxBPhyLaneCfg_t   , /*32 McPcs_cfgRxSgmiiMode*/
    McPcsX16LanesSgmiiCfg_t        , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_fld_id_base_x16b[McPcs_TOTAL_CNT] = {
    0                                                                    , /*0  logic_lane_num          */
    McPcsX16LanesMcFecCfg_cfgSoftRstRxMcFec_f                            , /*1  McPcs_SoftRstRxMcFec    */
    McPcsX16LanesMcFecCfg_cfgSoftRstTxMcFec_f                            , /*2  McPcs_SoftRstTxMcFec    */
    McPcsX16LanesInit_init_f                                             , /*3  McPcs_LaneInit          */
    McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_0_cfgRxGearboxMode_f         , /*4  McPcs_cfgRxGearboxMode  */
    McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f              , /*5  McPcs_cfgRxChanId       */
    McPcsX16LanesRxBLaneCfg_cfgRxLane_0_cfgRxSpeed_f                     , /*6  McPcs_cfgRxSpeed        */
    McPcsX16LanesRxBLaneCfg_cfgRxLane_0_cfgRxDskMaxAddr_f                , /*7  McPcs_cfgRxDskMaxAddr   */
    McPcsX16LanesRxBLaneSwapCfg_cfgRxSwapLane_0_cfgRxLaneId_f            , /*8  McPcs_cfgRxLaneswapId   */
    McPcsX16LanesRxBLaneLockCfg_cfgRxLockLane_0_cfgRxAmInterval_f        , /*9  McPcs_cfgRxAmInterval   */
    McPcsX16LanesRxBPam4EnCfg_cfgRxPam4En_0_cfgRxIsPam4_f                , /*10 McPcs_cfgRxIsPam4       */
    McPcsX16LanesRxBLaneModeCfg_cfgRxLaneMode_0_cfgRxSelRsFec_f          , /*11 McPcs_cfgRxSelRsFec     */
    McPcsX16LanesRxBLaneModeCfg_cfgRxLaneMode_0_cfgRxSelFcFec_f          , /*12 McPcs_cfgRxSelFcFec     */
    McPcsX16LanesRxBChanDskCfg_cfgRxDskChan_0_cfgRxFecMode_f             , /*13 McPcs_cfgRxFecMode      */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f           , /*14 McPcs_cfgTxChanId       */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxLaneId_f           , /*15 McPcs_cfgTxLaneId       */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxPcsMode_f          , /*16 McPcs_cfgTxPcsMode      */
    McPcsX16LanesTxPam4EnCfg_cfgTxChanIsPam4Bmp_f                        , /*17 McPcs_cfgTxChanIsPam4   */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxGearboxMode_f  , /*18 McPcs_cfgTxGearboxMode  */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxBufThrd_f      , /*19 McPcs_cfgTxBufThrd      */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxFifoAFullThrd_f, /*20 McPcs_cfgTxFifoAFullThrd*/ 
    McPcsX16LanesTxMiscCfg_cfgTxRsFecModeSel_f                           , /*21 McPcs_cfgTxRsFecModeSel */
    McPcsX16LanesQsgmiiReset_resetQsgmii_0_resetCore_f                   , /*22 McPcs_resetQsgmii_resetCore*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f                    , /*23 McPcs_cfgSgmii_unidirectionEn*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_0_anEnable_f                          , /*24 McPcs_cfgSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_unidirectionEn_f             , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anEnable_f                   , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anegMode_f                   , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmii_0_cfgTxCreditThrd_f                 , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmii_0_reAlignEachEn_f                   , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxDoneMode_f         , /*30 McPcs_cfgTxDoneMode*/
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxPrimingThrd_f  , /*31 McPcs_cfgTxPrimingThrd*/
    McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_0_cfgRxSgmiiMode_f           , /*32 McPcs_cfgRxSgmiiMode*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_0_txXmitLoadUseAsyncFifo_f            , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_field_step_x16b[McPcs_TOTAL_CNT] = {
    0                                                                                                                                            , /*0  logic_lane_num          */
    0                                                                                                                                            , /*1  McPcs_SoftRstRxMcFec    */
    0                                                                                                                                            , /*2  McPcs_SoftRstTxMcFec    */
    0                                                                                                                                            , /*3  McPcs_LaneInit          */
    McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_1_cfgRxGearboxMode_f - McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_0_cfgRxGearboxMode_f                  , /*4  McPcs_cfgRxGearboxMode  */
    McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_1_cfgRxChanId_f - McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f                            , /*5  McPcs_cfgRxChanId       */
    McPcsX16LanesRxBLaneCfg_cfgRxLane_1_cfgRxSpeed_f - McPcsX16LanesRxBLaneCfg_cfgRxLane_0_cfgRxSpeed_f                                          , /*6  McPcs_cfgRxSpeed        */
    McPcsX16LanesRxBLaneCfg_cfgRxLane_1_cfgRxDskMaxAddr_f - McPcsX16LanesRxBLaneCfg_cfgRxLane_0_cfgRxDskMaxAddr_f                                , /*7  McPcs_cfgRxDskMaxAddr   */
    McPcsX16LanesRxBLaneSwapCfg_cfgRxSwapLane_1_cfgRxLaneId_f - McPcsX16LanesRxBLaneSwapCfg_cfgRxSwapLane_0_cfgRxLaneId_f                        , /*8  McPcs_cfgRxLaneswapId   */
    McPcsX16LanesRxBLaneLockCfg_cfgRxLockLane_1_cfgRxAmInterval_f - McPcsX16LanesRxBLaneLockCfg_cfgRxLockLane_0_cfgRxAmInterval_f                , /*9  McPcs_cfgRxAmInterval   */
    McPcsX16LanesRxBPam4EnCfg_cfgRxPam4En_1_cfgRxIsPam4_f - McPcsX16LanesRxBPam4EnCfg_cfgRxPam4En_0_cfgRxIsPam4_f                                , /*10 McPcs_cfgRxIsPam4       */
    McPcsX16LanesRxBLaneModeCfg_cfgRxLaneMode_1_cfgRxSelRsFec_f - McPcsX16LanesRxBLaneModeCfg_cfgRxLaneMode_0_cfgRxSelRsFec_f                    , /*11 McPcs_cfgRxSelRsFec     */
    McPcsX16LanesRxBLaneModeCfg_cfgRxLaneMode_1_cfgRxSelFcFec_f - McPcsX16LanesRxBLaneModeCfg_cfgRxLaneMode_0_cfgRxSelFcFec_f                    , /*12 McPcs_cfgRxSelFcFec     */
    McPcsX16LanesRxBChanDskCfg_cfgRxDskChan_1_cfgRxFecMode_f - McPcsX16LanesRxBChanDskCfg_cfgRxDskChan_0_cfgRxFecMode_f                          , /*13 McPcs_cfgRxFecMode      */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxChanId_f - McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f                      , /*14 McPcs_cfgTxChanId       */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxLaneId_f - McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxLaneId_f                      , /*15 McPcs_cfgTxLaneId       */
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxPcsMode_f - McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxPcsMode_f                    , /*16 McPcs_cfgTxPcsMode      */
    0                                                                                                                                            , /*17 McPcs_cfgTxChanIsPam4   */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxGearboxMode_f - McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxGearboxMode_f    , /*18 McPcs_cfgTxGearboxMode  */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxBufThrd_f - McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxBufThrd_f            , /*19 McPcs_cfgTxBufThrd      */
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxFifoAFullThrd_f - McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxFifoAFullThrd_f, /*20 McPcs_cfgTxFifoAFullThrd*/
    0                                                                                                                                            , /*21 McPcs_cfgTxRsFecModeSel */
    McPcsX16LanesQsgmiiReset_resetQsgmii_1_resetCore_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_resetCore_f                                      , /*22 McPcs_resetQsgmii_resetCore*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_1_unidirectionEn_f - McPcsX16LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f                                        , /*23 McPcs_cfgSgmii_unidirectionEn*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_1_anEnable_f - McPcsX16LanesSgmiiCfg_cfgSgmii_0_anEnable_f                                                    , /*24 McPcs_cfgSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_unidirectionEn_f - McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_unidirectionEn_f                          , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_anEnable_f - McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anEnable_f                                      , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_anegMode_f - McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anegMode_f                                      , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmii_1_cfgTxCreditThrd_f - McPcsX16LanesQsgmiiCfg_cfgQsgmii_0_cfgTxCreditThrd_f                                  , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    McPcsX16LanesQsgmiiCfg_cfgQsgmii_1_reAlignEachEn_f - McPcsX16LanesQsgmiiCfg_cfgQsgmii_0_reAlignEachEn_f                                      , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxDoneMode_f - McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxDoneMode_f                  , /*30 McPcs_cfgTxDoneMode*/
    McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_1_cfgTxPrimingThrd_f - McPcsX16LanesTxLaneGearboxCfg_cfgTxGearboxLane_0_cfgTxPrimingThrd_f    , /*31 McPcs_cfgTxPrimingThrd*/
    McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_1_cfgRxSgmiiMode_f - McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_0_cfgRxSgmiiMode_f                      , /*32 McPcs_cfgRxSgmiiMode*/
    McPcsX16LanesSgmiiCfg_cfgSgmii_1_txXmitLoadUseAsyncFifo_f - McPcsX16LanesSgmiiCfg_cfgSgmii_0_txXmitLoadUseAsyncFifo_f                        , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_offset_type[McPcs_TOTAL_CNT] = {
    OFFSET_TYPE_1                     , /*0  logic_lane_num          */
    OFFSET_TYPE_1                     , /*1  McPcs_SoftRstRxMcFec    */
    OFFSET_TYPE_1                     , /*2  McPcs_SoftRstTxMcFec    */
    OFFSET_TYPE_1                     , /*3  McPcs_LaneInit          */
    OFFSET_TYPE_PHYSIC_LANE_ID_X16AB  , /*4  McPcs_cfgRxGearboxMode  */
    OFFSET_TYPE_PHYSIC_LANE_ID_X16AB  , /*5  McPcs_cfgRxChanId       */
    OFFSET_TYPE_LOGICAL_LANE_ID_X16AB , /*6  McPcs_cfgRxSpeed        */
    OFFSET_TYPE_LOGICAL_LANE_ID_X16AB , /*7  McPcs_cfgRxDskMaxAddr   */
    OFFSET_TYPE_PHYSIC_LANE_ID_X16AB  , /*8  McPcs_cfgRxLaneswapId   */
    OFFSET_TYPE_LOGICAL_LANE_ID_X16AB , /*9  McPcs_cfgRxAmInterval   */
    OFFSET_TYPE_LOGICAL_LANE_ID_X16AB , /*10 McPcs_cfgRxIsPam4       */
    OFFSET_TYPE_LOGICAL_LANE_ID_X16AB , /*11 McPcs_cfgRxSelRsFec     */
    OFFSET_TYPE_LOGICAL_LANE_ID_X16AB , /*12 McPcs_cfgRxSelFcFec     */
    OFFSET_TYPE_LOGICAL_LANE_ID_X16AB , /*13 McPcs_cfgRxFecMode      */
    OFFSET_TYPE_PHYSICAL_LANE_ID      , /*14 McPcs_cfgTxChanId       */
    OFFSET_TYPE_PHYSICAL_LANE_ID      , /*15 McPcs_cfgTxLaneId       */
    OFFSET_TYPE_PHYSICAL_LANE_ID      , /*16 McPcs_cfgTxPcsMode      */
    OFFSET_TYPE_1                     , /*17 McPcs_cfgTxChanIsPam4   */
    OFFSET_TYPE_PHYSICAL_LANE_ID      , /*18 McPcs_cfgTxGearboxMode  */
    OFFSET_TYPE_PHYSICAL_LANE_ID      , /*19 McPcs_cfgTxBufThrd      */
    OFFSET_TYPE_PHYSICAL_LANE_ID      , /*20 McPcs_cfgTxFifoAFullThrd*/
    OFFSET_TYPE_PCS_ID                , /*21 McPcs_cfgTxRsFecModeSel */
    OFFSET_TYPE_PCS_ID                , /*22 McPcs_resetQsgmii_resetCore*/
    OFFSET_TYPE_PCS_ID                , /*23 McPcs_cfgSgmii_unidirectionEn*/
    OFFSET_TYPE_PCS_ID                , /*24 McPcs_cfgSgmii_anEnable*/
    OFFSET_TYPE_TXQM_MAC_ID           , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    OFFSET_TYPE_TXQM_MAC_ID           , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    OFFSET_TYPE_TXQM_MAC_ID           , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    OFFSET_TYPE_PCS_ID                , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    OFFSET_TYPE_PCS_ID                , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    OFFSET_TYPE_PHYSICAL_LANE_ID      , /*30 McPcs_cfgTxDoneMode*/
    OFFSET_TYPE_PCS_ID                , /*31 McPcs_cfgTxPrimingThrd*/
    OFFSET_TYPE_PHYSIC_LANE_ID_X16AB  , /*32 McPcs_cfgRxSgmiiMode*/
    OFFSET_TYPE_PCS_ID                , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_tbl_idx_type[McPcs_TOTAL_CNT] = {
    INDEX_TYPE_0_0          , /*0  logic_lane_num          */
    INDEX_TYPE_0_0          , /*1  McPcs_SoftRstRxMcFec    */
    INDEX_TYPE_0_0          , /*2  McPcs_SoftRstTxMcFec    */
    INDEX_TYPE_PCSXIDX_0    , /*3  McPcs_LaneInit          */
    INDEX_TYPE_PCSXIDX_0    , /*4  McPcs_cfgRxGearboxMode  */
    INDEX_TYPE_PCSXIDX_0    , /*5  McPcs_cfgRxChanId       */
    INDEX_TYPE_PCSXIDX_0    , /*6  McPcs_cfgRxSpeed        */
    INDEX_TYPE_PCSXIDX_0    , /*7  McPcs_cfgRxDskMaxAddr   */
    INDEX_TYPE_PCSXIDX_0    , /*8  McPcs_cfgRxLaneswapId   */
    INDEX_TYPE_PCSXIDX_0    , /*9  McPcs_cfgRxAmInterval   */
    INDEX_TYPE_PCSXIDX_0    , /*10 McPcs_cfgRxIsPam4       */
    INDEX_TYPE_PCSXIDX_0    , /*11 McPcs_cfgRxSelRsFec     */
    INDEX_TYPE_PCSXIDX_0    , /*12 McPcs_cfgRxSelFcFec     */
    INDEX_TYPE_PCSXIDX_0    , /*13 McPcs_cfgRxFecMode      */
    INDEX_TYPE_PCSXIDX_0    , /*14 McPcs_cfgTxChanId       */
    INDEX_TYPE_PCSXIDX_0    , /*15 McPcs_cfgTxLaneId       */
    INDEX_TYPE_PCSXIDX_0    , /*16 McPcs_cfgTxPcsMode      */
    INDEX_TYPE_PCSXIDX_0    , /*17 McPcs_cfgTxChanIsPam4   */
    INDEX_TYPE_PCSXIDX_0    , /*18 McPcs_cfgTxGearboxMode  */
    INDEX_TYPE_PCSXIDX_0    , /*19 McPcs_cfgTxBufThrd      */
    INDEX_TYPE_PCSXIDX_0    , /*20 McPcs_cfgTxFifoAFullThrd*/
    INDEX_TYPE_PCSXIDX_PCSID, /*21 McPcs_cfgTxRsFecModeSel */
    INDEX_TYPE_PCSXIDX_0    , /*22 McPcs_resetQsgmii_resetCore*/
    INDEX_TYPE_PCSXIDX_0    , /*23 McPcs_cfgSgmii_unidirectionEn*/
    INDEX_TYPE_PCSXIDX_0    , /*24 McPcs_cfgSgmii_anEnable*/
    INDEX_TYPE_PCSXIDX_0    , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    INDEX_TYPE_PCSXIDX_0    , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    INDEX_TYPE_PCSXIDX_0    , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    INDEX_TYPE_PCSXIDX_0    , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    INDEX_TYPE_PCSXIDX_0    , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    INDEX_TYPE_PCSXIDX_0    , /*30 McPcs_cfgTxDoneMode*/
    INDEX_TYPE_PCSXIDX_0    , /*31 McPcs_cfgTxPrimingThrd*/
    INDEX_TYPE_PCSXIDX_0    , /*32 McPcs_cfgRxSgmiiMode*/
    INDEX_TYPE_PCSXIDX_0    , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_value_type[McPcs_TOTAL_CNT] = {
    VALUE_TYPE_NORMAL         , /*0  logic_lane_num          */
    VALUE_TYPE_NORMAL         , /*1  McPcs_SoftRstRxMcFec    */
    VALUE_TYPE_NORMAL         , /*2  McPcs_SoftRstTxMcFec    */
    VALUE_TYPE_NORMAL         , /*3  McPcs_LaneInit          */
    VALUE_TYPE_NORMAL         , /*4  McPcs_cfgRxGearboxMode  */
    VALUE_TYPE_PCS_ID         , /*5  McPcs_cfgRxChanId       */
    VALUE_TYPE_NORMAL         , /*6  McPcs_cfgRxSpeed        */
    VALUE_TYPE_NORMAL         , /*7  McPcs_cfgRxDskMaxAddr   */
    VALUE_TYPE_LOGICAL_LANE_ID, /*8  McPcs_cfgRxLaneswapId   */
    VALUE_TYPE_NORMAL         , /*9  McPcs_cfgRxAmInterval   */
    VALUE_TYPE_NORMAL         , /*10 McPcs_cfgRxIsPam4       */
    VALUE_TYPE_NORMAL         , /*11 McPcs_cfgRxSelRsFec     */
    VALUE_TYPE_NORMAL         , /*12 McPcs_cfgRxSelFcFec     */
    VALUE_TYPE_NORMAL         , /*13 McPcs_cfgRxFecMode      */
    VALUE_TYPE_PCS_ID         , /*14 McPcs_cfgTxChanId       */
    VALUE_TYPE_PCS_L_ID       , /*15 McPcs_cfgTxLaneId       */
    VALUE_TYPE_NORMAL         , /*16 McPcs_cfgTxPcsMode      */
    VALUE_TYPE_PCS_ID_BMP     , /*17 McPcs_cfgTxChanIsPam4   */
    VALUE_TYPE_NORMAL         , /*18 McPcs_cfgTxGearboxMode  */
    VALUE_TYPE_NORMAL         , /*19 McPcs_cfgTxBufThrd      */
    VALUE_TYPE_NORMAL         , /*20 McPcs_cfgTxFifoAFullThrd*/
    VALUE_TYPE_NORMAL         , /*21 McPcs_cfgTxRsFecModeSel */
    VALUE_TYPE_NORMAL         , /*22 McPcs_resetQsgmii_resetCore*/
    VALUE_TYPE_NORMAL         , /*23 McPcs_cfgSgmii_unidirectionEn*/
    VALUE_TYPE_NORMAL         , /*24 McPcs_cfgSgmii_anEnable*/
    VALUE_TYPE_NORMAL         , /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    VALUE_TYPE_NORMAL         , /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    VALUE_TYPE_NORMAL         , /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    VALUE_TYPE_NORMAL         , /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    VALUE_TYPE_NORMAL         , /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    VALUE_TYPE_NORMAL         , /*30 McPcs_cfgTxDoneMode*/
    VALUE_TYPE_NORMAL         , /*31 McPcs_cfgTxPrimingThrd*/
    VALUE_TYPE_NORMAL         , /*32 McPcs_cfgRxSgmiiMode*/
    VALUE_TYPE_NORMAL         , /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_mode_value_map[McPcs_TOTAL_CNT][CTC_CHIP_MAX_SERDES_MODE] = 
{
  /*NONE XFI SGMII NONE QSGMII NONE NONE XLG   CG    2.5G NONE NONE NONE XXVG LG    NONE LG_R1 CG_R2 CCG_R4CDG_R8*/
    {0,  1,  1,    0,   1,     0,   0,   4,    4,    1,   0,   0,   0,   1,   2,    0,   1,    2,    4,    8    }, /*0  logic_lane_num          */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*1  McPcs_SoftRstRxMcFec    */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*2  McPcs_SoftRstTxMcFec    */
    {0,  1,  1,    1,   1,     1,   1,   1,    1,    1,   1,   1,   1,   1,   1,    1,   1,    1,    1,    1    }, /*3  McPcs_LaneInit          */
    {0,  0,  2,    0,   2,     0,   0,   0,    0,    2,   0,   0,   0,   0,   0,    0,   1,    1,    3,    3    }, /*4  McPcs_cfgRxGearboxMode  */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*5  McPcs_cfgRxChanId       */
    {0,  5,  0,    0,   0,     0,   0,   7,    9,    0,   0,   0,   0,   6,   8,    0,   8,    9,    10,   11   }, /*6  McPcs_cfgRxSpeed        */
    {0,  159,50,   0,   50,    0,   0,   159,  31,   50,  0,   0,   0,   159, 79,   0,   39,   15,   79,   79   }, /*7  McPcs_cfgRxDskMaxAddr   */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*8  McPcs_cfgRxLaneswapId   */
    {0,16383,0,    0,   0,     0,   0,   16382,16382,0,   0,   0,   0,  16383,16382,0,   20478,16382,34815,34815}, /*9  McPcs_cfgRxAmInterval   */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   1,    1,    1,    1    }, /*10 McPcs_cfgRxIsPam4       */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    1,    1    }, /*11 McPcs_cfgRxSelRsFec     */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*12 McPcs_cfgRxSelFcFec     */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    1,    1    }, /*13 McPcs_cfgRxFecMode      */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*14 McPcs_cfgTxChanId       */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*15 McPcs_cfgTxLaneId       */
    {0,  0,  3,    0,   4,     0,   0,   0,    0,    3,   0,   0,   0,   0,   0,    0,   0,    0,    1,    1    }, /*16 McPcs_cfgTxPcsMode      */
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   1,    1,    1,    1    }, /*17 McPcs_cfgTxChanIsPam4   */
    {0,  0,  2,    0,   2,     0,   0,   0,    0,    2,   0,   0,   0,   0,   0,    0,   1,    1,    3,    3    }, /*18 McPcs_cfgTxGearboxMode  */
    {0,  1,  1,    0,   1,     0,   0,   1,    1,    1,   0,   0,   0,   1,   1,    0,   1,    1,    1,    1    }, /*19 McPcs_cfgTxBufThrd      */
    {0,  4,  4,    0,   4,     0,   0,   4,    4,    4,   0,   0,   0,   4,   4,    0,   6,    6,    6,    6    }, /*20 McPcs_cfgTxFifoAFullThrd*/
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    1,    1    }, /*21 McPcs_cfgTxRsFecModeSel */
    {0,  1,  1,    0,   0,     0,   0,   1,    1,    1,   0,   0,   0,   1,   1,    0,   1,    1,    1,    1    }, /*22 McPcs_resetQsgmii_resetCore*/
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*23 McPcs_cfgSgmii_unidirectionEn*/
    {0,  1,  1,    0,   1,     0,   0,   1,    1,    1,   0,   0,   0,   1,   1,    0,   1,    1,    1,    1    }, /*24 McPcs_cfgSgmii_anEnable*/
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    {0,  1,  1,    0,   1,     0,   0,   1,    1,    1,   0,   0,   0,   1,   1,    0,   1,    1,    1,    1    }, /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    {0,  2,  2,    0,   2,     0,   0,   2,    2,    2,   0,   0,   0,   2,   2,    0,   2,    2,    2,    2    }, /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    {0,  4,  4,    0,   8,     0,   0,   4,    4,    4,   0,   0,   0,   4,   4,    0,   4,    4,    4,    4    }, /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    {0,  0,  0,    0,   1,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    {0,  0,  1,    0,   1,     0,   0,   0,    0,    1,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*30 McPcs_cfgTxDoneMode*/
    {0,  1,  1,    0,   2,     0,   0,   1,    1,    1,   0,   0,   0,   1,   1,    0,   1,    1,    1,    1    }, /*31 McPcs_cfgTxPrimingThrd*/
    {0,  0,  1,    0,   1,     0,   0,   0,    0,    1,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*32 McPcs_cfgRxSgmiiMode*/
    {0,  0,  0,    0,   0,     0,   0,   0,    0,    0,   0,   0,   0,   0,   0,    0,   0,    0,    0,    0    }, /*33 McPcs_SgmiiAsyncFifo*/
};

const uint32 g_mcpcs_fec_value_map[McPcs_TOTAL_CNT][MAX_MODE_FEC] = 
{
   /*XFI_FC2112,  XXVG_FC2112, XXVG_RS528,  XLG_FC2112,  LG_R2_RS528, LG_R2_RS544,  LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272, 
   CG_R4_RS528, CG_R4_RS544, CG_R2_RS528, CG_R2_RS544, CG_R2_RS272, CCG_R4_RS544, CCG_R4_RS272, CDG_R8_RS544, CDG_R8_RS272*/
    {1,           1,           1,           4,           2,           2,            1,            1,            1,           
    4,           4,           2,           2,           2,           4,            4,            8,            8    }, /*0  logic_lane_num          */
    {0,           0,           0,           0,           0,           0,            0,            0,            0,           
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*1  McPcs_SoftRstRxMcFec    */
    {0,           0,           0,           0,           0,           0,            0,            0,            0,           
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*2  McPcs_SoftRstTxMcFec    */
    {1,           1,           1,           1,           1,           1,            1,            1,            1,           
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*3  McPcs_LaneInit          */
    {0,           0,           2,           0,           2,           2,            3,            3,            3,           
    2,           2,           3,           3,           3,           3,            3,            3,            3    }, /*4  McPcs_cfgRxGearboxMode  */
    {0,           0,           0,           0,           0,           0,            0,            0,            0,           
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*5  McPcs_cfgRxChanId       */
    {5,           6,           6,           7,           8,           8,            8,            8,            8,           
    9,           9,           9,           9,           9,           10,           10,           11,           11   }, /*6  McPcs_cfgRxSpeed        */
    {159,         159,         159,         159,         79,          79,           39,           39,           39,          
    31,          31,          15,          15,          15,          79,           79,           79,           79   }, /*7  McPcs_cfgRxDskMaxAddr   */
    {0,           0,           0,           0,           0,           0,            0,            0,            0,           
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*8  McPcs_cfgRxLaneswapId   */
    {16383,       16383,       67583,       16382,       33791,       34815,        33791,        34815,        34815,       
    67583,       69631,       67583,       69631,       69631,       34815,        34815,        34815,        34815}, /*9  McPcs_cfgRxAmInterval   */
    {0,           0,           0,           0,           0,           0,            1,            1,            1,           
    0,           0,           1,           1,           1,           1,            1,            1,            1    }, /*10 McPcs_cfgRxIsPam4       */
    {0,           0,           1,           0,           1,           1,            1,            1,            1,           
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*11 McPcs_cfgRxSelRsFec     */
    {1,           1,           0,           1,           0,           0,            0,            0,            0,           
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*12 McPcs_cfgRxSelFcFec     */
    {0,           0,           2,           0,           2,           1,            2,            1,            3,           
    2,           1,           2,           1,           3,           1,            3,            1,            3    }, /*13 McPcs_cfgRxFecMode      */
    {0,           0,           0,           0,           0,           0,            0,            0,            0,           
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*14 McPcs_cfgTxChanId       */
    {0,           0,           0,           0,           0,           0,            0,            0,            0,           
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*15 McPcs_cfgTxLaneId       */
    {2,           2,           1,           2,           1,           1,            1,            1,            1,           
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*16 McPcs_cfgTxPcsMode      */
    {0,           0,           0,           0,           0,           0,            1,            1,            1,           
    0,           0,           1,           1,           1,           1,            1,            1,            1    }, /*17 McPcs_cfgTxChanIsPam4   */
    {0,           0,           2,           0,           2,           2,            3,            3,            3,           
    2,           2,           3,           3,           3,           3,            3,            3,            3    }, /*18 McPcs_cfgTxGearboxMode  */
    {1,           1,           5,           1,           5,           5,            5,            5,            5,           
    5,           5,           5,           5,           5,           1,            5,            1,            1    }, /*19 McPcs_cfgTxBufThrd      */
    {4,           4,           4,           4,           4,           4,            6,            6,            6,           
    4,           4,           6,           6,           6,           6,            6,            6,            6    }, /*20 McPcs_cfgTxFifoAFullThrd*/
    {0,           0,           2,           0,           2,           1,            2,            1,            3,           
    2,           1,           2,           1,           3,           1,            3,            1,            3    }, /*21 McPcs_cfgTxRsFecModeSel */
    {1,           1,           1,           1,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*22 McPcs_resetQsgmii_resetCore*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,              
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*23 McPcs_cfgSgmii_unidirectionEn*/
    {1,           1,           1,           1,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*24 McPcs_cfgSgmii_anEnable*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*25 McPcs_cfgQsgmiiSgmii_unidirectionEn*/
    {1,           1,           1,           1,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*26 McPcs_cfgQsgmiiSgmii_anEnable*/
    {2,           2,           2,           2,           2,           2,            2,            2,            2,          
    2,           2,           2,           2,           2,           2,            2,            2,            2    }, /*27 McPcs_cfgQsgmiiSgmii_anegMode*/
    {4,           4,           4,           4,           4,           4,            4,            4,            4,          
    4,           4,           4,           4,           4,           4,            4,            4,            4    }, /*28 McPcs_cfgQsgmii_cfgTxCreditThrd*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,           
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*29 McPcs_cfgQsgmii_reAlignEachEn*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,           
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*30 McPcs_cfgTxDoneMode*/
    {1,           1,           1,           1,           1,           1,            1,            1,            1,          
    1,           1,           1,           1,           1,           1,            1,            1,            1    }, /*31 McPcs_cfgTxPrimingThrd*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*32 McPcs_cfgRxSgmiiMode*/
    {0,           0,           0,           0,           0,           0,            0,            0,            0,          
    0,           0,           0,           0,           0,           0,            0,            0,            0    }, /*33 McPcs_SgmiiAsyncFifo*/
};

/************************* Mac&Pcs public info *************************/
const uint32 g_mode_with_fec_map[CTC_CHIP_MAX_SERDES_MODE][MAX_MODE_FEC] = 
{
   /*RS528         RS544         RS272         FC2112(BASER)*/
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_NONE_MODE*/     
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, XFI_FC2112  }, /*CTC_CHIP_SERDES_XFI_MODE*/      
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_SGMII_MODE*/    
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_XSGMII_MODE*/   
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_QSGMII_MODE*/   
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_XAUI_MODE*/     
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_DXAUI_MODE*/    
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, XLG_FC2112  }, /*CTC_CHIP_SERDES_XLG_MODE*/      
    {CG_R4_RS528 , CG_R4_RS544 , MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_CG_MODE*/       
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_2DOT5G_MODE*/   
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_USXGMII0_MODE*/ 
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_USXGMII1_MODE*/ 
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_USXGMII2_MODE*/ 
    {XXVG_RS528  , MAX_MODE_FEC, MAX_MODE_FEC, XXVG_FC2112 }, /*CTC_CHIP_SERDES_XXVG_MODE*/     
    {LG_R2_RS528 , LG_R2_RS544 , MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_LG_MODE*/       
    {MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_100BASEFX_MODE*/
    {LG_R1_RS528 , LG_R1_RS544 , LG_R1_RS272 , MAX_MODE_FEC}, /*CTC_CHIP_SERDES_LG_R1_MODE*/    
    {CG_R2_RS528 , CG_R2_RS544 , CG_R2_RS272 , MAX_MODE_FEC}, /*CTC_CHIP_SERDES_CG_R2_MODE*/    
    {MAX_MODE_FEC, CCG_R4_RS544, CCG_R4_RS272, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_CCG_R4_MODE*/   
    {MAX_MODE_FEC, CDG_R8_RS544, CDG_R8_RS272, MAX_MODE_FEC}, /*CTC_CHIP_SERDES_CDG_R8_MODE*/   
};

extern int32
_sys_tmm_dynamic_switch_datapath(uint8 lchip, sys_tmm_ds_target_attr_t *p_ds_attr);

extern int32
_sys_tmm_datapath_set_qmgr_credit(uint8 lchip, sys_datapath_lport_attr_t* port_attr, uint8 alloc_type, uint8 enable);

extern int32
_sys_tmm_mac_set_ipg(uint8 lchip, uint16 lport, uint32 value_raw);

extern int32
_sys_tmm_mac_set_internal_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 value);

extern int32
_sys_tmm_cpumac_lane3_pcs_rx_reset(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr);

extern uint8 
_sys_tmm_serdes_is_fw_running(uint8 lchip, uint8 serdes_id);
extern int32
sys_tmm_serdes_get_real_data_rate(uint8 datarate_mode, uint8 overclock_flag, uint32 *real_data_rate);
extern int32
sys_tmm_serdes_get_tx_prbs(uint8 lchip, ctc_chip_serdes_prbs_t *p_prbs);
extern int32
sys_tmm_serdes_get_tx_taps(uint8 lchip, uint8 serdes_id, int8 *taps_param);
extern int32
sys_tmm_datapath_get_pll_lock(uint8 lchip, void* p_value);
extern int32
sys_tmm_serdes_get_eye(uint8 lchip, uint8 serdes_id, uint32 *eye_margin);
extern int32
sys_tmm_serdes_get_polarity(uint8 lchip, uint8 serdes_id, uint8 dir, uint8 *val);
extern int32
sys_tmm_datapath_get_serdes_optical_mode(uint8 lchip, void* p_data);
extern int32
sys_tmm_serdes_get_fw_reg(uint8 lchip, uint8 serdes_id, uint16 fw_addr, uint16 section, uint16 *data);
extern int32
sys_tmm_serdes_get_ctle(uint8 lchip, uint8 serdes_id, uint16 *index, uint16 *c1, uint16 *c2);
extern int32
_sys_tmm_mac_nw_sgmii_set_parallel_detect_en(uint8 lchip, sys_datapath_lport_attr_t* port_attr, uint32 enable);
extern int32
_sys_tmm_datapath_check_subtype_pcsmode(uint8 lchip, uint8 pcs_mode, uint8 logic_serdes);
extern int32
_sys_tmm_mac_get_cl37_en(uint8 lchip, uint16 lport, uint32* p_en);
extern int32
_sys_tmm_mac_get_cl37_mode(uint8 lchip, uint16 lport, uint32* p_mode);
/****************************************************************************
 *
* Function
*
*****************************************************************************/

/*find lport/chan mapping in chan_2_logic_serdes*/
int32
sys_tmm_get_lport_chan_map(uint8 lchip, uint8 logic_serdes_id, uint8* p_chan, uint16* p_lport)
{
    uint8 find_flag = FALSE;
    uint8 dp_chan_id;
    uint8 dp_id = SYS_TMM_GET_DP_ID_FROM_SERDES(logic_serdes_id);

    for(dp_chan_id = 0; dp_chan_id < SYS_TMM_CHANNEL_NUM_PER_DP; dp_chan_id++)
    {
        if(p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan_id].logic_serdes_id == logic_serdes_id)
        {
            find_flag = TRUE;
            break;
        }
    }

    SYS_CONDITION_RETURN((!find_flag), CTC_E_INVALID_PARAM);

    SYS_USW_VALID_PTR_WRITE(p_lport, p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan_id].lport);
    SYS_USW_VALID_PTR_WRITE(p_chan, SYS_GET_CHANNEL_BY_DP_CHANID(dp_chan_id, dp_id));

    return CTC_E_NONE;
}

/*for valid mode serdes, using serdes info lport id; for none mode serdes, using mapping lport*/
int32
sys_tmm_get_lport_chan_map_by_logic_serdes(uint8 lchip, uint8 logic_serdes_id, 
                                                         uint8* p_chan, uint16* p_lport)
{
    sys_datapath_serdes_info_t* p_serdes  = NULL;

    CTC_ERROR_RETURN(sys_usw_datapath_get_serdes_info(lchip, logic_serdes_id, &p_serdes));
    if(!SYS_TMM_IS_MODE_NONE(p_serdes->mode))
    {
        SYS_USW_VALID_PTR_WRITE(p_lport, p_serdes->lport);
        SYS_USW_VALID_PTR_WRITE(p_chan, p_serdes->chan_id);
    }
    else
    {
        CTC_ERROR_RETURN(sys_tmm_get_lport_chan_map(lchip, logic_serdes_id, p_chan, p_lport));
    }

    return CTC_E_NONE;
}

int32
sys_tmm_get_logic_serdes_chan_map_by_lport(uint8 lchip, uint16 lport, 
                                                         uint8* p_chan, uint8* p_logic_serdes)
{
    uint8 dp_chan_id;
    uint8 dp_id = 0;
 
    for(dp_id = 0; dp_id < SYS_TMM_DP_NUM; dp_id++)
    {
        for(dp_chan_id = 0; dp_chan_id < SYS_TMM_CHANNEL_NUM_PER_DP; dp_chan_id++)
        {
            if(p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan_id].lport == lport)
            {
                SYS_USW_VALID_PTR_WRITE(p_logic_serdes, 
                    p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan_id].logic_serdes_id);
                SYS_USW_VALID_PTR_WRITE(p_chan, SYS_GET_CHANNEL_BY_DP_CHANID(dp_chan_id, dp_id));
                return CTC_E_NONE;
            }
        }
    }

    return CTC_E_INVALID_PARAM;
}

int32
_sys_tmm_mac_port_set_cl73_ability(uint8 lchip, uint16 lport, void* p_ability)
{
    uint8  cnt = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num)
    {
        return CTC_E_INVALID_PARAM;
    }

    for(cnt = 0; cnt < port_attr->serdes_num; cnt++)
    {
        CTC_ERROR_RETURN(sys_tmm_serdes_set_serdes_auto_neg_ability(lchip, port_attr->multi_serdes_id[cnt], 
            (sys_datapath_an_ability_t*)p_ability));
    }

    return CTC_E_NONE;
}

/* support 802.3ap, Auto-Negotiation for Backplane Ethernet */
int32
sys_tmm_mac_set_cl73_ability(uint8 lchip, uint16 lport, uint32 ability)
{
    sys_datapath_lport_attr_t* port_attr = NULL;
    sys_datapath_an_ability_t cl73_ability;
    uint8  logic_serdes_id = 0;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%u, ability:0x%X\n", lport, ability);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    MAC_LOCK;

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if (!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC %d is not used \n", port_attr->mac_id);
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }
    if(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num)
    {
        MAC_UNLOCK;
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, port_attr->multi_serdes_id[0], 
        &logic_serdes_id));
    if(SYS_BMP_IS_SET(ability, CTC_PORT_CL73_50GBASE_KR) || SYS_BMP_IS_SET(ability, CTC_PORT_CL73_50GBASE_CR) || 
       SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_LF1_50GR1))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_datapath_check_subtype_pcsmode(lchip, CTC_CHIP_SERDES_LG_R1_MODE, 
            logic_serdes_id));
    }
    if(SYS_BMP_IS_SET(ability, CTC_PORT_CL73_100GBASE_KR2) || SYS_BMP_IS_SET(ability, CTC_PORT_CL73_100GBASE_CR2) || 
       SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_LF2_100GR2))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_datapath_check_subtype_pcsmode(lchip, CTC_CHIP_SERDES_CG_R2_MODE, 
            logic_serdes_id));
    }
    if(SYS_BMP_IS_SET(ability, CTC_PORT_CL73_200GBASE_KR4) || SYS_BMP_IS_SET(ability, CTC_PORT_CL73_200GBASE_CR4) || 
       SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_LF3_200GR4))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_datapath_check_subtype_pcsmode(lchip, CTC_CHIP_SERDES_CCG_R4_MODE, 
            logic_serdes_id));
    }
    if(SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_400GBASE_CR8))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_datapath_check_subtype_pcsmode(lchip, CTC_CHIP_SERDES_CDG_R8_MODE, 
            logic_serdes_id));
    }
    if(SYS_BMP_IS_SET(ability, CTC_PORT_CL73_25GBASE_KRS) || SYS_BMP_IS_SET(ability, CTC_PORT_CL73_25GBASE_CRS) || 
       SYS_BMP_IS_SET(ability, CTC_PORT_CL73_25GBASE_KR) || SYS_BMP_IS_SET(ability, CTC_PORT_CL73_25GBASE_CR) || 
       SYS_BMP_IS_SET(ability, CTC_PORT_CL73_25G_RS_FEC_REQUESTED) || SYS_BMP_IS_SET(ability, CTC_PORT_CL73_25G_BASER_FEC_REQUESTED) || 
       SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_25GBASE_KR1) || SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_25GBASE_CR1) || 
       SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_RS_FEC_ABILITY) || SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_RS_FEC_REQUESTED) || 
       SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_BASER_FEC_ABILITY) || SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_BASER_FEC_REQUESTED))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_datapath_check_subtype_pcsmode(lchip, CTC_CHIP_SERDES_XXVG_MODE, 
            logic_serdes_id));
    }
    if(SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_50GBASE_KR2) || SYS_BMP_IS_SET(ability, CTC_PORT_CSTM_50GBASE_CR2))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_datapath_check_subtype_pcsmode(lchip, CTC_CHIP_SERDES_LG_MODE, 
            logic_serdes_id));
    }
    if(SYS_BMP_IS_SET(ability, CTC_PORT_CL73_10GBASE_KR))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_datapath_check_subtype_pcsmode(lchip, CTC_CHIP_SERDES_XFI_MODE, 
            logic_serdes_id));
    }
    if(SYS_BMP_IS_SET(ability, CTC_PORT_CL73_40GBASE_KR4) || SYS_BMP_IS_SET(ability, CTC_PORT_CL73_40GBASE_CR4))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_datapath_check_subtype_pcsmode(lchip, CTC_CHIP_SERDES_XLG_MODE, 
            logic_serdes_id));
    }
    if(SYS_BMP_IS_SET(ability, CTC_PORT_CL73_100GBASE_KR4) || SYS_BMP_IS_SET(ability, CTC_PORT_CL73_100GBASE_CR4))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_datapath_check_subtype_pcsmode(lchip, CTC_CHIP_SERDES_CG_MODE, 
            logic_serdes_id));
    }

    if (SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type) &&
        ((ability & CTC_PORT_CL73_50GBASE_KR)
        || (ability & CTC_PORT_CL73_50GBASE_CR)
        || (ability & CTC_PORT_CL73_100GBASE_KR2)
        || (ability & CTC_PORT_CL73_100GBASE_CR2)
        || (ability & CTC_PORT_CL73_200GBASE_KR4)
        || (ability & CTC_PORT_CL73_200GBASE_CR4)
        || (ability & CTC_PORT_CSTM_400GBASE_CR8)))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% CPUMAC cannot support PAM4! \n");
        MAC_UNLOCK;
        return CTC_E_INVALID_CONFIG;
    }

    if ((SYS_TMM_IS_PCS_X16(port_attr->txqm_id)) &&
        ((ability & CTC_PORT_CL73_200GBASE_KR4)
        || (ability & CTC_PORT_CL73_200GBASE_CR4)
        || (ability & CTC_PORT_CSTM_400GBASE_CR8)))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% HS cannot support 200G/400G! \n");
        MAC_UNLOCK;
        return CTC_E_INVALID_CONFIG;
    }

    sal_memset(&cl73_ability, 0, sizeof(sys_datapath_an_ability_t));
    cl73_ability.base_ability0 |= (1<<0);
    /* 1. get ability */
    if(ability & CTC_PORT_CL73_10GBASE_KR)
    {
        cl73_ability.base_ability0 |= (SYS_PORT_CL73_10GBASE_KR);
    }
    if(ability & CTC_PORT_CL73_40GBASE_KR4)
    {
        cl73_ability.base_ability0 |= (SYS_PORT_CL73_40GBASE_KR4);
    }
    if(ability & CTC_PORT_CL73_40GBASE_CR4)
    {
        cl73_ability.base_ability0 |= (SYS_PORT_CL73_40GBASE_CR4);
    }
    if(ability & CTC_PORT_CL73_100GBASE_KR4)
    {
        cl73_ability.base_ability0 |= (SYS_PORT_CL73_100GBASE_KR4);
    }
    if(ability & CTC_PORT_CL73_100GBASE_CR4)
    {
        cl73_ability.base_ability0 |= (SYS_PORT_CL73_100GBASE_CR4);
    }
    if(ability & CTC_PORT_CL73_25GBASE_KRS)
    {
        cl73_ability.base_ability0 |= (SYS_PORT_CL73_25GBASE_KR_S);
    }
    if(ability & CTC_PORT_CL73_25GBASE_KR)
    {
        cl73_ability.base_ability0 |= (SYS_PORT_CL73_25GBASE_KR|SYS_PORT_CL73_25GBASE_KR_S);
    }
    if(ability & CTC_PORT_CL73_50GBASE_KR)
    {
        cl73_ability.base_ability1 |= (SYS_PORT_CL73_50GBASE_KR);
    }
    if(ability & CTC_PORT_CL73_50GBASE_CR)
    {
        cl73_ability.base_ability1 |= (SYS_PORT_CL73_50GBASE_CR);
    }
    if(ability & CTC_PORT_CL73_100GBASE_KR2)
    {
        cl73_ability.base_ability1 |= (SYS_PORT_CL73_100GBASE_KR2);
    }
    if(ability & CTC_PORT_CL73_100GBASE_CR2)
    {
        cl73_ability.base_ability1 |= (SYS_PORT_CL73_100GBASE_CR2);
    }
    if(ability & CTC_PORT_CL73_200GBASE_KR4)
    {
        cl73_ability.base_ability1 |= (SYS_PORT_CL73_200GBASE_KR4);
    }
    if(ability & CTC_PORT_CL73_200GBASE_CR4)
    {
        cl73_ability.base_ability1 |= (SYS_PORT_CL73_200GBASE_CR4);
    }
    if(ability & CTC_PORT_CL73_25G_RS_FEC_REQUESTED)
    {
        cl73_ability.base_ability1 |= (SYS_PORT_CL73_25G_RS_FEC_REQ);
    }
    if(ability & CTC_PORT_CL73_25G_BASER_FEC_REQUESTED)
    {
        cl73_ability.base_ability1 |= (SYS_PORT_CL73_25G_BASER_FEC_REQ);
    }
    if(ability & CTC_PORT_CL73_FEC_ABILITY)
    {
        cl73_ability.base_ability1 |= (SYS_PORT_CL73_FEC_SUP);
    }
    if(ability & CTC_PORT_CL73_FEC_REQUESTED)
    {
        cl73_ability.base_ability1 |= (SYS_PORT_CL73_FEC_REQ);
    }
    if(ability & CTC_PORT_CSTM_25GBASE_KR1)
    {
        cl73_ability.np1_ability0 |= (SYS_PORT_CSTM_25GBASE_KR1);
    }
    if(ability & CTC_PORT_CSTM_25GBASE_CR1)
    {
        cl73_ability.np1_ability0 |= (SYS_PORT_CSTM_25GBASE_CR1);
    }
    if(ability & CTC_PORT_CSTM_50GBASE_KR2)
    {
        cl73_ability.np1_ability0 |= (SYS_PORT_CSTM_50GBASE_KR2);
    }
    if(ability & CTC_PORT_CSTM_50GBASE_CR2)
    {
        cl73_ability.np1_ability0 |= (SYS_PORT_CSTM_50GBASE_CR2);
    }
    if(ability & CTC_PORT_CSTM_400GBASE_CR8)
    {
        cl73_ability.np1_ability1 |= (SYS_PORT_CSTM_400GBASE_CR8);
    }
    if(ability & CTC_PORT_CSTM_RS_FEC_ABILITY)
    {
        cl73_ability.np1_ability1 |= (SYS_PORT_CSTM_CL91_FEC_SUP);
    }
    if(ability & CTC_PORT_CSTM_BASER_FEC_ABILITY)
    {
        cl73_ability.np1_ability1 |= (SYS_PORT_CSTM_CL74_FEC_SUP);
    }
    if(ability & CTC_PORT_CSTM_RS_FEC_REQUESTED)
    {
        cl73_ability.np1_ability1 |= (SYS_PORT_CSTM_CL91_FEC_REQ);
    }
    if(ability & CTC_PORT_CSTM_BASER_FEC_REQUESTED)
    {
        cl73_ability.np1_ability1 |= (SYS_PORT_CSTM_CL74_FEC_REQ);
    }
    if(ability & CTC_PORT_CSTM_LF1_50GR1)
    {
        cl73_ability.np1_ability1 |= (SYS_PORT_CSTM_LF1_50GR1);
    }
    if(ability & CTC_PORT_CSTM_LF2_100GR2)
    {
        cl73_ability.np1_ability1 |= (SYS_PORT_CSTM_LF2_100GR2);
    }
    if(ability & CTC_PORT_CSTM_LF3_200GR4)
    {
        cl73_ability.np1_ability1 |= (SYS_PORT_CSTM_LF3_200GR4);
    }
    if(ability & CTC_PORT_CSTM_LL_RS_FEC_REQ)
    {
        cl73_ability.np1_ability1 |= (SYS_PORT_CSTM_LL_RS_FEC_REQ);
    }
    if((cl73_ability.np1_ability0) || (cl73_ability.np1_ability1))
    {
        cl73_ability.base_ability0 |= (SYS_PORT_CL73_NEXT_PAGE);
    }

    /* 2. cfg ability */
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_port_set_cl73_ability(lchip, lport, (void*)(&cl73_ability)));
    MAC_UNLOCK;
    return CTC_E_NONE;
}


int32
_sys_tmm_mac_get_cl73_capability(uint8 lchip, uint16 lport, uint32* p_capability)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if (!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PARAM;
    }

    if (SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        switch(port_attr->pcs_mode)
        {
            case CTC_CHIP_SERDES_XXVG_MODE:
            case CTC_CHIP_SERDES_XFI_MODE:
                if(DRV_CHIP_SUB_TYPE_1 == DRV_CHIP_SUB_TYPE(lchip))
                {
                    *p_capability = (CTC_PORT_CL73_10GBASE_KR |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED);
                }
                else
                {
                    *p_capability = (CTC_PORT_CL73_10GBASE_KR |
                                     CTC_PORT_CL73_25GBASE_KRS |
                                     CTC_PORT_CL73_25GBASE_CRS |
                                     CTC_PORT_CL73_25GBASE_KR |
                                     CTC_PORT_CL73_25GBASE_CR |
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                     CTC_PORT_CL73_25G_BASER_FEC_REQUESTED |
                                     CTC_PORT_CSTM_25GBASE_KR1 |
                                     CTC_PORT_CSTM_25GBASE_CR1 |
                                     CTC_PORT_CSTM_RS_FEC_ABILITY |
                                     CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                     CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                     CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED);
                }
                break;
            case CTC_CHIP_SERDES_LG_MODE:
                *p_capability = (CTC_PORT_CSTM_50GBASE_KR2 |
                                 CTC_PORT_CSTM_50GBASE_CR2 |
                                 CTC_PORT_CSTM_RS_FEC_ABILITY |
                                 CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                 CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                 CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                 CTC_PORT_CL73_FEC_ABILITY |
                                 CTC_PORT_CL73_FEC_REQUESTED);
                break;
            case CTC_CHIP_SERDES_CG_MODE:
            case CTC_CHIP_SERDES_XLG_MODE:
                if(DRV_CHIP_SUB_TYPE_1 == DRV_CHIP_SUB_TYPE(lchip))
                {
                    *p_capability = (CTC_PORT_CL73_40GBASE_KR4 |
                                     CTC_PORT_CL73_40GBASE_CR4 |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED);
                }
                else
                {
                    *p_capability = (CTC_PORT_CL73_40GBASE_KR4 |
                                     CTC_PORT_CL73_40GBASE_CR4 |
                                     CTC_PORT_CL73_100GBASE_KR4 |
                                     CTC_PORT_CL73_100GBASE_CR4 |
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED |
                                     CTC_PORT_CL73_25G_BASER_FEC_REQUESTED);
                }
                break;
            default:
                *p_capability = 0;
                break;
        }
    }
    else if (SYS_TMM_IS_PCS_X16(port_attr->txqm_id))
    {
        switch(port_attr->pcs_mode)
        {
            case CTC_CHIP_SERDES_XXVG_MODE:
            case CTC_CHIP_SERDES_XFI_MODE:
            case CTC_CHIP_SERDES_LG_R1_MODE:
                if(DRV_CHIP_SUB_TYPE_1 == DRV_CHIP_SUB_TYPE(lchip))
                {
                    *p_capability = (CTC_PORT_CL73_10GBASE_KR |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED);
                }
                else if(DRV_CHIP_SUB_TYPE_2 == DRV_CHIP_SUB_TYPE(lchip))
                {
                    *p_capability = (CTC_PORT_CL73_10GBASE_KR |
                                     CTC_PORT_CL73_25GBASE_KRS |
                                     CTC_PORT_CL73_25GBASE_CRS |
                                     CTC_PORT_CL73_25GBASE_KR |
                                     CTC_PORT_CL73_25GBASE_CR |
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                     CTC_PORT_CL73_25G_BASER_FEC_REQUESTED |
                                     CTC_PORT_CSTM_25GBASE_KR1 |
                                     CTC_PORT_CSTM_25GBASE_CR1 |
                                     CTC_PORT_CSTM_RS_FEC_ABILITY |
                                     CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                     CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                     CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED);
                }
                else
                {
                    *p_capability = (CTC_PORT_CL73_10GBASE_KR |
                                     CTC_PORT_CL73_25GBASE_KRS |
                                     CTC_PORT_CL73_25GBASE_CRS |
                                     CTC_PORT_CL73_25GBASE_KR |
                                     CTC_PORT_CL73_25GBASE_CR |
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                     CTC_PORT_CL73_25G_BASER_FEC_REQUESTED |
                                     CTC_PORT_CSTM_25GBASE_KR1 |
                                     CTC_PORT_CSTM_25GBASE_CR1 |
                                     CTC_PORT_CL73_50GBASE_KR |
                                     CTC_PORT_CL73_50GBASE_CR |
                                     CTC_PORT_CSTM_RS_FEC_ABILITY |
                                     CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                     CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                     CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED|
                                     CTC_PORT_CSTM_LF1_50GR1|
                                     CTC_PORT_CSTM_LL_RS_FEC_REQ);
                }
                break;
            case CTC_CHIP_SERDES_CG_R2_MODE:
                *p_capability = (CTC_PORT_CSTM_50GBASE_KR2 |
                                 CTC_PORT_CSTM_50GBASE_CR2 |
                                 CTC_PORT_CL73_100GBASE_KR2 |
                                 CTC_PORT_CL73_100GBASE_CR2 |
                                 CTC_PORT_CSTM_RS_FEC_ABILITY |
                                 CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                 CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                 CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                 CTC_PORT_CL73_FEC_ABILITY |
                                 CTC_PORT_CL73_FEC_REQUESTED|
                                 CTC_PORT_CSTM_LF2_100GR2|
                                 CTC_PORT_CSTM_LL_RS_FEC_REQ|
                                 CTC_PORT_CL73_25G_RS_FEC_REQUESTED);
                break;
            case CTC_CHIP_SERDES_LG_MODE:
                if(DRV_CHIP_SUB_TYPE_2 == DRV_CHIP_SUB_TYPE(lchip))
                {
                    *p_capability = (CTC_PORT_CSTM_50GBASE_KR2 |
                                     CTC_PORT_CSTM_50GBASE_CR2 |
                                     CTC_PORT_CSTM_RS_FEC_ABILITY |
                                     CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                     CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                     CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED|
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED);
                }
                else
                {
                    *p_capability = (CTC_PORT_CSTM_50GBASE_KR2 |
                                     CTC_PORT_CSTM_50GBASE_CR2 |
                                     CTC_PORT_CL73_100GBASE_KR2 |
                                     CTC_PORT_CL73_100GBASE_CR2 |
                                     CTC_PORT_CSTM_RS_FEC_ABILITY |
                                     CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                     CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                     CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED|
                                     CTC_PORT_CSTM_LF2_100GR2|
                                     CTC_PORT_CSTM_LL_RS_FEC_REQ);
                }
                break;
            case CTC_CHIP_SERDES_CG_MODE:
            case CTC_CHIP_SERDES_XLG_MODE:
                if(DRV_CHIP_SUB_TYPE_1 == DRV_CHIP_SUB_TYPE(lchip))
                {
                    *p_capability = (CTC_PORT_CL73_40GBASE_KR4 |
                                     CTC_PORT_CL73_40GBASE_CR4 |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED);
                }
                else
                {
                    *p_capability = (CTC_PORT_CL73_40GBASE_KR4 |
                                     CTC_PORT_CL73_40GBASE_CR4 |
                                     CTC_PORT_CL73_100GBASE_KR4 |
                                     CTC_PORT_CL73_100GBASE_CR4 |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED|
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                     CTC_PORT_CL73_25G_BASER_FEC_REQUESTED);
                }
                break;                
            default:
                *p_capability = 0;
                break;
        }
    }
    else
    {
        switch(port_attr->pcs_mode)
        {
            case CTC_CHIP_SERDES_XXVG_MODE:
            case CTC_CHIP_SERDES_XFI_MODE:
            case CTC_CHIP_SERDES_LG_R1_MODE:
                if((DRV_CHIP_SUB_TYPE_2 == DRV_CHIP_SUB_TYPE(lchip)) || (DRV_CHIP_SUB_TYPE_1 == DRV_CHIP_SUB_TYPE(lchip)))
                {
                    *p_capability = (CTC_PORT_CL73_10GBASE_KR |
                                     CTC_PORT_CL73_25GBASE_KRS |
                                     CTC_PORT_CL73_25GBASE_CRS |
                                     CTC_PORT_CL73_25GBASE_KR |
                                     CTC_PORT_CL73_25GBASE_CR |
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                     CTC_PORT_CL73_25G_BASER_FEC_REQUESTED |
                                     CTC_PORT_CSTM_25GBASE_KR1 |
                                     CTC_PORT_CSTM_25GBASE_CR1 |
                                     CTC_PORT_CSTM_RS_FEC_ABILITY |
                                     CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                     CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                     CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED);
                }
                else
                {
                    *p_capability = (CTC_PORT_CL73_10GBASE_KR |
                                     CTC_PORT_CL73_25GBASE_KRS |
                                     CTC_PORT_CL73_25GBASE_CRS |
                                     CTC_PORT_CL73_25GBASE_KR |
                                     CTC_PORT_CL73_25GBASE_CR |
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                     CTC_PORT_CL73_25G_BASER_FEC_REQUESTED |
                                     CTC_PORT_CSTM_25GBASE_KR1 |
                                     CTC_PORT_CSTM_25GBASE_CR1 |
                                     CTC_PORT_CL73_50GBASE_KR |
                                     CTC_PORT_CL73_50GBASE_CR |
                                     CTC_PORT_CSTM_RS_FEC_ABILITY |
                                     CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                     CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                     CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED|
                                     CTC_PORT_CSTM_LF1_50GR1|
                                     CTC_PORT_CSTM_LL_RS_FEC_REQ);
                }
                break;
            case CTC_CHIP_SERDES_LG_MODE:
                if((DRV_CHIP_SUB_TYPE_2 == DRV_CHIP_SUB_TYPE(lchip)) || (DRV_CHIP_SUB_TYPE_1 == DRV_CHIP_SUB_TYPE(lchip)))
                {
                    *p_capability = (CTC_PORT_CSTM_50GBASE_KR2 |
                                     CTC_PORT_CSTM_50GBASE_CR2 |
                                     CTC_PORT_CSTM_RS_FEC_ABILITY |
                                     CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                     CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                     CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED|
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED);
                }
                else
                {
                    *p_capability = (CTC_PORT_CSTM_50GBASE_KR2 |
                                     CTC_PORT_CSTM_50GBASE_CR2 |
                                     CTC_PORT_CL73_100GBASE_KR2 |
                                     CTC_PORT_CL73_100GBASE_CR2 |
                                     CTC_PORT_CSTM_RS_FEC_ABILITY |
                                     CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                     CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                     CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED|
                                     CTC_PORT_CSTM_LF2_100GR2|
                                     CTC_PORT_CSTM_LL_RS_FEC_REQ);
                }
                break;
            case CTC_CHIP_SERDES_CG_R2_MODE:
                *p_capability = (CTC_PORT_CSTM_50GBASE_KR2 |
                                 CTC_PORT_CSTM_50GBASE_CR2 |
                                 CTC_PORT_CL73_100GBASE_KR2 |
                                 CTC_PORT_CL73_100GBASE_CR2 |
                                 CTC_PORT_CSTM_RS_FEC_ABILITY |
                                 CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                 CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                 CTC_PORT_CSTM_BASER_FEC_REQUESTED |
                                 CTC_PORT_CL73_FEC_ABILITY |
                                 CTC_PORT_CL73_FEC_REQUESTED|
                                 CTC_PORT_CSTM_LF2_100GR2|
                                 CTC_PORT_CSTM_LL_RS_FEC_REQ|
                                 CTC_PORT_CL73_25G_RS_FEC_REQUESTED);
                break;
            case CTC_CHIP_SERDES_CG_MODE:
            case CTC_CHIP_SERDES_XLG_MODE:
            case CTC_CHIP_SERDES_CCG_R4_MODE:
                if((DRV_CHIP_SUB_TYPE_2 == DRV_CHIP_SUB_TYPE(lchip)) || (DRV_CHIP_SUB_TYPE_1 == DRV_CHIP_SUB_TYPE(lchip)))
                {
                    *p_capability = (CTC_PORT_CL73_40GBASE_KR4 |
                                     CTC_PORT_CL73_40GBASE_CR4 |
                                     CTC_PORT_CL73_100GBASE_KR4 |
                                     CTC_PORT_CL73_100GBASE_CR4 |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED|
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                     CTC_PORT_CL73_25G_BASER_FEC_REQUESTED);
                }
                else
                {
                    *p_capability = (CTC_PORT_CL73_40GBASE_KR4 |
                                     CTC_PORT_CL73_40GBASE_CR4 |
                                     CTC_PORT_CL73_100GBASE_KR4 |
                                     CTC_PORT_CL73_100GBASE_CR4 |
                                     CTC_PORT_CL73_200GBASE_KR4 |
                                     CTC_PORT_CL73_200GBASE_CR4 |
                                     CTC_PORT_CL73_25G_RS_FEC_REQUESTED |
                                     CTC_PORT_CL73_FEC_ABILITY |
                                     CTC_PORT_CL73_FEC_REQUESTED |
                                     CTC_PORT_CL73_25G_BASER_FEC_REQUESTED|
                                     CTC_PORT_CSTM_LF3_200GR4|
                                     CTC_PORT_CSTM_LL_RS_FEC_REQ);
                }
                break;
            case CTC_CHIP_SERDES_CDG_R8_MODE:
                *p_capability = (CTC_PORT_CSTM_400GBASE_CR8 |
                                 CTC_PORT_CSTM_RS_FEC_ABILITY |
                                 CTC_PORT_CSTM_BASER_FEC_ABILITY |
                                 CTC_PORT_CSTM_RS_FEC_REQUESTED |
                                 CTC_PORT_CSTM_BASER_FEC_REQUESTED);
                break;
            default:
                *p_capability = 0;
                break;
        }
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_nw_sgmii_unidir_en(uint8 lchip, sys_datapath_lport_attr_t* port_attr, uint8 enable)
{
    uint32 tbl_id           = 0;
    uint8  pcs_idx          = port_attr->pcs_idx;
    uint32 fld_id           = 0;
    uint32 index            = 0;
    uint32 cmd              = 0;
    uint32 step             = 0;
    uint32 value            = enable ? 1 : 0;
    uint8  is_pcs_x16       = 0;
    uint8  pcs_x8_x16_index = 0;
    McPcsX8LanesSgmiiCfg_m pcs_x8_cfg;
    McPcsX16LanesSgmiiCfg_m pcs_x16_cfg;

    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
    index = DRV_INS(pcs_x8_x16_index, 0);

    if(is_pcs_x16)
    {
        tbl_id = McPcsX16LanesSgmiiCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_cfg));
        
        step = McPcsX16LanesSgmiiCfg_cfgSgmii_1_unidirectionEn_f - McPcsX16LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f;
        fld_id = McPcsX16LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f + step*pcs_idx;

        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &value, &pcs_x16_cfg, pcs_x8_x16_index, 0);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_cfg));
    }
    else
    {
        tbl_id = McPcsX8LanesSgmiiCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_cfg));
        
        step = McPcsX8LanesSgmiiCfg_cfgSgmii_1_unidirectionEn_f - McPcsX8LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f;
        fld_id = McPcsX8LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f + step*pcs_idx;

        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &value, &pcs_x8_cfg, pcs_x8_x16_index, 0);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_cfg));
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_unidir_en(uint8 lchip, uint16 lport, uint8 enable, uint8 force_cfg)
{
    uint8  internal_mac_idx = 0;
    uint8  pcs_idx = 0;
    uint32 index  = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd = 0;
    uint32 step   = 0;
    uint32 value = 0;
    uint32 pcs_x8_x16_index = 0;
    uint32 is_bind_flexe_group           = 0;
    uint32 an_en_stat = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    McPcsX16LanesQsgmiiCfg_m pcs_qsgmii_cfg;
    McMacMiiTxCfg_m mii_tx_cfg;
    SharedPcsCfg_m shared_pcs_cfg;
    SharedMii0Cfg_m shared_mii_cfg;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN((SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type), CTC_E_NONE);

    if (!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC is not used \n");
        return CTC_E_INVALID_PORT;
    }

    CTC_ERROR_RETURN(sys_tmm_flexe_check_serdes_bind_group(lchip, port_attr->multi_serdes_id[0], &is_bind_flexe_group));
    if (is_bind_flexe_group)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% SerDes %d is bind to flexe group, cannot run unidir config ! \n", port_attr->multi_serdes_id[0]);
        return CTC_E_INVALID_CONFIG;
    }

    /*if auto-neg enable, cannot set unidir enable*/
    if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_get_cl37_en(lchip, lport, &an_en_stat));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_usw_mac_get_cl73_auto_neg(lchip, lport, CTC_PORT_PROP_AUTO_NEG_EN, &an_en_stat));
    }
    if(an_en_stat && (!force_cfg))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Lport %u has enable auto-nego, cannot config unidir! \n", lport);
        return CTC_E_INVALID_CONFIG;
    }

    value = enable ? 1 : 0;
    internal_mac_idx = port_attr->internal_mac_idx;
    pcs_idx = port_attr->pcs_idx;

    if(!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_TMM_GET_PCSXIDX(port_attr->txqm_id, pcs_x8_x16_index);
        index = DRV_INS(pcs_x8_x16_index, 0);

        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)|| (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_nw_sgmii_unidir_en(lchip, port_attr, enable));
        }
        else if(CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
        {
            tbl_id = McPcsX16LanesQsgmiiCfg_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_cfg));
            
            step = McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_unidirectionEn_f - McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_unidirectionEn_f;
            fld_id = McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_unidirectionEn_f + step*internal_mac_idx;

            DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &pcs_qsgmii_cfg);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_cfg));
        }
        else
        {
            index = DRV_INS(port_attr->txqm_id, 0);

            tbl_id = McMacMiiTxCfg_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_tx_cfg));
            
            step = McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxIgnoreRemoteFault_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreRemoteFault_f;
            
            fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreRemoteFault_f + step*internal_mac_idx;
            DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mii_tx_cfg);
            
            fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreLocalFault_f + step*internal_mac_idx;
            DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mii_tx_cfg);
            
            fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreLintFault_f + step*internal_mac_idx;
            DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mii_tx_cfg);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_tx_cfg));
        }
    }
    else
    {
         if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)|| (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode) 
                                                                 || (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode))
         {
            tbl_id = SharedPcsCfg_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

            step = SharedPcsCfg_unidirectionEn1_f - SharedPcsCfg_unidirectionEn0_f;
            fld_id = SharedPcsCfg_unidirectionEn0_f + step * pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &shared_pcs_cfg);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));
         }
         else
         {
            tbl_id = SharedMii0Cfg_t + pcs_idx *(SharedMii1Cfg_t - SharedMii0Cfg_t);
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_mii_cfg));

            fld_id = SharedMii0Cfg_cfgMiiIgnoreRemoteFault0_f;
            DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &shared_mii_cfg);

            fld_id = SharedMii0Cfg_cfgMiiIgnoreLocalFault0_f;
            DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &shared_mii_cfg);

            fld_id = SharedMii0Cfg_cfgMiiIgnoreLintFault0_f;
            DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &shared_mii_cfg);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_mii_cfg));
         }
    }

    p_usw_mac_master[lchip]->mac_prop[lport].unidir_en = value;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_unidir_en(uint8 lchip, uint16 lport, uint8 enable)
{

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_unidir_en(lchip, lport, enable, FALSE));
    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_unidir_en(uint8 lchip, uint16 lport, uint32* p_value)
{
    uint8  internal_mac_idx = 0;
    uint8  pcs_idx = 0;
    uint32 is_pcs_x16 = 0;
    uint32 index  = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd = 0;
    uint32 step   = 0;
    uint32 pcs_x8_x16_index = 0;
    uint32 value = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    McPcsX8LanesSgmiiCfg_m pcs_x8_cfg;
    McPcsX16LanesSgmiiCfg_m pcs_x16_cfg;
    McPcsX16LanesQsgmiiCfg_m pcs_qsgmii_cfg;
    SharedPcsCfg_m shared_pcs_cfg;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN((SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type), CTC_E_NONE);

    if (!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC is not used \n");
        return CTC_E_INVALID_PORT;
    }

    internal_mac_idx = port_attr->internal_mac_idx;
    pcs_idx = port_attr->pcs_idx;

    if(!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
        index = DRV_INS(pcs_x8_x16_index, 0);

        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)|| (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            if(is_pcs_x16)
            {
                tbl_id = McPcsX16LanesSgmiiCfg_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_cfg));
                step = McPcsX16LanesSgmiiCfg_cfgSgmii_1_unidirectionEn_f - McPcsX16LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f;
                fld_id = McPcsX16LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f + step*pcs_idx;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &pcs_x16_cfg);
            }
            else
            {
                tbl_id = McPcsX8LanesSgmiiCfg_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_cfg));
                step = McPcsX8LanesSgmiiCfg_cfgSgmii_1_unidirectionEn_f - McPcsX8LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f;
                fld_id = McPcsX8LanesSgmiiCfg_cfgSgmii_0_unidirectionEn_f + step*pcs_idx;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &pcs_x8_cfg);
            }
        }
        else if(CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
        {
            tbl_id = McPcsX16LanesQsgmiiCfg_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_cfg));
            step = McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_unidirectionEn_f - McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_unidirectionEn_f;
            fld_id = McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_unidirectionEn_f + step*internal_mac_idx;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &pcs_qsgmii_cfg);
        }
        else
        {
            value = p_usw_mac_master[lchip]->mac_prop[lport].unidir_en;
        }
    }
    else
    {
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            tbl_id = SharedPcsCfg_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));
            step = SharedPcsCfg_unidirectionEn1_f - SharedPcsCfg_unidirectionEn0_f;
            fld_id = SharedPcsCfg_unidirectionEn0_f + step * pcs_idx;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &shared_pcs_cfg);
        }
        else
        {
            value = p_usw_mac_master[lchip]->mac_prop[lport].unidir_en;
        }
    }
    SYS_USW_VALID_PTR_WRITE(p_value, value);

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_unidir_en(uint8 lchip, uint16 lport, uint32* p_value)
{

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_unidir_en(lchip, lport, p_value));
    MAC_UNLOCK;
    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_mac_set_speed(uint8 lchip, uint16 lport, ctc_port_speed_t speed_mode)
{
    uint8  mac_en_flag = (uint8)(p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en);
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    /*if mac enable, first mac disable, then mac enable again */
    if(mac_en_flag)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_en(lchip, lport, FALSE));
    }

    port_attr->speed_mode = speed_mode;

    if((SYS_DMPS_NETWORK_PORT == port_attr->port_type) || (SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type))
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mcmac_config(lchip, lport, port_attr->pcs_mode, CTC_PORT_FEC_TYPE_NONE, MACPCS_CFG_SPEED));
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mcpcs_config(lchip, lport, port_attr->pcs_mode, CTC_PORT_FEC_TYPE_NONE, MACPCS_CFG_SPEED));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_sgmii_config(lchip, lport)); 
    }

    if(mac_en_flag)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
    }

    return CTC_E_NONE;
}

STATIC int32
sys_tmm_mac_set_speed(uint8 lchip, uint16 lport, ctc_port_speed_t speed_mode)
{
    uint32 auto_neg_en = 0;
    uint8  valid_flag  = FALSE;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    /*config valid check*/
    if((SYS_DMPS_NETWORK_PORT == port_attr->port_type) || (SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type))
    {
        if (((port_attr->pcs_mode == CTC_CHIP_SERDES_SGMII_MODE) && 
             ((speed_mode == CTC_PORT_SPEED_1G) || (speed_mode == CTC_PORT_SPEED_100M) || (speed_mode == CTC_PORT_SPEED_10M))) || 
            ((port_attr->pcs_mode == CTC_CHIP_SERDES_QSGMII_MODE) && 
             ((speed_mode == CTC_PORT_SPEED_1G) || (speed_mode == CTC_PORT_SPEED_100M) || (speed_mode == CTC_PORT_SPEED_10M))))
        {
            valid_flag = TRUE;
        }
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        if((port_attr->pcs_mode == CTC_CHIP_SERDES_SGMII_MODE) && 
           ((speed_mode == CTC_PORT_SPEED_1G) || (speed_mode == CTC_PORT_SPEED_100M) || (speed_mode == CTC_PORT_SPEED_10M)))
        {
            valid_flag = TRUE;
        }
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC is not used \n");
        return CTC_E_INVALID_PORT; 
    }

    if(!valid_flag)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% PCS mode %u DO NOT support to config mac speed %u\n", 
            port_attr->pcs_mode, speed_mode);
        return CTC_E_INVALID_PARAM;
    }

    if (port_attr->speed_mode == speed_mode)
    {
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(_sys_tmm_mac_get_cl37_en(lchip, lport, &auto_neg_en));
    if ((CTC_E_NONE == sys_usw_phy_get_phy_register_exist(lchip, lport)) && (0 == auto_neg_en))
    {
        uint32 value = speed_mode;
        CTC_ERROR_RETURN(sys_usw_phy_set_phy_property(lchip, lport, CTC_PORT_PROP_SPEED, (void*)&value));
    }

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_speed(lchip, lport, speed_mode));
    MAC_UNLOCK;

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_mac_get_speed(uint8 lchip, uint16 lport, ctc_port_speed_t* p_speed_mode)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if ((!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type)) && (SYS_DMPS_INACTIVE_NETWORK_PORT != port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC is not used \n");
        return CTC_E_INVALID_PORT;
    }

    *p_speed_mode = port_attr->speed_mode;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_speed(uint8 lchip, uint16 lport, uint32* p_value)
{

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_speed(lchip, lport, p_value));
    MAC_UNLOCK;
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_sgmii_hata_reset_recover(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr)
{
    SYS_CONDITION_RETURN(((SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_A) || (FALSE == g_hata_sgmii_en) || 
        (SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type)) || (TRUE == p_usw_mac_master[lchip]->mac_prop[lport].unidir_en) ||
        ((CTC_CHIP_SERDES_SGMII_MODE != port_attr->pcs_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != port_attr->pcs_mode))), 
        CTC_E_NONE);

    CTC_ERROR_RETURN(_sys_tmm_mac_set_nw_sgmii_unidir_en(lchip, port_attr, 0));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_cl37_auto_neg_en(uint8 lchip, uint16 lport, uint32 enable)
{
    uint16 step       = 0;
    uint32 cmd        = 0;
    uint32 tbl_id     = 0;
    uint32 field_id   = 0;
    uint32 value      = 0;
    uint8  pcs_idx    = 0;
    uint32 unidir_en  = 0;
    uint32 factor = 0;
    uint32 index = 0;
    uint32 is_pcs_x16 = 0;  
    uint32 pcs_x8_x16_index = 0;
    uint32 parallel_dect_en = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    /* if unidir enable, cannot set AN enable */
    CTC_ERROR_RETURN(_sys_tmm_mac_get_unidir_en(lchip, lport, &unidir_en));
    if(enable && unidir_en)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% lport %u has enable unidir, cannot enable auto-nego! \n", lport);
        return CTC_E_INVALID_CONFIG;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if(port_attr == NULL)
    {
        return CTC_E_INVALID_PTR;
    }
    if(!enable)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_sgmii_hata_reset_recover(lchip, lport, port_attr));
    }

    if ((!enable) && ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || 
                            (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode) ||
                                (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)))
    {
        switch(port_attr->pcs_mode)
        {
            case CTC_CHIP_SERDES_QSGMII_MODE:
                CTC_ERROR_RETURN(_sys_tmm_mac_qsgmii_get_parallel_detect_en(lchip, lport, &parallel_dect_en));
                break;
            default:
                CTC_ERROR_RETURN(_sys_tmm_mac_sgmii_get_parallel_detect_en(lchip, lport, &parallel_dect_en));
                break;
        }
        
        if(parallel_dect_en)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% lport %u has enable parallel detect, cannot disable auto-nego. \n", lport);
            return CTC_E_INVALID_CONFIG;
        }
    }

    if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            index = 0;
            pcs_idx = port_attr->pcs_idx;
            step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
            tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
            field_id = SharedPcsSgmii0Cfg_anEnable0_f;
            cmd = DRV_IOW(tbl_id, field_id);
            value = enable ? 1 : 0;
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        }
    }
    else
    {
        SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
        index = DRV_INS(pcs_x8_x16_index, 0);  
        pcs_idx = port_attr->pcs_idx;
        value = enable ? 1 : 0;
        /*sgmii config */
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            /*HS PORT */
            if(is_pcs_x16)
            {                
                /*enable/disable */
                tbl_id=McPcsX16LanesSgmiiCfg_t;         
                step=McPcsX16LanesSgmiiCfg_cfgSgmii_1_anEnable_f-McPcsX16LanesSgmiiCfg_cfgSgmii_0_anEnable_f;
                factor = pcs_idx;
                field_id=McPcsX16LanesSgmiiCfg_cfgSgmii_0_anEnable_f+step*factor;
                cmd = DRV_IOW(tbl_id, field_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));

            }
            else
            {
                /*enable/disable */
                tbl_id=McPcsX8LanesSgmiiCfg_t;
                step=McPcsX8LanesSgmiiCfg_cfgSgmii_1_anEnable_f-McPcsX8LanesSgmiiCfg_cfgSgmii_0_anEnable_f;
                factor = pcs_idx;                    
                field_id=McPcsX8LanesSgmiiCfg_cfgSgmii_0_anEnable_f+step*factor;
                cmd = DRV_IOW(tbl_id, field_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));

            }
        }
        else if(CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
        {
            /*enable/disable */
            tbl_id=McPcsX16LanesQsgmiiCfg_t;
            step=McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_anEnable_f-McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anEnable_f;
            factor = port_attr->mac_id-(SYS_TMM_MAX_MAC_NUM_PER_TXQM*port_attr->txqm_id);
            field_id=McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anEnable_f+step*factor;
            cmd = DRV_IOW(tbl_id, field_id);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        }
    }

    return CTC_E_NONE; 
}

int32
_sys_tmm_mac_get_cl37_en(uint8 lchip, uint16 lport, uint32* p_en)
{
    uint32 cmd              = 0;
    uint32 tbl_id           = 0;
    uint32 field_id         = 0;
    uint16 step             = 0;
    uint8  pcs_idx          = 0;
    uint32 value            = 0;
    uint32 factor           = 0;
    uint32 index            = 0;
    uint32 is_pcs_x16       = 0;
    uint32 pcs_x8_x16_index = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
    index = DRV_INS(pcs_x8_x16_index, 0);
    if((port_attr->port_type != SYS_DMPS_NETWORK_PORT) && (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type)))
    {
        return CTC_E_INVALID_PARAM;
    }
    pcs_idx = port_attr->pcs_idx;
    /* SGMII/QSGMII mode auto neg */
    if(SYS_MAC_IS_MODE_SUPPORT_CL37(port_attr->pcs_mode))
    {
        if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
        {
            if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) ||
               (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
                index = 0;
                pcs_idx = port_attr->pcs_idx;
                step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
                tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
                field_id = SharedPcsSgmii0Cfg_anEnable0_f;
                cmd = DRV_IOR(tbl_id, field_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
            }
        }
        else
        {
            if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) ||
               (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
                if(1==is_pcs_x16)
                {
                    tbl_id=McPcsX16LanesSgmiiCfg_t;
                    step=McPcsX16LanesSgmiiCfg_cfgSgmii_1_anEnable_f-McPcsX16LanesSgmiiCfg_cfgSgmii_0_anEnable_f;
                    factor = pcs_idx;
                    field_id=McPcsX16LanesSgmiiCfg_cfgSgmii_0_anEnable_f+step*factor;
                    cmd = DRV_IOR(tbl_id, field_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
                }
                else if(0==is_pcs_x16)
                {
                    tbl_id=McPcsX8LanesSgmiiCfg_t;
                    step=McPcsX8LanesSgmiiCfg_cfgSgmii_1_anEnable_f-McPcsX8LanesSgmiiCfg_cfgSgmii_0_anEnable_f;
                    factor = pcs_idx;
                    field_id=McPcsX8LanesSgmiiCfg_cfgSgmii_0_anEnable_f+step*factor;
                    cmd = DRV_IOR(tbl_id, field_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
                }
            }
            else if (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
            {
                tbl_id=McPcsX16LanesQsgmiiCfg_t;
                step=McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_anEnable_f-McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anEnable_f;
                factor = port_attr->mac_id-(SYS_TMM_MAX_MAC_NUM_PER_TXQM*port_attr->txqm_id);
                field_id=McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anEnable_f+step*factor;
                cmd = DRV_IOR(tbl_id, field_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
            }
        }
    }
    SYS_USW_VALID_PTR_WRITE(p_en, value);
    return CTC_E_NONE; 
}

int32
_sys_tmm_mac_get_cl37_mode(uint8 lchip, uint16 lport, uint32* p_mode)
{
    uint32 cmd              = 0;
    uint32 tbl_id           = 0;
    uint32 field_id         = 0;
    uint16 step             = 0;
    uint8  pcs_idx          = 0;
    uint32 value            = 0;
    uint32 factor           = 0;
    uint32 index            = 0;
    uint32 is_pcs_x16       = 0;
    uint32 pcs_x8_x16_index = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
    index = DRV_INS(pcs_x8_x16_index, 0);
    if((port_attr->port_type != SYS_DMPS_NETWORK_PORT) && (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type)))
    {
        return CTC_E_INVALID_PARAM;
    }
    pcs_idx = port_attr->pcs_idx;
    /* SGMII/QSGMII mode auto neg */
    if(SYS_MAC_IS_MODE_SUPPORT_CL37(port_attr->pcs_mode))
    {
        if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
        {
            index = 0;
            pcs_idx = port_attr->pcs_idx;

            if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) ||
               (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
                step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
                tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
                field_id = SharedPcsSgmii0Cfg_anegMode0_f;
                cmd = DRV_IOR(tbl_id, field_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
            }
            /* CPUMAC inherit from tsingma  1000Base-X(2'b00), SGMII-Slaver(2'b10) */
            if(0 == value)
            {
                value = CTC_PORT_AUTO_NEG_MODE_1000BASE_X;
            }
            else if (2 == value)
            {
                value = CTC_PORT_AUTO_NEG_MODE_SGMII_SLAVER;
            }
        }
        else
        {
            if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) ||
               (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
                if(1==is_pcs_x16)
                {
                    tbl_id=McPcsX16LanesSgmiiCfg_t;
                    factor= pcs_idx;
                    step=McPcsX16LanesSgmiiCfg_cfgSgmii_1_anegMode_f-McPcsX16LanesSgmiiCfg_cfgSgmii_0_anegMode_f;
                    field_id=McPcsX16LanesSgmiiCfg_cfgSgmii_0_anegMode_f+step*factor;
                    cmd = DRV_IOR(tbl_id, field_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
                }
                else if(0==is_pcs_x16)
                {
                    tbl_id=McPcsX8LanesSgmiiCfg_t;
                    factor= pcs_idx;
                    step=McPcsX8LanesSgmiiCfg_cfgSgmii_1_anegMode_f-McPcsX8LanesSgmiiCfg_cfgSgmii_0_anegMode_f;
                    field_id=McPcsX8LanesSgmiiCfg_cfgSgmii_0_anegMode_f+step*factor;
                    cmd = DRV_IOR(tbl_id, field_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
                }
            }
            else if (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
            {
                tbl_id=McPcsX16LanesQsgmiiCfg_t;
                step=McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_anegMode_f-McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anegMode_f;
                factor = port_attr->mac_id-(SYS_TMM_MAX_MAC_NUM_PER_TXQM*port_attr->txqm_id);
                field_id=McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anegMode_f+step*factor;
                cmd = DRV_IOR(tbl_id, field_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
            }

            if(0 == value)
            {
                value = CTC_PORT_AUTO_NEG_MODE_1000BASE_X;
            }
            else if (2 == value)
            {
                value = CTC_PORT_AUTO_NEG_MODE_SGMII_MASTER;
            }
            else if (1 == value)
            {
                value = CTC_PORT_AUTO_NEG_MODE_SGMII_SLAVER;
            }
        }
    }
    SYS_USW_VALID_PTR_WRITE(p_mode, value);
    return CTC_E_NONE; 
}

/*McMacMiiRxDebugStats.dbgMcMacMiiRx_0.39_dbgMiiRxBuffEmpty*/
int32
_sys_tmm_mac_wait_rx_buf_empty(uint8 lchip, uint16 mac_id)
{
    uint32 times     = 10000;
    uint32 index     = 0;
    uint32 cmd       = 0;
    uint32 fld_id    = 0;
    uint32 is_empty  = 0;
    uint32 txqm_id   = mac_id / SYS_TMM_MAX_MAC_NUM_PER_TXQM;
    uint32 inner_mac = SYS_TMM_GET_MACID_PER_TXQM(mac_id);
    McMacMiiRxDebugStats_m mii_rx;

    SYS_CONDITION_RETURN(SYS_TMM_MAX_MAC_NUM <= mac_id, CTC_E_NONE);

    index  = DRV_INS(txqm_id, 0);
    fld_id = McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxBuffEmpty_f + inner_mac * 
             (McMacMiiRxDebugStats_dbgMcMacMiiRx_1_dbgMiiRxBuffEmpty_f - McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxBuffEmpty_f);
    cmd = DRV_IOR(McMacMiiRxDebugStats_t, DRV_ENTRY_FLAG);

    while(--times)
    {
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_rx));
        DRV_IOR_FIELD(lchip, McMacMiiRxDebugStats_t, fld_id, &is_empty, &mii_rx);
        if(1 == is_empty)
        {
            return CTC_E_NONE;
        }
    }

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% RX MII buf is not empty! mac_id %u\n", mac_id);

    return CTC_E_NONE;
}

/* support 802.3ap, Auto-Negotiation for Backplane Ethernet */
int32
_sys_tmm_mac_set_cl73_auto_neg_en(uint8 lchip, uint16 lport, uint32 enable, uint8 restart)
{
    sys_datapath_lport_attr_t* port_attr = NULL;
    uint16 real_serdes = 0;
    uint8  cnt = 0;
    uint32 unidir_en = 0;
    uint32 is_bind_flexe_group   = 0;
    uint8  tx_en = 0;
    uint8  mac_toggle = ((!enable) && (TRUE == p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en) && (FALSE == restart)) ? 
                        TRUE : FALSE;
    ctc_chip_serdes_loopback_t lb_param;

    if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
    {
        return CTC_E_NONE;
    }

    SYS_CL73_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "Enter %s\n", __FUNCTION__);
    SYS_CL73_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d, cl73 auto enable:0x%X\n", lport, enable);
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_EN, (uint16)enable);
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_RESTART, (uint16)restart);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    /* if unidir enable, cannot set AN enable or restart AN*/
    CTC_ERROR_RETURN(_sys_tmm_mac_get_unidir_en(lchip, lport, &unidir_en));
    if(enable && unidir_en)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% lport %u has enable unidir, cannot enable auto-nego! \n", lport);
        return CTC_E_INVALID_CONFIG;
    }

    /* auto-neg already enable, cann't set enable again*/
    if ((enable && p_usw_mac_master[lchip]->mac_prop[lport].cl73_enable)
        || ((!enable) && (!p_usw_mac_master[lchip]->mac_prop[lport].cl73_enable)))
    {
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }
    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num, CTC_E_INVALID_PARAM);

    port_attr->lt_done_num = 0;
    p_usw_mac_master[lchip]->mac_prop[lport].old_cl73_status = 0;

    CTC_ERROR_RETURN(sys_tmm_flexe_check_serdes_bind_group(lchip, port_attr->multi_serdes_id[0], &is_bind_flexe_group));
    /*if (is_bind_flexe_group)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% SerDes %d is bind to flexe group, cannot run auto-neg ! \n", port_attr->multi_serdes_id[0]);
        return CTC_E_PARAM_CONFLICT;
    }*/

    /* if serdes loopback enable, cannot set enable */
    for(cnt = 0; cnt < port_attr->serdes_num; cnt++)
    {
        real_serdes = port_attr->multi_serdes_id[cnt];
        sal_memset(&lb_param, 0, sizeof(ctc_chip_serdes_loopback_t));
        lb_param.serdes_id = real_serdes;
        lb_param.mode = 0;
        CTC_ERROR_RETURN(_sys_tmm_datapath_get_serdes_loopback(lchip, (void*)&lb_param));
        if (lb_param.enable)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Serdes %d is in loopback internal mode \n", real_serdes);
            return CTC_E_INVALID_CONFIG;
        }
        lb_param.mode = 1;
        CTC_ERROR_RETURN(_sys_tmm_datapath_get_serdes_loopback(lchip, (void*)&lb_param));
        if (1 == lb_param.enable)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Serdes %d is in loopback external mode \n", real_serdes);
            return CTC_E_INVALID_CONFIG;
        }
    }

    if (enable)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_pcs_rx_rst(lchip, lport, TRUE));
        CTC_ERROR_RETURN(_sys_tmm_mac_wait_rx_buf_empty(lchip, port_attr->mac_id));
        CTC_ERROR_RETURN(_sys_tmm_mac_mii_rx_rst(lchip, lport, TRUE));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_mii_rx_rst(lchip, lport, FALSE));
        CTC_ERROR_RETURN(_sys_tmm_mac_pcs_rx_rst(lchip, lport, FALSE));
    }
    
    for(cnt = 0; cnt < port_attr->serdes_num; cnt++)
    {
        tx_en = 0;
        real_serdes = port_attr->multi_serdes_id[cnt];
        (void)sys_tmm_serdes_get_tx_en(lchip, real_serdes, &tx_en);
        if(0 == tx_en) break;
    }
    if(tx_en || (restart && enable))
    {
        /*do mac & pcs rst when disable AN*/
        if(mac_toggle)
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_en(lchip, lport, FALSE));
        }

        port_attr->is_first = 0;

        for(cnt = 0; cnt < port_attr->serdes_num; cnt++)
        {
            real_serdes = port_attr->multi_serdes_id[cnt];
            if (!enable)
            {
                /* if disable, need do 3ap training disable first */
                sys_tmm_serdes_set_link_training_en(lchip, real_serdes, FALSE);
            }

            /* 2. enable 3ap auto-neg */
            CTC_ERROR_RETURN(sys_tmm_serdes_set_serdes_auto_neg_en(lchip, real_serdes, enable));
        }

        if(mac_toggle)
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
        }
    }

    p_usw_mac_master[lchip]->mac_prop[lport].cl73_enable = enable;

    SYS_CL73_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "Exit %s\n", __FUNCTION__);

    return CTC_E_NONE;
}

/* get serdes status by gport, sigdet | phyready*/
int32
_sys_tmm_mac_get_port_serdes_stat(uint8 lchip, uint16 lport, uint8 stat_type, uint32* p_stat)
{
    uint8  idx;
    uint8  is_detect = 0;
    uint32 phy_ready = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }
    if(CTC_PORT_IF_FLEXE == port_attr->interface_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% FlexE client mac DONOT support this feature \n");
        return CTC_E_INVALID_PORT;
    }
    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num, CTC_E_INVALID_PARAM);

    switch(stat_type)
    {
        case SYS_MAC_SERDES_SIGDET:
            for(idx = 0; idx < port_attr->serdes_num; idx++)
            {
                CTC_ERROR_RETURN(sys_tmm_serdes_get_signal_detect(lchip, port_attr->multi_serdes_id[idx], &is_detect, NULL));
                if(0 == is_detect)
                {
                    break;
                }
            }
            SYS_USW_VALID_PTR_WRITE(p_stat, is_detect);
            break;
        case SYS_MAC_SERDES_READY:
            for(idx = 0; idx < port_attr->serdes_num; idx++)
            {
                CTC_ERROR_RETURN(sys_tmm_serdes_get_phyready(lchip, port_attr->multi_serdes_id[idx], &phy_ready));
                if(0 == phy_ready)
                {
                    break;
                }
            }
            SYS_USW_VALID_PTR_WRITE(p_stat, phy_ready);
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_mac_signal_detect(uint8 lchip, uint16 lport, uint32* p_is_detect)
{
    if(NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_port_serdes_stat(lchip, lport, SYS_MAC_SERDES_SIGDET, p_is_detect));
    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_intr_get_table_bitmap(uint8 lchip, uint16 mac_id, uint32* tb_id, uint32* tb_index, uint32* value)
{
    uint16 inner_mac_id = 0;

    if (mac_id < 40)
    {
        *tb_id = CtcHsCtlInterruptFunc_t;
        *tb_index = 0;
        inner_mac_id = mac_id;
    }
    else if (mac_id <80)
    {
        *tb_id = CtcHsCtlInterruptFunc_t;
        *tb_index = 1;
        inner_mac_id = mac_id - 40;
    }
    else if (mac_id <120)
    {
        *tb_id = CtcCsCtlInterruptFunc_t;
        *tb_index = 0;
        inner_mac_id = mac_id - 80;
    }
    else if (mac_id <160)
    {
        *tb_id = CtcCsCtlInterruptFunc_t;
        *tb_index = 1;
        inner_mac_id = mac_id - 120;
    }
    else if (mac_id <200)
    {
        *tb_id = CtcHsCtlInterruptFunc_t;
        *tb_index = 2;
        inner_mac_id = mac_id - 160;
    }
    else if (mac_id <240)
    {
        *tb_id = CtcHsCtlInterruptFunc_t;
        *tb_index = 3;
        inner_mac_id = mac_id - 200;
    }
    else if (mac_id <280)
    {
        *tb_id = CtcCsCtlInterruptFunc_t;
        *tb_index = 2;
        inner_mac_id = mac_id - 240;
    }
    else if(mac_id < 320)
    {
        *tb_id = CtcCsCtlInterruptFunc_t;
        *tb_index = 3;
        inner_mac_id = mac_id - 280;
    }
    else
    {
        *tb_id = CpuMacProcInterruptFunc_t;
        *tb_index = 0;
        inner_mac_id = mac_id - 320;
    }

    if (inner_mac_id < 15)
    {
        if(CpuMacProcInterruptFunc_t == (*tb_id))
        {
            value[0] = 0x11 << (3 - inner_mac_id);
        }
        else
        {
            value[0] = 6 << 2 * inner_mac_id;
        }
    }
    else if (inner_mac_id == 15)
    {
        value[0] = 0x8000;
        value[1] = 1;
    }
    else if (inner_mac_id < 31)
    {
        value[1] = 6 << 2 * (inner_mac_id - 16);
    }
    else if (inner_mac_id == 31)
    {
        value[1] = 0x8000;
        value[2] = 1;
    }
    else
    {
        value[2] = 6 << 2 * (inner_mac_id - 32);
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_intr_get_flexe_table_bitmap(uint8 lchip, sys_datapath_lport_attr_t* port_attr, uint32* tb_id, uint32* tb_index, uint32* value)
{
    uint8 i = 0;
    uint8 lane_num = 0;
    uint8 pcs_l_id = 0;
    if (SYS_DMPS_INACTIVE_NETWORK_PORT != port_attr->port_type)
    {
        return CTC_E_INVALID_CONFIG;
    }

    *tb_id = CtcCsCtlInterruptFunc_t;
    
    if ((port_attr->multi_serdes_id[0] >= 32)
        && (port_attr->multi_serdes_id[0] <= 39))
    {
        *tb_index = 0;
    }
    else if ((port_attr->multi_serdes_id[0] >= 40)
        && (port_attr->multi_serdes_id[0] <= 47))
    {
        *tb_index = 1;
    }
    else if ((port_attr->multi_serdes_id[0] >= 80)
        && (port_attr->multi_serdes_id[0] <= 87))
    {
        *tb_index = 2;
    }
    else if ((port_attr->multi_serdes_id[0] >= 88)
        && (port_attr->multi_serdes_id[0] <= 95))
    {
        *tb_index = 3;
    }
    else
    {
        return CTC_E_INVALID_CONFIG;
    }

    switch (port_attr->pcs_mode)
    {
    case CTC_CHIP_SERDES_LG_R1_MODE:
        lane_num = 1;
        break;
    case CTC_CHIP_SERDES_LG_MODE:
    case CTC_CHIP_SERDES_CG_R2_MODE:
        lane_num = 2;
        break;
    case CTC_CHIP_SERDES_CG_MODE:
    case CTC_CHIP_SERDES_CCG_R4_MODE:
        lane_num = 4;
        break;
    case CTC_CHIP_SERDES_CDG_R8_MODE:
        lane_num = 8;
        break;
    default:
        return CTC_E_INVALID_CONFIG;
    }

    for (i = 0; i < lane_num; i++)
    {
        pcs_l_id = port_attr->pcs_idx + i;
        if (pcs_l_id < 7)  /* 0~6 */
        {
            value[2] |= 0x3 << (17 + 2*pcs_l_id);
        }
        else
        {
            value[2] |= (1 << 31);
            value[3] |= 1;
        }
    }
    
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_link_intr(uint8 lchip, uint16 lport, uint32 enable)
{
    uint32 cmd         = 0;
    uint32 tb_id       = 0;
    uint32 tb_index    = 0;
    uint32 value[5]    = {0};
    uint32 index       = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }

    if(SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_intr_get_flexe_table_bitmap(lchip, port_attr, &tb_id, &tb_index, value));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_intr_get_table_bitmap(lchip, port_attr->mac_id, &tb_id, &tb_index, value));
    }

    if(enable)
    {
        /*clear link intr*/
        index = DRV_INS(tb_index, 1);
        cmd = DRV_IOW(tb_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, value));
        index = DRV_INS(tb_index, 3);
    }
    else
    {
        index = DRV_INS(tb_index, 2);
    }

    cmd = DRV_IOW(tb_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, value));
    
    p_usw_mac_master[lchip]->mac_prop[lport].link_intr_en = (enable)?1:0;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_link_intr(uint8 lchip, uint16 lport, uint32 enable)
{

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_link_intr(lchip, lport, enable));
    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_link_intr(uint8 lchip, uint16 lport, uint32* enable)
{
    uint32 cmd         = 0;
    uint32 tb_id       = 0;
    uint32 tb_index    = 0;
    uint32 value[5]    = {0};
    uint32 tb_value[5] = {0};
    uint32 index       = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_PORT;
    }

    if (SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% FlexE PHY port DONOT support mac interrupt \n");
        return CTC_E_INVALID_PORT;
    }

    CTC_ERROR_RETURN(_sys_tmm_mac_intr_get_table_bitmap(lchip, port_attr->mac_id, &tb_id, &tb_index, value));        

    index = DRV_INS(tb_index, 2);
    cmd = DRV_IOR(tb_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, tb_value));

    if(CTC_FLAG_ISSET(tb_value[0], value[0])
        && CTC_FLAG_ISSET(tb_value[1], value[1])
        && CTC_FLAG_ISSET(tb_value[2], value[2]))
    {
        *enable = 0;
    }
    else
    {
        *enable = 1;
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_link_intr(uint8 lchip, uint16 lport, uint32* enable)
{

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_intr(lchip, lport, enable));
    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_cl73_autoneg_ability(uint8 lchip, uint16 lport, uint32 type, sys_datapath_an_ability_t* p_ability)
{
    sys_datapath_lport_attr_t* port_attr = NULL;
    uint8 cnt = 0;
    sys_datapath_an_ability_t serdes_ability[8];

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d\n", lport);

    /* 1. get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }
    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num, CTC_E_INVALID_PARAM);

    /* if auto_neg_ok, should get ability */
    if (type)
    {
        for(cnt = 0; cnt < port_attr->serdes_num; cnt++)
        {
            CTC_ERROR_RETURN(sys_tmm_serdes_get_serdes_auto_neg_remote_ability(lchip, port_attr->multi_serdes_id[cnt], &(serdes_ability[cnt])));
        }
    }
    else
    {
        for(cnt = 0; cnt < port_attr->serdes_num; cnt++)
        {
            CTC_ERROR_RETURN(sys_tmm_serdes_get_serdes_auto_neg_local_ability(lchip, port_attr->multi_serdes_id[cnt], &(serdes_ability[cnt])));
        }
    }
    sal_memset(p_ability, 0, sizeof(sys_datapath_an_ability_t));
    for(cnt = 0; cnt < port_attr->serdes_num; cnt++)
    {
        p_ability->base_ability0 |= serdes_ability[cnt].base_ability0;
        p_ability->base_ability1 |= serdes_ability[cnt].base_ability1;
        p_ability->np0_ability0 |= serdes_ability[cnt].np0_ability0;
        p_ability->np0_ability1 |= serdes_ability[cnt].np0_ability1;
        p_ability->np1_ability0 |= serdes_ability[cnt].np1_ability0;
        p_ability->np1_ability1 |= serdes_ability[cnt].np1_ability1;
    }

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,
        "port %s base ability[0]:0x%x,[1] :0x%x, next page0[0]:0x%x,[1]:0x%x, next page1[0]:0x%x,[1]:0x%x\n",
        type?"remote":"local", p_ability->base_ability0, p_ability->base_ability1, p_ability->np0_ability0,
        p_ability->np0_ability1, p_ability->np1_ability0, p_ability->np1_ability1);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_cl73_ability(uint8 lchip, uint16 lport, uint32 type, uint32* p_ability)
{
    sys_datapath_an_ability_t cl73_ability;

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(_sys_tmm_mac_get_cl73_autoneg_ability(lchip, lport, type, &cl73_ability));
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_10GBASE_KR)
    {
        *p_ability |= (CTC_PORT_CL73_10GBASE_KR);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_40GBASE_KR4)
    {
        *p_ability |= (CTC_PORT_CL73_40GBASE_KR4);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_40GBASE_CR4)
    {
        *p_ability |= (CTC_PORT_CL73_40GBASE_CR4);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_100GBASE_KR4)
    {
        *p_ability |= (CTC_PORT_CL73_100GBASE_KR4);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_100GBASE_CR4)
    {
        *p_ability |= (CTC_PORT_CL73_100GBASE_CR4);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_25GBASE_KR_S)
    {
        *p_ability |= (CTC_PORT_CL73_25GBASE_KRS);
    }
    if(cl73_ability.base_ability0 & SYS_PORT_CL73_25GBASE_KR)
    {
        *p_ability |= (CTC_PORT_CL73_25GBASE_KR);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_50GBASE_KR)
    {
        *p_ability |= (CTC_PORT_CL73_50GBASE_KR);
        *p_ability |= (CTC_PORT_CL73_50GBASE_CR);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_100GBASE_KR2)
    {
        *p_ability |= (CTC_PORT_CL73_100GBASE_KR2);
        *p_ability |= (CTC_PORT_CL73_100GBASE_CR2);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_200GBASE_KR4)
    {
        *p_ability |= (CTC_PORT_CL73_200GBASE_KR4);
        *p_ability |= (CTC_PORT_CL73_200GBASE_CR4);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_25G_RS_FEC_REQ)
    {
        *p_ability |= (CTC_PORT_CL73_25G_RS_FEC_REQUESTED);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_25G_BASER_FEC_REQ)
    {
        *p_ability |= (CTC_PORT_CL73_25G_BASER_FEC_REQUESTED);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_FEC_SUP)
    {
        *p_ability |= (CTC_PORT_CL73_FEC_ABILITY);
    }
    if(cl73_ability.base_ability1 & SYS_PORT_CL73_FEC_REQ)
    {
        *p_ability |= (CTC_PORT_CL73_FEC_REQUESTED);
    }
    if(cl73_ability.np1_ability0 & SYS_PORT_CSTM_25GBASE_KR1)
    {
        *p_ability |= (CTC_PORT_CSTM_25GBASE_KR1);
    }
    if(cl73_ability.np1_ability0 & SYS_PORT_CSTM_25GBASE_CR1)
    {
        *p_ability |= (CTC_PORT_CSTM_25GBASE_CR1);
    }
    if(cl73_ability.np1_ability0 & SYS_PORT_CSTM_50GBASE_KR2)
    {
        *p_ability |= (CTC_PORT_CSTM_50GBASE_KR2);
    }
    if(cl73_ability.np1_ability0 & SYS_PORT_CSTM_50GBASE_CR2)
    {
        *p_ability |= (CTC_PORT_CSTM_50GBASE_CR2);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_400GBASE_CR8)
    {
        *p_ability |= (CTC_PORT_CSTM_400GBASE_CR8);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_CL91_FEC_SUP)
    {
        *p_ability |= (CTC_PORT_CSTM_RS_FEC_ABILITY);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_CL74_FEC_SUP)
    {
        *p_ability |= (CTC_PORT_CSTM_BASER_FEC_ABILITY);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_CL91_FEC_REQ)
    {
        *p_ability |= (CTC_PORT_CSTM_RS_FEC_REQUESTED);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_CL74_FEC_REQ)
    {
        *p_ability |= (CTC_PORT_CSTM_BASER_FEC_REQUESTED);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_LF1_50GR1)
    {
        *p_ability |= (CTC_PORT_CSTM_LF1_50GR1);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_LF2_100GR2)
    {
        *p_ability |= (CTC_PORT_CSTM_LF2_100GR2);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_LF3_200GR4)
    {
        *p_ability |= (CTC_PORT_CSTM_LF3_200GR4);
    }
    if(cl73_ability.np1_ability1 & SYS_PORT_CSTM_LL_RS_FEC_REQ)
    {
        *p_ability |= (CTC_PORT_CSTM_LL_RS_FEC_REQ);
    }
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_serdes_info_capability(uint8 lchip, uint16 lport, ctc_port_serdes_info_t* p_value)
{
    uint8 cnt   = 0;
    uint8 logic_serdes_id = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    sys_datapath_serdes_info_t* p_serdes  = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d\n", lport);

    /* 1. get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num, CTC_E_INVALID_PARAM);
    p_value->serdes_mode = port_attr->pcs_mode;
    p_value->serdes_num = port_attr->serdes_num;
    p_value->serdes_id = port_attr->multi_serdes_id[0];

    for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
    {
        p_value->serdes_id_array[cnt] = port_attr->multi_serdes_id[cnt];
    }

    CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, port_attr->multi_serdes_id[0], &logic_serdes_id));
    CTC_ERROR_RETURN(sys_usw_datapath_get_serdes_info(lchip, logic_serdes_id, &p_serdes));
    p_value->overclocking_speed = p_serdes->overclocking_speed;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_cl37_flowctl_ability_local(uint8 lchip, uint16 lport, uint32* value)
{
    uint32 val_32     = 0;
    uint32 cmd        = 0;
    uint32 tbl_id     = 0;
    uint32 fld_id     = 0;
    uint16 step       = 0;
    uint32 factor     = 0;
    uint32 index      = 0;
    uint32 is_pcs_x16 = 0;  
    uint32 pcs_x8_x16_index = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    SharedPcsSgmii0Cfg_m   cpumac_cfg;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN((NULL == port_attr), CTC_E_INVALID_PTR);

    if((CTC_CHIP_SERDES_SGMII_MODE != port_attr->pcs_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != port_attr->pcs_mode))
    {
        *value = 0;
        return CTC_E_NONE;
    }

    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
        index = DRV_INS(pcs_x8_x16_index, 0);
        factor = port_attr->pcs_idx;

        if (1==is_pcs_x16)
        {
            tbl_id = McPcsX16LanesSgmiiCfg_t;
            step   = McPcsX16LanesSgmiiCfg_cfgSgmii_1_localPauseAbility_f-McPcsX16LanesSgmiiCfg_cfgSgmii_0_localPauseAbility_f;
            fld_id = McPcsX16LanesSgmiiCfg_cfgSgmii_0_localPauseAbility_f+step*factor;
        }
        else
        {
            tbl_id = McPcsX8LanesSgmiiCfg_t;
            step   = McPcsX8LanesSgmiiCfg_cfgSgmii_1_localPauseAbility_f-McPcsX8LanesSgmiiCfg_cfgSgmii_0_localPauseAbility_f;
            fld_id = McPcsX8LanesSgmiiCfg_cfgSgmii_0_localPauseAbility_f+step*factor;
        }
        cmd = DRV_IOR(tbl_id, fld_id);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &val_32));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        step   = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
        tbl_id = SharedPcsSgmii0Cfg_t + port_attr->pcs_idx*step;
        index  = 0;
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_cfg));
        DRV_IOR_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_localPauseAbility0_f, &val_32, &cpumac_cfg);
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PARAM;
    }

    switch(val_32)
    {
        case SYS_ASMDIR_0_PAUSE_0:
            val_32 = ((!CTC_PORT_PAUSE_ABILITY_TX_EN) & (!CTC_PORT_PAUSE_ABILITY_RX_EN));
            break;
        case SYS_ASMDIR_0_PAUSE_1:
            val_32 = (CTC_PORT_PAUSE_ABILITY_TX_EN | CTC_PORT_PAUSE_ABILITY_RX_EN);
            break;
        case SYS_ASMDIR_1_PAUSE_0:
            val_32 = CTC_PORT_PAUSE_ABILITY_TX_EN;
            break;
        case SYS_ASMDIR_1_PAUSE_1:
        default:
            val_32 = CTC_PORT_PAUSE_ABILITY_RX_EN;
            break;
    }

    *value = val_32;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_cl37_flowctl_ability_remote(uint8 lchip, uint16 lport, uint32* value)
{
    uint32 val_32 = 0;
    uint32 cmd        = 0;
    uint32 mask       = 0x3;
    uint32 tbl_id     = 0;
    uint32 fld_id     = 0;
    uint16 step       = 0;
    uint32 factor     = 0;
    uint32 index      = 0;
    uint32 is_pcs_x16 = 0;  
    uint32 pcs_x8_x16_index = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    SharedPcsSgmii0Status_m   sgmii_stat;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN((NULL == port_attr), CTC_E_INVALID_PTR);

    if((CTC_CHIP_SERDES_SGMII_MODE != port_attr->pcs_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != port_attr->pcs_mode))
    {
        *value = 0;
        return CTC_E_NONE;
    }

    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
        index = DRV_INS(pcs_x8_x16_index, 0);
        factor = port_attr->pcs_idx;

        if (1==is_pcs_x16)
        {
            tbl_id = McPcsX16LanesSgmiiMon_t;
            step   = McPcsX16LanesSgmiiMon_monSgmii_1_anRxRemoteCfg_f-McPcsX16LanesSgmiiMon_monSgmii_0_anRxRemoteCfg_f;
            fld_id = McPcsX16LanesSgmiiMon_monSgmii_0_anRxRemoteCfg_f+step*factor;
        }
        else
        {
            tbl_id = McPcsX8LanesSgmiiMon_t;
            step   = McPcsX8LanesSgmiiMon_monSgmii_1_anRxRemoteCfg_f-McPcsX8LanesSgmiiMon_monSgmii_0_anRxRemoteCfg_f;
            fld_id = McPcsX8LanesSgmiiMon_monSgmii_0_anRxRemoteCfg_f+step*factor;
        }
        cmd = DRV_IOR(tbl_id, fld_id);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &val_32));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        step   = SharedPcsSgmii1Status_t - SharedPcsSgmii0Status_t;
        tbl_id = SharedPcsSgmii0Status_t + port_attr->pcs_idx*step;
        index  = 0;
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_stat));
        DRV_IOR_FIELD(lchip, tbl_id, SharedPcsSgmii0Status_anRxRemoteCfg0_f, &val_32, &sgmii_stat);
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PARAM;
    }

    /*bit[8:7]*/
    val_32 = (val_32 >> 7) & mask;

    switch(val_32)
    {
        case SYS_ASMDIR_0_PAUSE_0:
            val_32 = ((!CTC_PORT_PAUSE_ABILITY_TX_EN) & (!CTC_PORT_PAUSE_ABILITY_RX_EN));
            break;
        case SYS_ASMDIR_0_PAUSE_1:
            val_32 = (CTC_PORT_PAUSE_ABILITY_TX_EN | CTC_PORT_PAUSE_ABILITY_RX_EN);
            break;
        case SYS_ASMDIR_1_PAUSE_0:
            val_32 = CTC_PORT_PAUSE_ABILITY_TX_EN;
            break;
        case SYS_ASMDIR_1_PAUSE_1:
        default:
            val_32 = CTC_PORT_PAUSE_ABILITY_RX_EN;
            break;
    }

    *value = val_32;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_cl37_flowctl_ability(uint8 lchip, uint16 lport, uint32 value)
{
    uint32 val_32 = value;
    uint32 cmd        = 0;
    uint32 tbl_id     = 0;
    uint32 fld_id     = 0;
    uint16 step       = 0;
    uint32 factor     = 0;
    uint32 index      = 0;
    uint32 is_pcs_x16 = 0;  
    uint32 pcs_x8_x16_index = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    SharedPcsSgmii0Cfg_m   cpumac_cfg;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN((NULL == port_attr), CTC_E_INVALID_PTR);

    if((CTC_CHIP_SERDES_SGMII_MODE != port_attr->pcs_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != port_attr->pcs_mode))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Port mode %u is not supported! \n", port_attr->pcs_mode);
        return CTC_E_INVALID_PARAM;
    }
    if(3 < val_32)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid value %u! \n", val_32);
        return CTC_E_INVALID_PARAM;
    }

    switch(val_32)
    {
        case ((!CTC_PORT_PAUSE_ABILITY_TX_EN) & (!CTC_PORT_PAUSE_ABILITY_RX_EN)):
            val_32 = SYS_ASMDIR_0_PAUSE_0;
            break;
        case CTC_PORT_PAUSE_ABILITY_TX_EN:
            val_32 = SYS_ASMDIR_1_PAUSE_0;
            break;
        case CTC_PORT_PAUSE_ABILITY_RX_EN:
            val_32 = SYS_ASMDIR_1_PAUSE_1;
            break;
        case (CTC_PORT_PAUSE_ABILITY_TX_EN | CTC_PORT_PAUSE_ABILITY_RX_EN):
        default:
            val_32 = SYS_ASMDIR_0_PAUSE_1;
            break;
    }

    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
        index = DRV_INS(pcs_x8_x16_index, 0);
        factor = port_attr->pcs_idx;

        if (1==is_pcs_x16)
        {
            tbl_id = McPcsX16LanesSgmiiCfg_t;
            step   = McPcsX16LanesSgmiiCfg_cfgSgmii_1_localPauseAbility_f-McPcsX16LanesSgmiiCfg_cfgSgmii_0_localPauseAbility_f;
            fld_id = McPcsX16LanesSgmiiCfg_cfgSgmii_0_localPauseAbility_f+step*factor;
        }
        else
        {
            tbl_id = McPcsX8LanesSgmiiCfg_t;
            step   = McPcsX8LanesSgmiiCfg_cfgSgmii_1_localPauseAbility_f-McPcsX8LanesSgmiiCfg_cfgSgmii_0_localPauseAbility_f;
            fld_id = McPcsX8LanesSgmiiCfg_cfgSgmii_0_localPauseAbility_f+step*factor;
        }
        cmd = DRV_IOW(tbl_id, fld_id);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &val_32));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        step   = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
        tbl_id = SharedPcsSgmii0Cfg_t + port_attr->pcs_idx*step;
        index  = 0;
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_cfg));
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_localPauseAbility0_f, &val_32, &cpumac_cfg);
        cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_cfg));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_auto_neg(uint8 lchip, uint16 lport, uint32 type, uint32* p_value)
{
    uint32 value     = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_INIT_CHECK();

    SYS_USW_VALID_PTR_WRITE(p_value, 0);

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }

    if(SYS_MAC_IS_MODE_SUPPORT_CL37(port_attr->pcs_mode))
    {
        if(CTC_PORT_PROP_AUTO_NEG_EN == type)
        {
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_cl37_en(lchip, lport, &value));
        }
        else if(CTC_PORT_PROP_AUTO_NEG_MODE == type)
        {
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_cl37_mode(lchip, lport, &value));
        }
        else
        {
            MAC_UNLOCK;
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% auto-neg type %d not supported\n", type);
            return CTC_E_INVALID_PARAM;
        }
    }
    else
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_usw_mac_get_cl73_auto_neg(lchip, lport, type, &value));
    }

    SYS_USW_VALID_PTR_WRITE(p_value, value);
    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_capability(uint8 lchip, uint16 lport, ctc_port_capability_type_t type, void* p_value)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get port capability, lport:%u, type:%d!\n", lport, type);

    SYS_MAC_INIT_CHECK();
    CTC_PTR_VALID_CHECK(p_value);
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        MAC_UNLOCK;
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PARAM;
    }

    switch (type)
    {
        case CTC_PORT_CAP_TYPE_SERDES_INFO:
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_serdes_info_capability(lchip, lport, (ctc_port_serdes_info_t*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_MAC_ID:
            /*same as usw*/
            *(uint32*)p_value = port_attr->mac_id;
            break;
        case CTC_PORT_CAP_TYPE_SPEED_MODE:
            /*same as usw*/
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_usw_mac_get_speed_mode_capability(lchip, lport, (uint32*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_IF_TYPE:
            /*same as usw*/
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_usw_mac_get_if_type_capability(lchip, lport, (uint32*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_FEC_TYPE:
            _sys_tmm_mac_get_fec_type_capability(port_attr->pcs_mode, (uint32*)p_value);
            break;
        case CTC_PORT_CAP_TYPE_CL73_ABILITY:
            _sys_tmm_mac_get_cl73_capability(lchip, lport, (uint32*)p_value);
            break;
        case CTC_PORT_CAP_TYPE_CL73_REMOTE_ABILITY:
            /*same as usw*/
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_cl73_ability(lchip, lport, 1, (uint32*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_LOCAL_PAUSE_ABILITY:
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_get_cl37_flowctl_ability_local(lchip, lport, (uint32*)p_value));
            break;
        case CTC_PORT_CAP_TYPE_REMOTE_PAUSE_ABILITY:
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_get_cl37_flowctl_ability_remote(lchip, lport, (uint32*)p_value));
            break;
        default:
            MAC_UNLOCK;
            return CTC_E_INVALID_PARAM;
    }

    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_capability(uint8 lchip, uint16 lport, ctc_port_capability_type_t type, uint32 value)
{

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port capability, lport:%u, type:%d value:0x%x!\n", lport, type, value);

    SYS_MAC_INIT_CHECK();
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;

    switch (type)
    {
        case CTC_PORT_CAP_TYPE_LOCAL_PAUSE_ABILITY:
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_set_cl37_flowctl_ability(lchip, lport, value));
            break;
        default:
            MAC_UNLOCK;
            return CTC_E_INVALID_PARAM;
    }

    MAC_UNLOCK;

    return CTC_E_NONE;
}

#define  __TMM_MAC_CONFIG__



int32
_sys_tmm_macpcs_get_offset(uint8 lchip, uint32 offset_type, sys_datapath_lport_attr_t* port_attr, 
                                    uint32* p_offset_num, uint32* p_offset)
{
    uint32 offset_num = 0;
    uint32 i;
    uint32 pcs_lane_num = 0;
    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num, CTC_E_INVALID_PARAM);
    pcs_lane_num = SYS_TMM_GET_PCS_LANE_NUM(port_attr->txqm_id);

    switch(offset_type)
    {
        case OFFSET_TYPE_TXQM_MAC_ID:
            offset_num = 1;
            p_offset[0] = TXQM_INNER_MAC_ID(port_attr->mac_id);
            break;
        case OFFSET_TYPE_PCS_ID:
            offset_num = 1;
            p_offset[0] = port_attr->pcs_idx % pcs_lane_num;
            break;
        case OFFSET_TYPE_LOGICAL_LANE_ID:
            offset_num = port_attr->serdes_num;
            for(i = 0; i < offset_num; i++)
            {
                p_offset[i] = port_attr->pcs_idx % pcs_lane_num + i;
            }
            break;
        case OFFSET_TYPE_PHYSICAL_LANE_ID:
            offset_num = port_attr->serdes_num;
            for(i = 0; i < offset_num; i++)
            {
                p_offset[i] = port_attr->multi_serdes_id[i] % pcs_lane_num;
            }
            break;
        case OFFSET_TYPE_LOGICAL_LANE_ID_X16AB:
            offset_num = port_attr->serdes_num;
            for(i = 0; i < offset_num; i++)
            {
                p_offset[i] = port_attr->pcs_idx % (SYS_TMM_PCS_X16_LANE_NUM/2) + i;
            }
            break;
        case OFFSET_TYPE_PHYSIC_LANE_ID_X16AB:
            offset_num = port_attr->serdes_num;
            for(i = 0; i < offset_num; i++)
            {
                p_offset[i] = port_attr->multi_serdes_id[i] % (SYS_TMM_PCS_X16_LANE_NUM/2);
            }
            break;
        case OFFSET_TYPE_1:
        default:
            offset_num = 1;
            p_offset[0] = 1;
            break;
    }
    SYS_USW_VALID_PTR_WRITE(p_offset_num, offset_num);
    return CTC_E_NONE;
}

/*
Note: For 500M, both pam4 and nrz mode using low freq config; for 800M, pam4 mode using low freq config
and nrz mode using normal 1050M config.
*/
int32
_sys_tmm_macpcs_get_value(uint8 lchip, uint32 value_type, uint32 value_num, uint32 value_base, 
                                  sys_datapath_lport_attr_t* port_attr, uint32* p_value, 
                                  uint32 item, ctc_chip_serdes_mode_t mode, uint8 mac_or_pcs, uint32 mode_fec)
{
    uint32 i;
    uint32 pcs_lane_num = 0;
    uint32 value_base_fix = value_base;
    uint8  logic_serdes   = 0;
    sys_datapath_serdes_info_t* p_serdes = NULL;
    uint8  speed_mode_col = 0; //speed_mode_val column 0~2
    uint8  speed_mode_row = 0; //speed_mode_val row 0~3
    uint32 speed_mode_val[4][3] = {/*10M  100M 1G*/
                                    {0,   1,   2}, /*McMac_cfgMcMacTxSpeed*/
                                    {99,  9,   0}, /*McMac_cfgMiiRxSampleCnt*/
                                    {99,  9,   0}, /*McMac_cfgMcMacTxReplicateCnt*/
                                    {0,   1,   2}};/*McPcs_cfgRxSpeed*/
    uint32 mac_crdt_500[] = 
   /*N  XFI SGMII N  QSGMII N  N  XLG CG  2.5G N  N  N  XXVG LG  N  LGR1 CGR2 CCGR4 CDGR8*/
    {0, 20, 64,   0, 64,    0, 0, 54, 96, 64,  0, 0, 0, 32,  54, 0, 36,  64,  120,  192  }; /*9 McMac_cfgTxCreditThrd*/    
    uint32 pcs_aful_500[] = 
   /*N  XFI SGMII N  QSGMII N  N  XLG CG  2.5G N  N  N  XXVG LG  N  LGR1 CGR2 CCGR4 CDGR8*/
    {0, 4,  4,    0, 4,     0, 0, 4,  7,  4,   0, 0, 0, 5,   6,  0, 7,   7,   5,    4    }; /*20 McPcs_cfgTxFifoAFullThrd*/   
    uint32 mac_crdt_800[] = 
   /*N  XFI SGMII N  QSGMII N  N  XLG CG  2.5G N  N  N  XXVG LG  N  LGR1 CGR2 CCGR4 CDGR8*/
    {0, 24, 64,   0, 64,    0, 0, 54, 64, 64,  0, 0, 0, 24,  54, 0, 36,  64,  120,  192  }; /*9 McMac_cfgTxCreditThrd*/    
    uint32 pcs_aful_800[] = 
   /*N  XFI SGMII N  QSGMII N  N  XLG CG  2.5G N  N  N  XXVG LG  N  LGR1 CGR2 CCGR4 CDGR8*/
    {0, 4,  4,    0, 4,     0, 0, 4,  4,  4,   0, 0, 0, 4,   4,  0, 7,   7,   5,    4    }; /*20 McPcs_cfgTxFifoAFullThrd*/  
    
    uint32 mac_crdt_fec_500[] = 
   /*XFI_FC2112,  XXVG_FC2112, XXVG_RS528,  XLG_FC2112,  LG_R2_RS528, LG_R2_RS544,  LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272, 
    CG_R4_RS528, CG_R4_RS544, CG_R2_RS528, CG_R2_RS544, CG_R2_RS272, CCG_R4_RS544, CCG_R4_RS272, CDG_R8_RS544, CDG_R8_RS272*/
    {20,          24,          34,          54,          64,          64,           36,           36,           36,         
    96,          96,          64,          64,          64,          120,          120,          192,          192  }; /*9 McMac_cfgTxCreditThrd*/      
    uint32 pcs_aful_fec_500[] = 
   /*XFI_FC2112,  XXVG_FC2112, XXVG_RS528,  XLG_FC2112,  LG_R2_RS528, LG_R2_RS544,  LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272, 
    CG_R4_RS528, CG_R4_RS544, CG_R2_RS528, CG_R2_RS544, CG_R2_RS272, CCG_R4_RS544, CCG_R4_RS272, CDG_R8_RS544, CDG_R8_RS272*/
    {4,           5,           4,           4,           5,           5,            7,            7,            7,           
    6,           5,           7,           7,           7,           5,            5,            4,            4    }; /*20 McPcs_cfgTxFifoAFullThrd*/
    uint32 mac_crdt_fec_800[] = 
   /*XFI_FC2112,  XXVG_FC2112, XXVG_RS528,  XLG_FC2112,  LG_R2_RS528, LG_R2_RS544,  LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272, 
    CG_R4_RS528, CG_R4_RS544, CG_R2_RS528, CG_R2_RS544, CG_R2_RS272, CCG_R4_RS544, CCG_R4_RS272, CDG_R8_RS544, CDG_R8_RS272*/
    {16,          24,          24,          54,          54,          54,           36,           36,           36,         
    64,          64,          64,          64,          64,          120,          120,          192,          192  }; /*9 McMac_cfgTxCreditThrd*/      
    uint32 pcs_aful_fec_800[] = 
   /*XFI_FC2112,  XXVG_FC2112, XXVG_RS528,  XLG_FC2112,  LG_R2_RS528, LG_R2_RS544,  LG_R1_RS528,  LG_R1_RS544,  LG_R1_RS272, 
    CG_R4_RS528, CG_R4_RS544, CG_R2_RS528, CG_R2_RS544, CG_R2_RS272, CCG_R4_RS544, CCG_R4_RS272, CDG_R8_RS544, CDG_R8_RS272*/
    {4,           5,           4,           4,           4,           4,            7,            7,            7,           
    4,           4,           7,           7,           7,           5,            5,            4,            4    }; /*20 McPcs_cfgTxFifoAFullThrd*/

    pcs_lane_num = SYS_TMM_GET_PCS_LANE_NUM(port_attr->txqm_id);

    /*special operation for low core clock*/
    if(500 >= p_usw_datapath_master[lchip]->core_plla)
    {
        if(MAC == mac_or_pcs)
        {
            if(McMac_cfgTxCreditThrd == item)
            {
                value_base_fix = (MAX_MODE_FEC <= mode_fec) ? mac_crdt_500[mode] : mac_crdt_fec_500[mode_fec];
            }
        }
        else
        {
            if(McPcs_cfgTxFifoAFullThrd == item)
            {
                value_base_fix = (MAX_MODE_FEC <= mode_fec) ? pcs_aful_500[mode] : pcs_aful_fec_500[mode_fec];
            }
        }
    }
    else if(800 >= p_usw_datapath_master[lchip]->core_plla)
    {
        if(MAC == mac_or_pcs)
        {
            if(McMac_cfgTxCreditThrd == item)
            {
                value_base_fix = (MAX_MODE_FEC <= mode_fec) ? mac_crdt_800[mode] : mac_crdt_fec_800[mode_fec];
            }
        }
        else
        {
            if(McPcs_cfgTxFifoAFullThrd == item)
            {
                value_base_fix = (MAX_MODE_FEC <= mode_fec) ? pcs_aful_800[mode] : pcs_aful_fec_800[mode_fec];
            }
        }
    }

    /*special operation for 10M/100M/1000M*/
    if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode))
    {
        if(MAC == mac_or_pcs)
        {
            switch(item)
            {
                case McMac_cfgMcMacTxSpeed:
                    speed_mode_row = 0;
                    break;
                case McMac_cfgMiiRxSampleCnt:
                    speed_mode_row = 1;
                    break;
                case McMac_cfgMcMacTxReplicateCnt:
                    speed_mode_row = 2;
                    break;
                default:
                    speed_mode_row = SYS_TMM_USELESS_ID8;
                    break;
            }
        }
        else
        {
            if(McPcs_cfgRxSpeed == item)
            {
                speed_mode_row = 3;
            }
            else
            {
                speed_mode_row = SYS_TMM_USELESS_ID8;
            }
        }

        if(4 > speed_mode_row)
        {
            switch(port_attr->speed_mode)
            {
                case CTC_PORT_SPEED_10M:
                    speed_mode_col = 0;
                    break;
                case CTC_PORT_SPEED_100M:
                    speed_mode_col = 1;
                    break;
                case CTC_PORT_SPEED_1G:
                default:
                    speed_mode_col = 2;
                    break;
            }
            value_base_fix = speed_mode_val[speed_mode_row][speed_mode_col];
        }
    }

    /*special operation for 56.25G TxFifoAFullThrd (keep in 6)*/
    if((MAC != mac_or_pcs) && (McPcs_cfgTxFifoAFullThrd == item))
    {
        CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, port_attr->multi_serdes_id[0], &logic_serdes));
        CTC_ERROR_RETURN(sys_usw_datapath_get_serdes_info(lchip, logic_serdes, &p_serdes));
        if(CTC_CHIP_SERDES_OCS_MODE_52_94G == p_serdes->overclocking_speed)
        {
            value_base_fix = 6;
        }
    }

    /*special operation for TMM 1.0 sgmii*/
    if((MAC == mac_or_pcs) && (McMac_cfgMcMacRxUseHataTsEn == item) && 
       ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode)) &&
       (SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_A))
    {
        value_base_fix = 0;
    }

    if((MAC == mac_or_pcs) && (McMac_cfgMcMacMacTxWaitCaptureTs == item) && 
       ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode) ||
       (XFI_FC2112 == mode_fec) || (XXVG_FC2112 == mode_fec) || (XLG_FC2112 == mode_fec)))
    {
        value_base_fix = 0;
    }

    if((MAC == mac_or_pcs) && (McMac_cfgTxCreditThrd == item) && 
       ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode)))
    {
        value_base_fix = 0x30;
    }

    switch(value_type)
    {
        case VALUE_TYPE_PCS_ID:
            for(i = 0; i < value_num; i++)
            {
                p_value[i] = port_attr->pcs_idx % pcs_lane_num;
            }
            break;
        case VALUE_TYPE_LOGICAL_LANE_ID:
            for(i = 0; i < value_num; i++)
            {
                p_value[i] = port_attr->pcs_idx % pcs_lane_num + i;
            }
            break;
        case VALUE_TYPE_PCS_L_ID:
            for(i = 0; i < value_num; i++)
            {
                p_value[i] = i;
            }
            break;
        case VALUE_TYPE_TXQM_INNER_MAC_ID:
            for(i = 0; i < value_num; i++)
            {
                p_value[i] = TXQM_INNER_MAC_ID(port_attr->mac_id);
            }
            break;
        case VALUE_TYPE_PCSX_BASED_1:
            for(i = 0; i < value_num; i++)
            {
                if(!SYS_TMM_IS_PCS_X16(port_attr->txqm_id))
                {
                    p_value[i] = 1;
                }
                else
                {
                    p_value[i] = 0;
                }
            }
            break;
        case VALUE_TYPE_MAC_ID_BMP:
        case VALUE_TYPE_NORMAL:
        case VALUE_TYPE_PCS_ID_BMP:
        default:
            for(i = 0; i < value_num; i++)
            {
                p_value[i] = value_base_fix;
            }
            break;
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_macpcs_get_ins_index(uint8 lchip, uint32 idx_type, sys_datapath_lport_attr_t* port_attr, 
                                        uint32* p_ins, uint32* p_entry, uint32* p_index)
{
    uint32 ins              = 0;
    uint32 entry            = 0;
    uint32 index            = 0;
    uint32 pcs_x8_x16_index = 0;
    uint32 pcs_lane_num     = 0;

    pcs_lane_num = SYS_TMM_GET_PCS_LANE_NUM(port_attr->txqm_id);
    SYS_TMM_GET_PCSXIDX(port_attr->txqm_id, pcs_x8_x16_index);

    switch(idx_type)
    {
        case INDEX_TYPE_TXQMID_0:
            ins   = port_attr->txqm_id;
            entry = 0;
            break;
        case INDEX_TYPE_TXQMID_MACID:
            ins   = port_attr->txqm_id;
            entry = port_attr->mac_id % 40;
            break;
        case INDEX_TYPE_TXQMID_PCSID:
            ins   = port_attr->txqm_id;
            entry = port_attr->pcs_idx % pcs_lane_num;
            break;
        case INDEX_TYPE_PCSXIDX_0:
            ins   = pcs_x8_x16_index;
            entry = 0;
            break;
        case INDEX_TYPE_PCSXIDX_PCSID:
            ins   = pcs_x8_x16_index;
            entry = port_attr->pcs_idx % pcs_lane_num;
            break;
        case INDEX_TYPE_0_0:
        default:
            break;
    }
    index = DRV_INS(ins, entry);
    
    SYS_USW_VALID_PTR_WRITE(p_ins,   ins);
    SYS_USW_VALID_PTR_WRITE(p_entry, entry);
    SYS_USW_VALID_PTR_WRITE(p_index, index);
    
    return CTC_E_NONE;
}

int32
_sys_tmm_macpcs_get_cfg_flag(uint8 lchip, uint8 cfg_prop_type, uint32 item, uint8 mac_or_pcs, 
                                      sys_datapath_lport_attr_t* port_attr, uint32* p_cfg_flag)
{
    uint8  idx;
    uint32 mac_item_remap[] = {McMac_cfgTxChanIdLane};
    uint32 pcs_item_remap[] = {McPcs_cfgRxGearboxMode, 
                               McPcs_cfgRxChanId, 
                               McPcs_cfgRxLaneswapId,
                               McPcs_cfgTxChanId, 
                               McPcs_cfgTxLaneId, 
                               McPcs_cfgTxPcsMode,
                               McPcs_cfgTxGearboxMode, 
                               McPcs_cfgTxBufThrd, 
                               McPcs_cfgTxFifoAFullThrd, 
                               McPcs_cfgTxDoneMode, 
                               McPcs_cfgRxSgmiiMode};

    uint32 mac_item_speed[] = {McMac_cfgMcMacTxSpeed,
                               McMac_cfgMiiRxSampleCnt,
                               McMac_cfgMcMacTxReplicateCnt};
    uint32 pcs_item_speed[] = {McPcs_cfgRxSpeed};

    uint32* p_item_arr = NULL;
    uint8  item_num;
    uint32 cfg_flag;
    uint8  find_flag = FALSE;
    
    if(MAC == mac_or_pcs)
    {
        if(McMac_TOTAL_CNT <= item)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Invalid MAC value item %u!\n", item);
            return CTC_E_INVALID_PARAM;
        }

        switch(cfg_prop_type)
        {
            case MACPCS_CFG_REMAP:
                p_item_arr = mac_item_remap;
                item_num   = sizeof(mac_item_remap) / sizeof(uint32);
                break;
            case MACPCS_CFG_SPEED:
                p_item_arr = mac_item_speed;
                item_num   = sizeof(mac_item_speed) / sizeof(uint32);
                break;
            default:
                p_item_arr = NULL;
                item_num   = 0;
                break;
        }

        if(NULL != p_item_arr)
        {
            for(idx = 0; idx < item_num; idx++)
            {
                if(item == p_item_arr[idx])
                {
                    find_flag = TRUE;
                }
            }
            if(!find_flag)
            {
                cfg_flag = ITEM_NO_WRITE;
            }
            else
            {
                cfg_flag = g_mcmac_cfg_flag[item];
            }
        }
        else
        {
            cfg_flag = g_mcmac_cfg_flag[item];
        }
    }
    else
    {
        if(McPcs_TOTAL_CNT <= item)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Invalid PCS value item %u!\n", item);
            return CTC_E_INVALID_PARAM;
        }

        switch(cfg_prop_type)
        {
            case MACPCS_CFG_REMAP:
                p_item_arr = pcs_item_remap;
                item_num   = sizeof(pcs_item_remap) / sizeof(uint32);
                break;
            case MACPCS_CFG_SPEED:
                p_item_arr = pcs_item_speed;
                item_num   = sizeof(pcs_item_speed) / sizeof(uint32);
                break;
            default:
                p_item_arr = NULL;
                item_num   = 0;
                break;
        }

        if(NULL != p_item_arr)
        {
            for(idx = 0; idx < item_num; idx++)
            {
                if(item == p_item_arr[idx])
                {
                    find_flag = TRUE;
                }
            }
            if(!find_flag)
            {
                cfg_flag = ITEM_NO_WRITE;
            }
            else
            {
                cfg_flag = (PCS_X8 == mac_or_pcs) ? g_mcpcs_cfg_flag_x8[item] : g_mcpcs_cfg_flag_x16[item];
            }
        }
        else
        {
            cfg_flag = (PCS_X8 == mac_or_pcs) ? g_mcpcs_cfg_flag_x8[item] : g_mcpcs_cfg_flag_x16[item];
            /*qsgmii judge valid id*/
            if((McPcs_resetQsgmii_resetCore == item) || (McPcs_cfgQsgmiiSgmii_unidirectionEn == item) || 
                (McPcs_cfgQsgmiiSgmii_anEnable == item) || (McPcs_cfgQsgmiiSgmii_anegMode == item) || 
                (McPcs_cfgQsgmii_cfgTxCreditThrd == item) || (McPcs_cfgQsgmii_reAlignEachEn == item))
            {
                if(!SYS_TMM_IS_MAC_SUPPORT_QSGMII(port_attr->mac_id))
                {
                    cfg_flag = ITEM_NO_WRITE;
                }
                else
                {
                    if(((McPcs_resetQsgmii_resetCore == item) || (McPcs_cfgQsgmii_cfgTxCreditThrd == item) || 
                       (McPcs_cfgQsgmii_reAlignEachEn == item)) && (0 != port_attr->mac_id % 4))
                    {
                        cfg_flag = ITEM_NO_WRITE;
                    }
                }
            }
        }
    }

    SYS_USW_VALID_PTR_WRITE(p_cfg_flag, cfg_flag);
    
    return CTC_E_NONE;
}

int32
_sys_tmm_macpcs_get_write_on_read_value(uint8 lchip, uint16 lport, sys_mcpcs_config_list_item_t item,
                                                     uint32 value_base, uint32* p_val32)
{
    uint32 pcs_lane_num = 0;
    uint32 bmp32 = 0;
    uint32 inner_mac_id;
    sys_datapath_lport_attr_t* port_attr = NULL;
    
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    pcs_lane_num = SYS_TMM_GET_PCS_LANE_NUM(port_attr->txqm_id);
    bmp32 = ((uint32)1 << (port_attr->pcs_idx % pcs_lane_num));
    
    switch(item)
    {
        case McPcs_cfgTxChanIsPam4:
            if(1 == value_base)
            {
                p_val32[0] |= bmp32;
            }
            else
            {
                p_val32[0] &= ~bmp32;
            }
            break;
        case McMac_cfgMcMacMacTxSoftReset:
            inner_mac_id = TXQM_INNER_MAC_ID(port_attr->mac_id);
            if(inner_mac_id >= 32)
            {
                p_val32[1] &= ~(1 << (inner_mac_id - 32));
            }
            else
            {
                p_val32[0] &= ~(1 << inner_mac_id);
            }
        default:
            break;
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_fill_remap_port_attr(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr)
{
    uint8  txqm_id;
    uint8  pcs_idx;
    uint8  chan_id;
    uint8  serdes_id;
    uint8  logic_serdes_id  = SYS_TMM_USELESS_ID8;
    uint16 mac_id;

    SYS_CONDITION_RETURN(NULL == port_attr, CTC_E_INVALID_PTR);

    /*Using lport to get mac/serdes/txqm id, not port_attr, because none mode port still have mapping relationship*/
    sys_tmm_get_logic_serdes_chan_map_by_lport(lchip, lport, &chan_id, &logic_serdes_id);
    SYS_CONDITION_RETURN(logic_serdes_id >= SYS_TMM_MAX_SERDES_NUM, CTC_E_INVALID_PARAM);
    SYS_CONDITION_RETURN(CTC_E_INVALID_PARAM == _sys_usw_datapath_get_physical_serdes_id_by_logical(lchip, 
        logic_serdes_id, &serdes_id), CTC_E_INVALID_PARAM);

    mac_id = g_lane_2_pcs_mac_map[logic_serdes_id].mac_id;
    pcs_idx = g_lane_2_pcs_mac_map[logic_serdes_id].pcs_idx;
    txqm_id = SYS_TMM_GET_TXQM_BY_MACID(mac_id);

    port_attr->mac_id = mac_id;
    port_attr->pcs_idx = pcs_idx;
    port_attr->txqm_id = txqm_id;
    port_attr->chan_id = chan_id;
    port_attr->port_type = SYS_DMPS_RSV_PORT;
    port_attr->serdes_num = 1;
    port_attr->multi_serdes_id[0] = serdes_id;

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_fill_config_list_mcmac(uint8 lchip, uint16 lport, ctc_chip_serdes_mode_t mode, 
                                                ctc_port_fec_type_t fec_type, sys_macpcs_config_item_t *p_mcmac_list, 
                                                uint8 cfg_prop_type)
{
    uint32 item                          = 0;
    uint32 idx                           = 0;
    uint32 value_base                    = 0;
    uint32 mode_fec                      = MAX_MODE_FEC;
    uint32 offset_num                    = 0;
    uint32 cfg_flag                      = 0;
    uint32 offset[SYS_MAC_MAX_LANE_NUM]  = {0};
    sys_datapath_lport_attr_t* port_attr = NULL;
    sys_datapath_lport_attr_t  remap_port = {0};
    
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    /*0. check fec type invalid & get mode_with_fec value*/
    if(CTC_PORT_FEC_TYPE_NONE != fec_type)
    {
        mode_fec = g_mode_with_fec_map[mode][FEC_TYPE_NORMALIZE(fec_type)];
        if(MAX_MODE_FEC == mode_fec)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Unsupported FEC type %u, mode %u\n", fec_type, mode);
            return CTC_E_INVALID_PARAM;
        }
    }
    
    /*1. info collection*/
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);
    if(SYS_DMPS_RSV_PORT == port_attr->port_type)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_fill_remap_port_attr(lchip, lport, &remap_port));
        port_attr = &remap_port;
    }

    /*2. fill base info of mcmac config list*/
    for(item = 0; item < McMac_TOTAL_CNT; item++)
    {
        _sys_tmm_macpcs_get_cfg_flag(lchip, cfg_prop_type, item, MAC, port_attr, &cfg_flag);
        p_mcmac_list[item].cfg_flag   = cfg_flag;
        
        p_mcmac_list[item].table_id   = g_mcmac_tbl_id_base[item];
        
        _sys_tmm_macpcs_get_offset(lchip, g_mcmac_offset_type[item], port_attr, 
            &offset_num, offset);
        p_mcmac_list[item].field_id_num = offset_num;
        
        for(idx = 0; idx < offset_num; idx++)
        {
            p_mcmac_list[item].field_id[idx] = g_mcmac_fld_id_base[item] + g_mcmac_field_step[item] * offset[idx];
        }
        _sys_tmm_macpcs_get_ins_index(lchip, g_mcmac_tbl_idx_type[item], port_attr, 
            &(p_mcmac_list[item].ins), &(p_mcmac_list[item].entry), &(p_mcmac_list[item].index));
    }

    /*3. fill value of mcmac config list*/
    for(item = 0; item < McMac_TOTAL_CNT; item++)
    {
        /*get fec value or non-fec*/
        value_base = (CTC_PORT_FEC_TYPE_NONE == fec_type) ?
            g_mcmac_mode_value_map[item][mode] : g_mcmac_fec_value_map[item][mode_fec];
        _sys_tmm_macpcs_get_value(lchip, g_mcmac_value_type[item], p_mcmac_list[item].field_id_num, 
            value_base, port_attr, p_mcmac_list[item].value, 
            item, mode, MAC, mode_fec);
        /*sepcial operation for McMac_cfgTxCreditThrd*/
        if((McMac_cfgTxCreditThrd == item) && (44 == p_mcmac_list[item].value[0]) && 
           (SYS_TMM_PCS_X8_LANE_NUM == SYS_TMM_GET_PCS_LANE_NUM(port_attr->txqm_id)))
        {
            for(idx = 0; idx < p_mcmac_list[item].field_id_num; idx++)
            {
                p_mcmac_list[item].value[idx] = 48;
            }
        }
    }

    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_fill_config_list_mcpcs(uint8 lchip, uint16 lport, ctc_chip_serdes_mode_t mode, 
                                                ctc_port_fec_type_t fec_type, sys_macpcs_config_item_t *p_mcpcs_list, 
                                                uint8 cfg_prop_type)
{
    uint8   pcs_type;
    uint32  item                         = 0;
    uint32  idx                          = 0;
    uint32  value_base                   = 0;
    uint32  mode_fec                     = MAX_MODE_FEC;
    uint32  offset_num                   = 0;
    uint32  cfg_flag                     = 0;
    uint32  offset[SYS_MAC_MAX_LANE_NUM] = {0};
    const uint32* p_step;
    const uint32* p_tbl_id_base;
    const uint32* p_fld_id_base;
    sys_datapath_lport_attr_t* port_attr = NULL;
    sys_datapath_lport_attr_t  remap_port = {0};
    
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    /*0. check fec type invalid & get mode_with_fec value*/
    if(CTC_PORT_FEC_TYPE_NONE != fec_type)
    {
        mode_fec = g_mode_with_fec_map[mode][FEC_TYPE_NORMALIZE(fec_type)];
        if(MAX_MODE_FEC == mode_fec)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Unsupported FEC type %u, mode %u\n", fec_type, mode);
            return CTC_E_INVALID_PARAM;
        }
    }
    
    /*1. info collection*/
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);
    if(SYS_DMPS_RSV_PORT == port_attr->port_type)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_fill_remap_port_attr(lchip, lport, &remap_port));
        port_attr = &remap_port;
    }

    if(SYS_TMM_IS_PCS_X16(port_attr->txqm_id))
    {
        pcs_type = PCS_X16;
        if(MCPCS_IS_X16_A(port_attr->pcs_idx))
        {
            p_tbl_id_base = g_mcpcs_tbl_id_base_x16a;
            p_fld_id_base = g_mcpcs_fld_id_base_x16a;
            p_step        = g_mcpcs_field_step_x16a;
        }
        else
        {
            p_tbl_id_base = g_mcpcs_tbl_id_base_x16b;
            p_fld_id_base = g_mcpcs_fld_id_base_x16b;
            p_step        = g_mcpcs_field_step_x16b;
        }
    }
    else
    {
        pcs_type      = PCS_X8;
        p_tbl_id_base = g_mcpcs_tbl_id_base_x8;
        p_fld_id_base = g_mcpcs_fld_id_base_x8;
        p_step        = g_mcpcs_field_step_x8;
    }

    /*2. fill base info of mcmac config list*/
    for(item = 0; item < McPcs_TOTAL_CNT; item++)
    {
        _sys_tmm_macpcs_get_cfg_flag(lchip, cfg_prop_type, item, pcs_type, port_attr, &cfg_flag);
        p_mcpcs_list[item].cfg_flag   = cfg_flag;
        p_mcpcs_list[item].table_id   = p_tbl_id_base[item];
        _sys_tmm_macpcs_get_offset(lchip, g_mcpcs_offset_type[item], port_attr, 
                                   &offset_num, offset);
        p_mcpcs_list[item].field_id_num = offset_num;
        for(idx = 0; idx < offset_num; idx++)
        {
            p_mcpcs_list[item].field_id[idx] = p_fld_id_base[item] + p_step[item] * offset[idx];
        }
        _sys_tmm_macpcs_get_ins_index(lchip, g_mcpcs_tbl_idx_type[item], port_attr, 
            &(p_mcpcs_list[item].ins), &(p_mcpcs_list[item].entry), &(p_mcpcs_list[item].index));
    }

    /*3. fill value of mcmac config list*/
    for(item = 0; item < McPcs_TOTAL_CNT; item++)
    {
        /*get fec value or non-fec*/
        value_base = (CTC_PORT_FEC_TYPE_NONE == fec_type) ? 
            g_mcpcs_mode_value_map[item][mode] : g_mcpcs_fec_value_map[item][mode_fec];
        _sys_tmm_macpcs_get_value(lchip, g_mcpcs_value_type[item], p_mcpcs_list[item].field_id_num,
            value_base, port_attr, p_mcpcs_list[item].value,
            item, mode, pcs_type, mode_fec);
        /*sepcial operation for McPcs_cfgRxDskMaxAddr*/
        if((McPcs_cfgRxDskMaxAddr == item) && (!SYS_TMM_IS_PCS_X16(port_attr->txqm_id)) && 
           ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode)))
        {
            for(idx = 0; idx < p_mcpcs_list[item].field_id_num; idx++)
            {
                p_mcpcs_list[item].value[idx] = 159;
            }
        }
        /*special operation for McPcs_resetQsgmii_resetCore*/
        if((McPcs_resetQsgmii_resetCore == item) && ((!(SYS_TMM_IS_PCS_X16(port_attr->txqm_id) && (8 > port_attr->pcs_idx))) || 
            (0 != port_attr->mac_id % 4)))
        {
            p_mcpcs_list[item].cfg_flag = ITEM_NO_WRITE;
        }
#ifdef EMULATION_ENV
        /*special operation for McPcs_cfgQsgmiiSgmii_anEnable*/
        if((McPcs_cfgQsgmiiSgmii_anEnable == item) && (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode))
        {
            for(idx = 0; idx < p_mcpcs_list[item].field_id_num; idx++)
            {
                p_mcpcs_list[item].value[idx] = 0;
            }
        }
        /*special operation for McPcs_cfgSgmii_anEnable*/
        if((McPcs_cfgSgmii_anEnable == item) && 
           ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode)))
        {
            for(idx = 0; idx < p_mcpcs_list[item].field_id_num; idx++)
            {
                p_mcpcs_list[item].value[idx] = 0;
            }
        }
#endif
        if(((McPcs_cfgQsgmiiSgmii_unidirectionEn == item) || (McPcs_cfgQsgmiiSgmii_anEnable == item) || 
            (McPcs_cfgQsgmiiSgmii_anegMode == item) || (McPcs_cfgQsgmii_cfgTxCreditThrd == item) || 
            (McPcs_cfgQsgmii_reAlignEachEn == item)) && 
           (!(SYS_TMM_IS_PCS_X16(port_attr->txqm_id) && (8 > port_attr->pcs_idx))))
        {
            p_mcpcs_list[item].cfg_flag = ITEM_NO_WRITE;
        }
    }
    
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    return CTC_E_NONE;
}

int32
_sys_tmm_macpcs_config_write_tables(uint8 lchip, uint16 lport, sys_macpcs_config_item_t *p_mcmac_list, uint8 list_len)
{
    uint32 curr_item    = 0;
    uint32 next_item    = 0;
    uint32 index        = 0;
    uint32 tbl_id       = 0;
    uint32 fld_id       = 0;
    uint32 val32        = 0;
    uint32 cmd          = 0;
    uint32 fld_idx      = 0;
    uint32 val_arr[2];
    uint32 write_st[SYS_MAC_MAX_STRUCT_WORD] = {0};
#ifdef EMULATION_ENV
    int32 ret = 0;
#endif
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    for(curr_item = 0; curr_item < list_len; curr_item++)
    {
        if(ITEM_NO_WRITE == p_mcmac_list[curr_item].cfg_flag)
        {
            continue;
        }

        /*1. read table*/
        /*1.1 collect info: tbl_id, p_struct*/
        tbl_id = p_mcmac_list[curr_item].table_id;
        index  = p_mcmac_list[curr_item].index;
        
        /*special opration for type ITEM_WRITE_ON_READ*/
        if(ITEM_WRITE_ON_READ == p_mcmac_list[curr_item].cfg_flag)
        {
            for(fld_idx = 0; fld_idx < p_mcmac_list[curr_item].field_id_num; fld_idx++)
            {
                fld_id = p_mcmac_list[curr_item].field_id[fld_idx];

                sal_memset(val_arr, 0, 2 * sizeof(uint32));
                
                cmd = DRV_IOR(tbl_id, fld_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, val_arr));

                _sys_tmm_macpcs_get_write_on_read_value(lchip, lport, curr_item,
                                                     p_mcmac_list[curr_item].value[fld_idx], val_arr);

                cmd = DRV_IOW(tbl_id, fld_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, val_arr));
                DRV_IOW_PRINT_NZ(lchip, tbl_id, fld_id, val_arr[0], p_mcmac_list[curr_item].ins, p_mcmac_list[curr_item].entry);
                DRV_IOW_PRINT_NZ(lchip, tbl_id, fld_id, val_arr[1], p_mcmac_list[curr_item].ins, p_mcmac_list[curr_item].entry);
            }
            continue;
        }

        /*1.3 do read action*/
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
#ifdef EMULATION_ENV
        ret = (DRV_IOCTL(lchip, index, cmd, write_st));
        if(0 != ret)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% IOR: tbl_id %u, curr_item %u, index %u, ret %d\n", tbl_id, curr_item, index, ret);
        }
#else
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, write_st));
#endif

        /*2. write field (merge R&W actions of different fields in same table)*/
        for(; curr_item < list_len; curr_item++)
        {
            for(fld_idx = 0; fld_idx < p_mcmac_list[curr_item].field_id_num; fld_idx++)
            {
                fld_id = p_mcmac_list[curr_item].field_id[fld_idx];
                val32  = p_mcmac_list[curr_item].value[fld_idx];
                DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, write_st, p_mcmac_list[curr_item].ins, p_mcmac_list[curr_item].entry);
            }
            next_item = curr_item + 1;
            if((next_item < list_len) && (p_mcmac_list[curr_item].table_id != p_mcmac_list[next_item].table_id))
            {
                break;
            }
        }

        /*3. write table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
#ifdef EMULATION_ENV
        ret = (DRV_IOCTL(lchip, index, cmd, write_st));
        if(0 != ret)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% IOW: tbl_id %u, curr_item %u, index %u, ret %d\n", tbl_id, curr_item, index, ret);
        }
#else
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, write_st));
#endif

        if(curr_item >= list_len)
        {
            break;
        }
    }

    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_fec_soft_table_upt(uint8 lchip, uint16 lport, ctc_port_fec_type_t fec_type)
{
    uint8 i = 0;
    uint8 logical_serdes_id = 0;
    sys_datapath_serdes_info_t* p_serdes  = NULL;
    sys_datapath_lport_attr_t*  port_attr = NULL;
    
    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    if (!port_attr)
    {
        return CTC_E_NOT_INIT;
    }
    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num, CTC_E_INVALID_PARAM);

    for (i = 0; i < port_attr->serdes_num; i++)
    {
        _sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, port_attr->multi_serdes_id[i], &logical_serdes_id);
        SYS_CONDITION_CONTINUE(SYS_TMM_USELESS_ID8 == logical_serdes_id);
        CTC_ERROR_RETURN(sys_usw_datapath_get_serdes_info(lchip, logical_serdes_id, &p_serdes));
        p_serdes->fec_type = fec_type;
    }

    p_usw_mac_master[lchip]->mac_prop[lport].port_fec_val = fec_type;

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_mcmac_config(uint8 lchip,
                            uint16 lport,
                            ctc_chip_serdes_mode_t mode,
                            ctc_port_fec_type_t fec_type, 
                            uint8 cfg_prop_type)
{
    int32  ret = CTC_E_NONE;
    sys_macpcs_config_item_t* p_mcmac_list = NULL;

    /*1. init config list*/
    p_mcmac_list = (sys_macpcs_config_item_t*)mem_malloc(MEM_DMPS_MODULE, McMac_TOTAL_CNT * sizeof(sys_macpcs_config_item_t));
    if(NULL == p_mcmac_list)
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(p_mcmac_list, 0, McMac_TOTAL_CNT * sizeof(sys_macpcs_config_item_t));

    /*2. fill config list*/
    CTC_ERROR_GOTO(_sys_tmm_mac_fill_config_list_mcmac(lchip, lport, mode, fec_type, p_mcmac_list, cfg_prop_type), 
                   ret, RELEASE_PTR_RETURN);

    /*3. write tables*/
    CTC_ERROR_GOTO(_sys_tmm_macpcs_config_write_tables(lchip, lport, p_mcmac_list, McMac_TOTAL_CNT), 
                   ret, RELEASE_PTR_RETURN);

RELEASE_PTR_RETURN:
    mem_free(p_mcmac_list);
    return ret;
}

int32
_sys_tmm_mac_set_mcpcs_config(uint8 lchip,
                            uint16 lport,
                            ctc_chip_serdes_mode_t mode,
                            ctc_port_fec_type_t fec_type, 
                            uint8 cfg_prop_type)
{
    int32  ret = CTC_E_NONE;
    sys_macpcs_config_item_t* p_mcpcs_list = NULL;

    /*1. init config list*/
    p_mcpcs_list = (sys_macpcs_config_item_t*)mem_malloc(MEM_DMPS_MODULE, McPcs_TOTAL_CNT * sizeof(sys_macpcs_config_item_t));
    if(NULL == p_mcpcs_list)
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(p_mcpcs_list, 0, McPcs_TOTAL_CNT * sizeof(sys_macpcs_config_item_t));

    /*2. fill config list*/
    CTC_ERROR_GOTO(_sys_tmm_mac_fill_config_list_mcpcs(lchip, lport, mode, fec_type, p_mcpcs_list, cfg_prop_type), 
                   ret, RELEASE_PTR_RETURN);

    /*3. write tables*/
    CTC_ERROR_GOTO(_sys_tmm_macpcs_config_write_tables(lchip, lport, p_mcpcs_list, McPcs_TOTAL_CNT), 
                   ret, RELEASE_PTR_RETURN);

RELEASE_PTR_RETURN:
    mem_free(p_mcpcs_list);
    return ret;
}

/*
 * 3 calls:
 *   1) init
 *   2) dynamic switch
 *   3) user API call
 *  if 1)/2) and Qsgmii/Usxgmii, need do quadreset.
 */
int32
_sys_tmm_mac_set_mac_config(uint8 lchip,
                            uint16 lport,
                            ctc_chip_serdes_mode_t mode,
                            ctc_port_fec_type_t fec_type,
                            sys_dmps_lport_type_t port_type,
                            uint8 is_init)
{
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n\n\n######### %s start! lport %u, mode %u, fec_type %u\n", __FUNCTION__, lport, mode, fec_type);

    SYS_CONDITION_RETURN(CTC_CHIP_MAX_SERDES_MODE <= mode, CTC_E_INVALID_PARAM);

    if(SYS_DMPS_INACTIVE_NETWORK_PORT != port_type)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mcmac_config(lchip, lport, mode, fec_type, MACPCS_CFG_INIT));
    }

    CTC_ERROR_RETURN(_sys_tmm_mac_set_mcpcs_config(lchip, lport, mode, fec_type, MACPCS_CFG_INIT));

    CTC_ERROR_RETURN(_sys_tmm_mac_set_fec_soft_table_upt(lchip, lport, fec_type));

    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n######### %s end!\n\n\n", __FUNCTION__);

    return CTC_E_NONE;
}




int32
_sys_tmm_mac_calculate_interval(uint8 lchip, uint32 speed, uint16 dp_mac_id, uint32 num, uint8 low_prio, uint8 extra, 
                                          uint8 bw_ratio, int32* interval)
{
    uint32 cnt = 0;
    uint32 avg_base = 0;
    uint32 cnt_org = 0;
    uint32 oversub_bw = (500 == p_usw_datapath_master[lchip]->core_plla) ? 230 : 
                        (800 == p_usw_datapath_master[lchip]->core_plla) ? 350 : 400;

    if(0 != speed)
    {
        avg_base = (oversub_bw * SYS_TMM_MAC_CALENDAR_MULTI_FACTOR) / speed;
    }
    else
    {
        *interval = 0;
        return CTC_E_NONE;
    }

    cnt_org = avg_base / SYS_TMM_MAC_CALENDAR_MULTI_FACTOR;
    cnt = cnt_org;

    *interval = cnt;

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_calculate_calendar(uint8 lchip, uint8 dp_id, uint8 dp_txqm_id, 
                                          uint16 cal[128], uint16* p_walk_end, uint8* p_valid)
{
    uint8  mactx_reorder_en[SYS_TMM_MAX_MAC_NUM_PER_TXQM] = {0};
    int32  interval[SYS_TMM_MAX_MAC_NUM_PER_TXQM] = {0};/*interval,per port*/
    int32  interval_cp[SYS_TMM_MAX_MAC_NUM_PER_TXQM+1] = {0};/*interval,per port*/
    int32  interval_order[SYS_TMM_MAX_MAC_NUM_PER_TXQM] = {0};/*interval,per port*/
    uint8  active[SYS_TMM_MAX_MAC_NUM_PER_TXQM+1] = {0};/*active list*/
    uint8  en[SYS_TMM_MAX_MAC_NUM_PER_TXQM] = {0};/*port enable*/
    uint8  first_cal_record_en[SYS_TMM_MAX_MAC_NUM_PER_TXQM] = {0};/*record the index first select*/
    uint32 speed_sum = 0;
    uint32 speed = 0;
    uint32 oversub_bw = (500 == p_usw_datapath_master[lchip]->core_plla) ? 230 : 
                        (800 == p_usw_datapath_master[lchip]->core_plla) ? 350 : 400;
    uint8  oversub_flag = FALSE;
    uint32 member_num = 0;
    uint8  bw_ratio = 1;
    /*uint8  spd_2nd_flag = FALSE;*/
    /*uint8  spd_2nd_lock = 0;*/
    uint8  spd_max_lock = 0;
    uint8  low_prio = FALSE;
    uint16 cycle    = 0;  /*calendar cycle*/
    uint8  done     = FALSE;
    uint8  error    = FALSE;
    uint8  force_sel = FALSE;
    uint32 min_id = 1;
    int32  min_intv = 10000;
    uint8  min_index = 0;
    uint8  exchange_flag = 0;
    uint32 selport = 0;
    uint8  extra = FALSE;
    uint8  active_flag = FALSE;
    uint8  illegal = FALSE;
    uint8  reload_active = FALSE;
    uint8  mactx_illegal = 0;
    uint8  i, k;
    uint16 dp_mac_id = 0;
    
    uint32 actual_interval = 0;
    uint32 expect_interval = 0;
    uint32 multi_factor = 1000;
    uint32 last_gap = 0;
    int32  ret = CTC_E_NONE;
    int32* cnt_history = NULL;
    sys_cal_info_collect_t* cal_info = NULL;
    sys_mac_cal_heap_t*     p_heap   = NULL;

    cnt_history = (int32*)mem_malloc(MEM_DMPS_MODULE, SYS_TMM_MAX_MAC_NUM_PER_DP * sizeof(int32));
    CTC_ERROR_GOTO((NULL == cnt_history) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_1);
    sal_memset(cnt_history, 0, SYS_TMM_MAX_MAC_NUM_PER_DP * sizeof(int32));

    cal_info = (sys_cal_info_collect_t*)mem_malloc(MEM_DMPS_MODULE, (SYS_TMM_MAX_MAC_NUM_PER_DP + (SYS_TMM_CPUMAC_SERDES_NUM / 2)) * sizeof(sys_cal_info_collect_t));
    CTC_ERROR_GOTO((NULL == cal_info) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_2);
    sys_tmm_calendar_speed_info_collect(lchip, cal_info, dp_id, dp_txqm_id, SYS_TMM_MAC_CAL);

    p_heap = (sys_mac_cal_heap_t*)mem_malloc(MEM_DMPS_MODULE, sizeof(sys_mac_cal_heap_t));
    CTC_ERROR_GOTO((NULL == p_heap) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_3);
    sal_memset(p_heap, 0, sizeof(sys_mac_cal_heap_t));

    /*initial phase*/
    for(i = 0; i < SYS_TMM_MAX_MAC_NUM_PER_TXQM; i++)
    {
        dp_mac_id = dp_txqm_id * SYS_TMM_MAX_MAC_NUM_PER_TXQM + i;
        /*consider 2.5G bandwidth as 25G*/
        speed = (SYS_ALLOC_NORMAL == cal_info[dp_mac_id].cl_type) ? 
                ((2 == cal_info[dp_mac_id].speed) ? 25 : cal_info[dp_mac_id].speed) : 0;
        speed_sum += speed;
        p_heap->first_cal_record[i] = 0;
        first_cal_record_en[i] = TRUE;
    }

    SYS_USW_VALID_PTR_WRITE(p_valid, TRUE);
    if(0 == speed_sum)
    {
        SYS_USW_VALID_PTR_WRITE(p_valid, FALSE);
        goto RELEASE_PTR_RETURN_4;
    }

    if(speed_sum > SYS_TMM_MAX_BANDWIDTH_PER_TXQM)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [MacTx]Error: total speed %u > 400G, dp_id %u\n", speed_sum, dp_id);
        ret = CTC_E_INVALID_PARAM;
        goto RELEASE_PTR_RETURN_4;
    }
    /*look up low priority speed, inherit from Duet2*/
    /*spd_2nd_flag = FALSE;*/
    /*spd_2nd_lock = 0;*/
    spd_max_lock = 0;

    for(i = 0; i < SYS_TMM_MAX_MAC_NUM_PER_TXQM; i++)
    {
        dp_mac_id = dp_txqm_id * SYS_TMM_MAX_MAC_NUM_PER_TXQM + i;
        /*consider 2.5G bandwidth as 25G*/
        speed = (SYS_ALLOC_NORMAL == cal_info[dp_mac_id].cl_type) ? 
                ((2 == cal_info[dp_mac_id].speed) ? 25 : cal_info[dp_mac_id].speed) : 0;
        if((1 <= speed) && (spd_max_lock < speed))
        {
            /*if((0 != spd_2nd_lock) && (spd_2nd_lock < spd_max_lock))
            {
                spd_2nd_flag = TRUE;
            }*/
            /*spd_2nd_lock = spd_max_lock;*/
            spd_max_lock = speed;
        }
    }

    for(i = 0; i < SYS_TMM_MAX_MAC_NUM_PER_TXQM; i++)
    {
        dp_mac_id = dp_txqm_id * SYS_TMM_MAX_MAC_NUM_PER_TXQM + i;
        /*consider 2.5G bandwidth as 25G*/
        speed = (SYS_ALLOC_NORMAL == cal_info[dp_mac_id].cl_type) ? 
                ((2 == cal_info[dp_mac_id].speed) ? 25 : cal_info[dp_mac_id].speed) : 0;
        low_prio = oversub_flag && (spd_max_lock != speed);
        /*initial interval*/
        _sys_tmm_mac_calculate_interval(lchip, speed, dp_mac_id, 1, low_prio, 0, bw_ratio, interval + i);
        /*initial active / enable and num*/
        if(1 <= speed)
        {
            active[i] = TRUE;
            en[i] = TRUE;
            p_heap->num[i] = 1;
            member_num++;
        }
        else  /*invalid port*/
        {
            active[i] = FALSE;
            en[i] = FALSE;
            p_heap->num[i] = 1;
            //member_num++;
        }
    }

    /*main function*/
    while((!done) && (!(error == 1)))
    {
        /*reorder*/
        for(i = 1; i < SYS_TMM_MAX_MAC_NUM_PER_TXQM+1; i++)
        {
            interval_cp[i] = interval[i-1];
        }
        /*stage1. bubble sort*/  
        // kegc | only satisfy sort requre, we can use 
        for(i = 1; i <= member_num; i++)
        {
            min_id = 1;
            min_intv = 10000;

            for(k = 1; k <= SYS_TMM_MAX_MAC_NUM_PER_TXQM; k++)
            {
                if((interval_cp[k]) && (min_intv > interval_cp[k]))
                {
                    min_intv = interval_cp[k];
                    min_id = k;
                }
                else if((interval_cp[k]) && (min_intv == interval_cp[k]) && active[k])
                {
                    min_id = k;
                }
            }
            interval_cp[min_id] = 10000;
            interval_order[i] = min_intv;
            p_heap->portid_order[i] = min_id - 1;
        }

        /*stage2. calendar select*/
        min_index = p_heap->portid_order[1];  /*default min interval portid*/
        //min_intv = interval_order[1];  /*default min interval*/
        /*detect error*/
        force_sel = FALSE;
        exchange_flag = FALSE;
        for(i = 1; i <= member_num; i++)
        {
            if(i > interval_order[i])
            {
                error = 2;
                //SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [MacTx]automatic constrain failed! failed id = %u, interval = %u, cycle = %u\n", 
                    //i, interval_order[i], cycle);
                for(k = 1; k <= member_num; k++)
                {
                    //SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [MacTx]bubble sort index %u, interval %u\n", k, interval_order[k]) ;
                }
                break;
            } 
            /*get the mac id*/
            selport = p_heap->portid_order[i];
            /*exchange min_index due to : 
            1: must in active list 
            2: doesn't set exchange_flag before 
            3: doesn't set force_sel before 
            4: has small interval*/
            if((active[selport]) && (!exchange_flag) && (!force_sel))
            {
                min_index = p_heap->portid_order[i];
                exchange_flag = TRUE;
                /*min_intv = interval_order[i];*/
            }
            /*force_sel eq 1 means calendar can't select the portid_order index larger than i*/
            if(i == interval_order[i])
            {
                force_sel = TRUE;
            }
        }

        /*stage3. maintain DS*/
        /*stage3.1 all interval will decrease 1*/
        for(i = 0; i < SYS_TMM_MAX_MAC_NUM_PER_TXQM; i++)
        {
            if(en[i])
            {
                interval[i]--;
            }
        }
        /*stage3.2 generage calendar data*/
        cal[cycle] = min_index;

        /*stage3.3  re-calulate interval*/
        dp_mac_id = dp_txqm_id * SYS_TMM_MAX_MAC_NUM_PER_TXQM + min_index;
        /*consider 2.5G bandwidth as 25G*/
        speed = (SYS_ALLOC_NORMAL == cal_info[dp_mac_id].cl_type) ? 
                ((2 == cal_info[dp_mac_id].speed) ? 25 : cal_info[dp_mac_id].speed) : 0;
        low_prio = oversub_flag && (!(spd_max_lock == speed));
        _sys_tmm_mac_calculate_interval(lchip, speed, dp_mac_id, p_heap->num[min_index], low_prio, extra, bw_ratio, 
            interval + min_index);
        p_heap->num[min_index]++;  /*num++ after re-calculate interval*/
        active[min_index] = FALSE;

        /*stage3.4 record the first calendar cycle*/
        if(first_cal_record_en[min_index])
        {
            p_heap->first_cal_record[min_index] = cycle;
            first_cal_record_en[min_index] = FALSE;
        }

        /*stage4. finish calendar calculate*/
        /*4.1 detect active flag*/
        active_flag = FALSE;

        for(i = 0; i < SYS_TMM_MAX_MAC_NUM_PER_TXQM; i++)
        {
            if(active[i])
            {
                active_flag = TRUE;
            }
        }
        /*4.2 detect interval violation*/
        /*NetTx use 1*192+1 Byte to calculate interval average*/
        if(!active_flag)
        {
            illegal = FALSE;
            mactx_illegal = 0;
            sal_memset(mactx_reorder_en, FALSE, SYS_TMM_MAX_MAC_NUM_PER_TXQM*sizeof(uint8));
            for(i = 0; i < SYS_TMM_MAX_MAC_NUM_PER_TXQM; i++)
            {
                dp_mac_id = dp_txqm_id * SYS_TMM_MAX_MAC_NUM_PER_TXQM + i;
                /*consider 2.5G bandwidth as 25G*/
                speed = (SYS_ALLOC_NORMAL == cal_info[dp_mac_id].cl_type) ? 
                        ((2 == cal_info[dp_mac_id].speed) ? 25 : cal_info[dp_mac_id].speed) : 0;
                mactx_reorder_en[i] = FALSE;
                /*port enable*/
                if(0 != speed)
                {
                    /*192*1+1 B could reach performance*/
                    /*expect_interval = (400 * multi_factor) / speed;*/
                    /*expect_interval = (SYS_TMM_MAC_CALENDAR_CLK_MF * 8 * 64) / speed;*/
                    
                    /*if(500 >= SYS_TMM_MAC_CALENDAR_CLK_MF)
                    {
                        expect_interval = (SYS_TMM_MAC_CALENDAR_CLK_MF * 8 * 64) / speed;
                    }
                    else
                    {
                        expect_interval = (400 * multi_factor) / speed;
                    }*/
                    expect_interval = (oversub_bw * multi_factor) / speed;

                    actual_interval = ((cycle + 1) * multi_factor) / (p_heap->num[i] - 1);

                    if(actual_interval > expect_interval)
                    {
                        illegal = TRUE;
                        active[i] = TRUE;
                    }
                    /*tail --> head gap illegal calculate*/
                    last_gap = p_heap->first_cal_record[i];
                    if(last_gap > interval[i])
                    {
                        illegal = TRUE;
                        active[i] = TRUE;
                    }
                }
            }
            /*special for MacTx*/
            /*adjust calendar if interval too small*/
            /*omitted*/
            /*becasue MacTx is abandoned, mactx_illegal is not funcational*/
            reload_active = (illegal || (0 != mactx_illegal));
            /*finish if no violation*/
            if(!reload_active)
            {
                done = TRUE;
                SYS_USW_VALID_PTR_WRITE(p_walk_end, cycle);
            }
        }
        cycle++;
        if(128 < cycle)
        {
            error = 1;
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [MacTx]calendar cycle larger than 128, cycle %u \n", cycle);
        }
    }
    if(1 == error)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [MacTx]calendar generate mistake ! error %u\n", error);
        ret = CTC_E_INVALID_PARAM;
        goto RELEASE_PTR_RETURN_4;
    }

RELEASE_PTR_RETURN_4:
    mem_free(p_heap);
RELEASE_PTR_RETURN_3:
    mem_free(cal_info);
RELEASE_PTR_RETURN_2:
    mem_free(cnt_history);
RELEASE_PTR_RETURN_1:
    return ret;
}


int32
sys_tmm_mac_calendar_get_cal_entry(uint8 lchip, uint8 dp_id, uint8 txqm_id, uint32 txqm_mac_id, uint32* p_val)
{
    uint32 mac_id = SYS_TMM_USELESS_ID32;
    uint16 lport  = SYS_TMM_USELESS_ID16;
    uint32 val_32 = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    if(SYS_FLEXE_UNUSED_FLAG_U8 == txqm_mac_id)
    {
        val_32 = SYS_TMM_MAC_CALENDAR_ROUND_ID;
    }
    else
    {
        mac_id = txqm_id * SYS_TMM_MAX_MAC_NUM_PER_TXQM + txqm_mac_id + dp_id*SYS_TMM_MAX_MAC_NUM_PER_DP;
        lport  = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);
        CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
        
        val_32 = ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || 
                  (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode) || 
                  (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)) ? SYS_TMM_MAC_CALENDAR_ROUND_ID : txqm_mac_id;
    }

    SYS_USW_VALID_PTR_WRITE(p_val, val_32);

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_mac_calculate_calendar_fixlen(uint8 lchip, uint8 dp_id, uint8 dp_txqm_id, 
                                                   uint16 cal[128], uint16* p_walk_end, uint8* p_valid)
{
    uint8  dp_mac_id;
    uint8  txqm_mac_id;
    uint8  index            = 0;
    uint8  cycle            = 0;
    uint8  client_num       = 0;
    uint8  fix_client_num   = 0;
    uint8  select_index     = 0;
    uint8  rm_cnt           = 0;
    int32  min_interval     = 0;
    uint8  min_sel          = FALSE;
    uint32 min_speed        = 0;
    int32  interval_cal     = 0;
    uint32 client_list_num  = 0;
    uint32 client_speed_sum = 0;
    uint32 blank_slot_num   = 0;
    int32  ret              = CTC_E_NONE;
    uint32 ratio            = 10000;
    uint8  reload_flag1     = FALSE;
    uint8  reload_flag2     = FALSE;
    uint32 max_bw_txqm      = (500 == p_usw_datapath_master[lchip]->core_plla) ? 200 : 
                              (800 == p_usw_datapath_master[lchip]->core_plla) ? 250 : 400;
    uint16 max_step_num     = (uint16)(max_bw_txqm / SYS_FLEXE_SLOT_SPEED);
    sys_flexe_client_calcfg_t  calcfg[SYS_TMM_MAX_MAC_NUM_PER_TXQM] = {{0}};
    sys_flexe_client_calgen_t* key_list = NULL;
    sys_cal_info_collect_t*    cal_info = NULL;

    cal_info = (sys_cal_info_collect_t*)mem_malloc(MEM_DMPS_MODULE, 
        (SYS_TMM_MAX_MAC_NUM_PER_DP+SYS_TMM_CPUMAC_SERDES_NUM/2) * sizeof(sys_cal_info_collect_t));
    CTC_ERROR_GOTO((NULL == cal_info) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_1);
    sys_tmm_calendar_speed_info_collect(lchip, cal_info, dp_id, dp_txqm_id, SYS_TMM_MAC_FIXLEN_CAL);

    /*1. info preparation*/
    for (txqm_mac_id = 0; txqm_mac_id < SYS_TMM_MAX_MAC_NUM_PER_TXQM; txqm_mac_id++)
    {
        dp_mac_id = txqm_mac_id + dp_txqm_id*SYS_TMM_MAX_MAC_NUM_PER_TXQM;
        SYS_CONDITION_CONTINUE(cal_info[dp_mac_id].cl_type == SYS_ALLOC_NONE_MODE);
        /*add up valid speed sum and number*/
        client_speed_sum  += cal_info[dp_mac_id].speed;
        client_list_num++;
        /*combine valid speed & mac_id into calcfg to simplify following steps*/
        calcfg[index].speed  = cal_info[dp_mac_id].speed;
        calcfg[index].mac_id = txqm_mac_id;
        index++;
    }

    SYS_USW_VALID_PTR_WRITE(p_valid, TRUE);
    if((0 == client_speed_sum) || (client_speed_sum > max_bw_txqm))
    {
        SYS_USW_VALID_PTR_WRITE(p_valid, FALSE);
        ret = (0 == client_speed_sum) ? CTC_E_NONE : CTC_E_INVALID_CONFIG;
        goto RELEASE_PTR_RETURN_2;
    }

    client_num = client_list_num;

    if (client_speed_sum < max_bw_txqm)
    {
        blank_slot_num = (max_bw_txqm-client_speed_sum) / SYS_FLEXE_SLOT_SPEED;
        for (index = 0; index < blank_slot_num; index++)
        {
            client_list_num++;               
        }
    }
    fix_client_num = client_list_num;

    key_list = (sys_flexe_client_calgen_t*)mem_malloc(MEM_DMPS_MODULE, sizeof(sys_flexe_client_calgen_t) * fix_client_num);
    CTC_ERROR_GOTO((NULL == key_list) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_2);
    sal_memset(key_list, 0, sizeof(sys_flexe_client_calgen_t) * fix_client_num);

    for(index = 0; index < fix_client_num; index++)
    {
        key_list[index].speed         = (index < client_num) ? calcfg[index].speed : SYS_FLEXE_SLOT_SPEED;
        key_list[index].cur_interval  = max_bw_txqm / key_list[index].speed;
        key_list[index].init_interval = ratio * key_list[index].speed / max_bw_txqm;
        key_list[index].sch_cnt_max   = key_list[index].speed / SYS_FLEXE_SLOT_SPEED;
    }

    for(cycle = 0; cycle < max_step_num; cycle ++)
    {
        /*2. select client, it's cur_interval is minimum*/
        min_interval = MCHIP_CAP(SYS_CAP_FLEXE_MAX_CYCLE);
        select_index = 0;
        min_sel      = FALSE;
        min_speed    = 0;
        for(index = 0; index < fix_client_num; index++)
        {
            if(0 == key_list[index].rm_flag)
            {
                if(key_list[index].cur_interval < min_interval)
                {
                    min_interval = key_list[index].cur_interval;
                    select_index = index;
                    min_sel      = key_list[index].sel;
                    min_speed    = key_list[index].speed;
                }
                /*optimization: if reloaded ports have same cur_interval and it is minimal, prefer to choose the bigger one*/
                else if(key_list[index].cur_interval == min_interval)
                {
                    if((key_list[index].sel == 1) && (min_sel == 1))
                    {
                        if(key_list[index].speed > min_speed)
                        {
                            min_interval = key_list[index].cur_interval;
                            select_index = index;
                            min_sel      = key_list[index].sel;
                            min_speed    = key_list[index].speed;
                        }
                    }
                }
            }
        }

        cal[cycle] = (select_index < client_num ? calcfg[select_index].mac_id : SYS_FLEXE_UNUSED_FLAG_U8);

        /*3. update database*/
        key_list[select_index].sel          = 0;
        key_list[select_index].pending      = 1;
        key_list[select_index].cur_interval = ratio / (key_list[select_index].init_interval);
        key_list[select_index].rm_flag      = 1;
        key_list[select_index].sch_sel_cnt ++;
        key_list[select_index].sch_cnt ++;
        rm_cnt ++;        
        
        for(index = 0; index < fix_client_num; index++)
        {
            reload_flag1 = FALSE;
            reload_flag2 = FALSE;

            key_list[index].sch_total_cnt++;
            key_list[index].cur_interval--;

            if((key_list[index].sch_cnt) == (key_list[index].sch_cnt_max))
            {
                key_list[index].sel     = 0;
                key_list[index].pending = 0;
            }

            /*4. judge reloading*/
            interval_cal = key_list[index].pending ? (ratio * key_list[index].sch_sel_cnt / key_list[index].sch_total_cnt) : 0;
            reload_flag1 = ((key_list[index].pending == 1) && (0 == key_list[index].sel)) && 
                            (interval_cal < key_list[index].init_interval);
            reload_flag2 = (rm_cnt == fix_client_num);

            if(reload_flag1 || reload_flag2)
            {
                key_list[index].sel     = 1;
                key_list[index].rm_flag = 0;
                rm_cnt --;
                if(key_list[index].init_interval == (ratio * key_list[index].sch_sel_cnt / key_list[index].sch_total_cnt))
                {
                    key_list[index].sch_sel_cnt = 0;
                    key_list[index].sch_total_cnt = 0;
                }
            }
        }
    }

    SYS_USW_VALID_PTR_WRITE(p_walk_end, max_step_num-1);

    mem_free(key_list);
RELEASE_PTR_RETURN_2:
    mem_free(cal_info);
RELEASE_PTR_RETURN_1:
    return ret;
}

int32
_sys_tmm_mac_get_calendar(uint8 lchip, uint8 dp_id, uint8 dp_txqm_id, uint16 cal[128], uint16* p_walk_end, uint8* p_valid, uint8 is_tx)
{

    uint16 mac_id;
    uint16 lport;
    uint16 txqm_mac;
    uint8  fixlen_flag = FALSE; /*judge if using fixlen mac calendar. only ((HS && 1G exist TXQMs) || RX) need this way.*/
    sys_datapath_lport_attr_t* port_attr = NULL;
    uint8 calendar_skip = 0;

    if (dp_txqm_id>=2)
    {
        for(txqm_mac = 0; txqm_mac < SYS_TMM_MAX_MAC_NUM_PER_TXQM; txqm_mac++)
        {
            mac_id    = SYS_TMM_MAX_MAC_NUM_PER_DP * dp_id + (dp_txqm_id * SYS_TMM_MAX_MAC_NUM_PER_TXQM + txqm_mac);
            lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);
            SYS_CONDITION_CONTINUE(SYS_COMMON_USELESS_MAC == lport);
            port_attr = sys_usw_datapath_get_port_capability(lchip, lport);
            SYS_CONDITION_CONTINUE((NULL == port_attr) || (port_attr->port_type != SYS_DMPS_NETWORK_PORT));
            if (CTC_PORT_IF_FLEXE == port_attr->interface_type)
            {
                calendar_skip = 1;
                break;
            }
        }
    }
    else if((2 > dp_txqm_id) && (is_tx))
    {
        for(txqm_mac = 0; txqm_mac < SYS_TMM_MAX_MAC_NUM_PER_TXQM; txqm_mac++)
        {
            mac_id    = SYS_TMM_MAX_MAC_NUM_PER_DP * dp_id + (dp_txqm_id * SYS_TMM_MAX_MAC_NUM_PER_TXQM + txqm_mac);
            lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);
            SYS_CONDITION_CONTINUE(SYS_COMMON_USELESS_MAC == lport);
            port_attr = sys_usw_datapath_get_port_capability(lchip, lport);
            SYS_CONDITION_CONTINUE((NULL == port_attr) || (port_attr->port_type != SYS_DMPS_NETWORK_PORT));

            if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode) ||
               (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
                fixlen_flag = TRUE;
                break;
            }
        }
    }
    else if(!is_tx)
    {
        fixlen_flag = TRUE;
    }
    if (1 == calendar_skip)
    {
        SYS_USW_VALID_PTR_WRITE(p_valid, FALSE);
        return CTC_E_NONE;
    }

    if(fixlen_flag)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_calculate_calendar_fixlen(lchip, dp_id, dp_txqm_id, cal, p_walk_end, p_valid));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_calculate_calendar(lchip, dp_id, dp_txqm_id, cal, p_walk_end, p_valid));
    }
    return CTC_E_NONE;
}

/*
 * @brief       tx & rx
 * @details     calCtrl and cal
 */
int32
sys_tmm_set_mac_calendar(uint8 lchip, uint8 dp_id, uint8 dp_txqm_id)
{
    uint16 cal_rx[128] = {0};
    uint16 walk_end_rx = 0;
    uint16 cal_tx[128] = {0};
    uint16 walk_end_tx = 0;
    uint32 cmd = 0;
    uint32 val_32 = 0;
    uint32 entry_id = 0;
    uint8 i = 0;
    uint8 is_back_cal = 0;
    uint32 table = 0;
    uint32 field = 0;
    uint8  txqm_id = SYS_TMM_TXQM_NUM_PER_DP*dp_id + dp_txqm_id;
    uint8  valid_flag_rx = TRUE;
    uint8  valid_flag_tx = TRUE;
    McMacTxCal_m mactx_cal;
    McMacRxCal_m macrx_cal;
    McMacCalCtrl_m cal_ctrl;

    CTC_ERROR_RETURN(_sys_tmm_mac_get_calendar(lchip, dp_id, dp_txqm_id, cal_rx, &walk_end_rx, &valid_flag_rx, FALSE));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_calendar(lchip, dp_id, dp_txqm_id, cal_tx, &walk_end_tx, &valid_flag_tx, TRUE));
    SYS_CONDITION_RETURN((FALSE == valid_flag_rx) && (FALSE == valid_flag_tx), CTC_E_NONE);
    SYS_CONDITION_RETURN(((128 <= walk_end_rx) || (128 <= walk_end_tx)), CTC_E_INVALID_CONFIG);

    entry_id = DRV_INS(txqm_id, 0);
    cmd = DRV_IOR(McMacCalCtrl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, entry_id, cmd, &cal_ctrl));

    val_32 = GetMcMacCalCtrl(V, cfgMcMacTxReady_f, &cal_ctrl);
    is_back_cal = GetMcMacCalCtrl(V, cfgCalEntrySel_f, &cal_ctrl);
    if(!val_32)
        is_back_cal = 0;
    else
        is_back_cal = is_back_cal ? 0 : 1;
    
// MacTxCal[Bak|]   -------------        
    /* TX entry */
    table = (is_back_cal ? McMacTxCalBak_t : McMacTxCal_t);
    field = McMacTxCalBak_calEntry_f;

    for(i = 0; i <= walk_end_tx; i++)    
    {       
        entry_id = DRV_INS(txqm_id, i);
        cmd = DRV_IOR(table, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, entry_id, cmd, &mactx_cal));

        val_32 = cal_tx[i];
        DRV_IOW_FIELD_NZ(lchip, table, field, &val_32, &mactx_cal, txqm_id, i);

        cmd = DRV_IOW(table, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, entry_id, cmd, &mactx_cal));
    }
// MacRxCal[Bak|]   --------------
    /* RX entry */
    table = (is_back_cal ? McMacRxCalBak_t : McMacRxCal_t);
    field = McMacRxCalBak_calEntry_f;

    for(i = 0; i <= walk_end_rx; i++)    
    {       
        entry_id = DRV_INS(txqm_id, i);
        cmd = DRV_IOR(table, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, entry_id, cmd, &macrx_cal));

        SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_tmm_mac_calendar_get_cal_entry(lchip, dp_id, dp_txqm_id, 
            cal_rx[i], &val_32));
        DRV_IOW_FIELD_NZ(lchip, table, field, &val_32, &macrx_cal, txqm_id, i);

        cmd = DRV_IOW(table, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, entry_id, cmd, &macrx_cal));
    }

    /* WalkerEnd */
    entry_id = DRV_INS(txqm_id, 0);
    cmd = DRV_IOR(McMacCalCtrl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, entry_id, cmd, &cal_ctrl));

    if(is_back_cal)
    {
        val_32 = walk_end_tx;
        DRV_IOW_FIELD_NZ(lchip, McMacCalCtrl_t, McMacCalCtrl_cfgWalkerEndBak_f, &val_32, &cal_ctrl, txqm_id, 0);
        val_32 = walk_end_rx;
        DRV_IOW_FIELD_NZ(lchip, McMacCalCtrl_t, McMacCalCtrl_cfgRxWalkerEndBak_f, &val_32, &cal_ctrl, txqm_id, 0);
    }
    else
    {
        val_32 = walk_end_tx;
        DRV_IOW_FIELD_NZ(lchip, McMacCalCtrl_t, McMacCalCtrl_cfgWalkerEnd_f, &val_32, &cal_ctrl, txqm_id, 0);
        val_32 = walk_end_rx;
        DRV_IOW_FIELD_NZ(lchip, McMacCalCtrl_t, McMacCalCtrl_cfgRxWalkerEnd_f, &val_32, &cal_ctrl, txqm_id, 0);
    }

    /* BankSel */
    val_32 = is_back_cal;
    DRV_IOW_FIELD_NZ(lchip, McMacCalCtrl_t, McMacCalCtrl_cfgRxCalEntrySel_f, &val_32, &cal_ctrl, txqm_id, 0);
    cmd = DRV_IOW(McMacCalCtrl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, entry_id, cmd, &cal_ctrl));
    DRV_IOW_FIELD_NZ(lchip, McMacCalCtrl_t, McMacCalCtrl_cfgCalEntrySel_f, &val_32, &cal_ctrl, txqm_id, 0);
    cmd = DRV_IOW(McMacCalCtrl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, entry_id, cmd, &cal_ctrl));

    /* MacTx/RxReady */
    /* when every things have been wrote to registor, set MacTxReady to 1*/
    val_32 = 1;
    DRV_IOW_FIELD_NZ(lchip, McMacCalCtrl_t, McMacCalCtrl_cfgMcMacTxReady_f, &val_32, &cal_ctrl, txqm_id, 0);
    val_32 = 1;
    DRV_IOW_FIELD_NZ(lchip, McMacCalCtrl_t, McMacCalCtrl_cfgMcMacRxReady_f, &val_32, &cal_ctrl, txqm_id, 0);

    cmd = DRV_IOW(McMacCalCtrl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, entry_id, cmd, &cal_ctrl));

    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "sys_tmm_set_mac_calendar end\n");

    return CTC_E_NONE;
}

/*Quad Group                     cfgQuadSgmacRxBufMode cfgQuadSgmacTxBufMode cfgSharedMiiMuxMode*/
/*1×40G/100G                     3'b010                3'b010                3'b010             */
/*2×50G                          3'b111                3'b111                3'b111             */
/*50G Port0 + 2*1G/10G/25G/none  3'b101                3'b101                3'b101             */
/*50G Port1 + 2*1G/10G/25G/none  3'b110                3'b110                3'b110             */
/*4×1G/10G/25G/none              3'b000                3'b000                3'b000             */
int32
_sys_tmm_cpumac_set_quad_group_mode(uint8 lchip)
{
    uint32 cmd      = 0;
    uint8  is_lg0   = FALSE;
    uint8  is_lg1   = FALSE;
    uint8  is_quad  = FALSE;
    uint32 mode_val = 0;
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;
    QuadSgmacCfg_m mac_cfg;
    SharedMiiCfg_m mii_cfg;

    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, SYS_TMM_CPUMAC_HSS_ID);
    SYS_CONDITION_RETURN((NULL == p_hss_vec), CTC_E_NONE);

    /*get quad value*/
    is_quad = ((CTC_CHIP_SERDES_XLG_MODE == p_hss_vec->serdes_info[0].mode) || 
              (CTC_CHIP_SERDES_CG_MODE == p_hss_vec->serdes_info[0].mode)) ? TRUE : FALSE;
    is_lg0  = (CTC_CHIP_SERDES_LG_MODE == p_hss_vec->serdes_info[0].mode) ? TRUE : FALSE;
    is_lg1  = (CTC_CHIP_SERDES_LG_MODE == p_hss_vec->serdes_info[2].mode) ? TRUE : FALSE;

    if(is_quad)
    {
        mode_val = 0x00000002; /*1×40G/100G*/
    }
    else
    {
        if(is_lg0 && is_lg1)
        {
            mode_val = 0x00000007; /*2×50G*/
        }
        else if(is_lg0)
        {
            mode_val = 0x00000005; /*50G Port0 + 2*1G/10G/25G/none*/
        }
        else if(is_lg1)
        {
            mode_val = 0x00000006; /*50G Port1 + 2*1G/10G/25G/none*/
        }
        else
        {
            mode_val = 0x00000000; /*4×1G/10G/25G/none*/
        }
    }

    /*QuadSgmacCfg.cfgQuadSgmacRxBufMode*/
    /*QuadSgmacCfg.cfgQuadSgmacTxBufMode*/
    cmd = DRV_IOR(QuadSgmacCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));
    DRV_IOW_FIELD(lchip, QuadSgmacCfg_t, QuadSgmacCfg_cfgQuadSgmacRxBufMode_f, &mode_val, &mac_cfg);
    DRV_IOW_FIELD(lchip, QuadSgmacCfg_t, QuadSgmacCfg_cfgQuadSgmacTxBufMode_f, &mode_val, &mac_cfg);
    cmd = DRV_IOW(QuadSgmacCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));

    /*SharedMiiCfg.cfgSharedMiiMuxMode*/
    cmd = DRV_IOR(SharedMiiCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_cfg));
    DRV_IOW_FIELD(lchip, SharedMiiCfg_t, SharedMiiCfg_cfgSharedMiiMuxMode_f, &mode_val, &mii_cfg);
    cmd = DRV_IOW(SharedMiiCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_cfg));

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_set_sgmii_config(uint8 lchip, uint16 lport)
{
    uint32 value               = 0;
    uint32 value1              = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint16 step                = 0;
    uint8  index               = 0;
    uint32 sgmac_idx           = 0;
    uint8  mii_idx             = 0;
    uint8  pcs_idx             = 0;
    uint8  speed_mode          = 0;
    Sgmac0RxCfg_m              mac_rx_cfg;
    Sgmac0TxCfg_m              mac_tx_cfg;
    SharedMii0Cfg_m            mii_per_cfg;
    SharedPcsCfg_m             shared_pcs_cfg;
    SharedPcsSgmii0Cfg_m       sgmii_cfg;
    SharedPcsFx0Cfg_m          pcs_fx_cfg;
    SharedPcsSerdes0Cfg_m      pcs_serdes_cfg;
    SharedMiiCfg_m             mii_cfg;
    SharedPcsDsfCfg_m          dsf_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);

    speed_mode = port_attr->speed_mode;
    mii_idx    = port_attr->mii_idx;
    pcs_idx    = port_attr->pcs_idx;
    sgmac_idx  = SYS_TMM_CPUMAC_GET_MAC_HW_IDX(port_attr->mac_id);
    
    /* cfg Quad sgmac  move to _sys_tmm_cpumac_set_quad_group_mode*/

    /* cfg sgmac Rx/Tx*/
    step = Sgmac1RxCfg_t - Sgmac0RxCfg_t;
    tbl_id = Sgmac0RxCfg_t + sgmac_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));
    value = (0 == sgmac_idx) ? 2 : ((2 == sgmac_idx) ? 1 : 0);
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f,    &value, &mac_rx_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    step = Sgmac1TxCfg_t - Sgmac0TxCfg_t;
    tbl_id = Sgmac0TxCfg_t + sgmac_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));
    value = 3;
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f,   &value, &mac_tx_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxWaitCaptureTs_f, &value, &mac_tx_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxKeepTsEn_f, &value, &mac_tx_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));

    /* cfg Share Mii*/
    tbl_id = SharedMiiCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode1_f,       &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode0_f,       &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiXauiMode_f,         &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiQsgmiiMode_f,       &value, &mii_cfg);
    /*SharedMiiCfg_cfgSharedMiiMuxMode_f move to _sys_tmm_cpumac_set_quad_group_mode*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiTxIpgDelInterval_f, &value, &mii_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    /* cfg per Share Mii*/
    value = 0;
    step = SharedMii1Cfg_t - SharedMii0Cfg_t;
    tbl_id = SharedMii0Cfg_t + mii_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFXMode0_f,       &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiUsxgmiiEn0_f,    &value, &mii_per_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxEvenIgnore0_f, &value, &mii_per_cfg);

    switch(speed_mode)
    {
        case CTC_PORT_SPEED_2G5:
            value = 3;
            value1 = 0;
            break;
        case CTC_PORT_SPEED_1G:
            value = 2;
            value1 = 0;
            break;
        case CTC_PORT_SPEED_100M:
            value = 1;
            value1 = 9;
            break;
        case CTC_PORT_SPEED_10M:
            value = 0;
            value1 = 99;
            break;
        default:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"error port speed mode: %d \n", speed_mode);
            return CTC_E_INVALID_PARAM;
    }
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiSpeed0_f,          &value,  &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f, &value1, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,    &value1, &mii_per_cfg);

    value  = 1;
    value1 = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f, &value,  &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f, &value1, &mii_per_cfg);
    if (CTC_PORT_SPEED_2G5 == speed_mode)
    {
        value = (500 == p_usw_datapath_master[lchip]->core_plla) ? 11 : 6;
    }
    else
    {
        value = 0x4;
    }
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAFullThrd0_f,       &value, &mii_per_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      &value, &mii_per_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxSampleSlot0_f,      &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateSlot0_f,   &value, &mii_per_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFaultMaskLinkEn0_f,   &value, &mii_per_cfg);
    /*link filter*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f,    &value, &mii_per_cfg);
    value = 0x60;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f, &value, &mii_per_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    /* additional integrity config */
    tbl_id = SharedPcsDsfCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));
    value = 31;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsDsfCfg_cfgDsfDepth0_f, &value, &dsf_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));

    /* cfg SharedPcsCfg */
    value = 0;
    tbl_id = SharedPcsCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_cgMode_f,                    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode0_f         + pcs_idx, &value, &shared_pcs_cfg);
    if (pcs_idx <= 1)
    {
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode0_f,               &value, &shared_pcs_cfg);
    }
    else
    {
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode1_f,               &value, &shared_pcs_cfg);
    }
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_rxauiMode_f,                 &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xauiMode_f,                  &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xlgMode_f,                   &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode0_f       + pcs_idx, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn0_f + pcs_idx, &value, &shared_pcs_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx0_f    + pcs_idx, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx0_f    + pcs_idx, &value, &shared_pcs_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    value = 80;
    step = SharedPcsSerdes1Cfg_t - SharedPcsSerdes0Cfg_t;
    tbl_id = SharedPcsSerdes0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSerdes0Cfg_rxPopCntCfg0_f,        &value, &pcs_serdes_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));

    /*parallelizing check*/
    step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
    tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,  &value, &sgmii_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));

    /*additional 100BaseFx config 0*/
    value = 0;
    step = SharedPcsFx1Cfg_t - SharedPcsFx0Cfg_t;
    tbl_id = SharedPcsFx0Cfg_t + pcs_idx * step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxTxForceLinkStatus0_f, &value, &pcs_fx_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxLinkEnable0_f,        &value, &pcs_fx_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_xfi_config(uint8 lchip, uint16 lport)
{
    uint32 value               = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 step                = 0;
    uint8  index               = 0;
    uint32 sgmac_idx           = 0;
    uint8  mii_idx             = 0;
    uint32 pcs_idx             = 0;
    Sgmac0RxCfg_m              mac_rx_cfg;
    Sgmac0TxCfg_m              mac_tx_cfg;
    SharedMii0Cfg_m            mii_per_cfg;
    SharedPcsCfg_m             shared_pcs_cfg;
    SharedPcsSgmii0Cfg_m       sgmii_cfg;
    SharedPcsFx0Cfg_m          pcs_fx_cfg;
    SharedPcsSerdes0Cfg_m      pcs_serdes_cfg;
    SharedMiiCfg_m             mii_cfg;
    SharedPcsDsfCfg_m          dsf_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);

    mii_idx    = port_attr->mii_idx;
    pcs_idx    = port_attr->pcs_idx;
    sgmac_idx  = SYS_TMM_CPUMAC_GET_MAC_HW_IDX(port_attr->mac_id);

    /* cfg Quad sgmac  move to _sys_tmm_cpumac_set_quad_group_mode*/

    /* cfg sgmac Rx/Tx*/
    value = (0 == sgmac_idx) ? 2 : ((2 == sgmac_idx) ? 1 : 0);
    step = Sgmac1RxCfg_t - Sgmac0RxCfg_t;
    tbl_id = Sgmac0RxCfg_t + sgmac_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, &value, &mac_rx_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    step = Sgmac1TxCfg_t - Sgmac0TxCfg_t;
    tbl_id = Sgmac0TxCfg_t + sgmac_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, &value, &mac_tx_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxKeepTsEn_f, &value, &mac_tx_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));

    /* cfg Share Mii*/
    tbl_id = SharedMiiCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode1_f,          &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode0_f,          &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiXauiMode_f,            &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiQsgmiiMode_f,          &value, &mii_cfg);
    /*SharedMiiCfg_cfgSharedMiiMuxMode_f move to _sys_tmm_cpumac_set_quad_group_mode*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiTxIpgDelInterval_f,    &value, &mii_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    /* cfg per Share Mii*/
    value = 0;
    step = SharedMii1Cfg_t - SharedMii0Cfg_t;
    tbl_id = SharedMii0Cfg_t + mii_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFXMode0_f,            &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiUsxgmiiEn0_f,         &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxEvenIgnore0_f,      &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f,    &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,       &value, &mii_per_cfg);

    value = 5;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiSpeed0_f,             &value, &mii_per_cfg);
    value = 17;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f,    &value, &mii_per_cfg);
    value = 16;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f,    &value, &mii_per_cfg);
    value = 0xb;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAFullThrd0_f,       &value, &mii_per_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      &value, &mii_per_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxSampleSlot0_f,      &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateSlot0_f,   &value, &mii_per_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFaultMaskLinkEn0_f,   &value, &mii_per_cfg);
    /*config link filter*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f,    &value, &mii_per_cfg);
    value = 0x60;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f, &value, &mii_per_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    /* additional integrity config */
    tbl_id = SharedPcsDsfCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));
    value = 31;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsDsfCfg_cfgDsfDepth0_f, &value, &dsf_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));

    /* cfg SharedPcsCfg */
    value = 0;
    tbl_id = SharedPcsCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_cgMode_f,                    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode0_f         + pcs_idx, &value, &shared_pcs_cfg);
    if (pcs_idx <= 1)
    {
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode0_f,               &value, &shared_pcs_cfg);
    }
    else
    {
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode1_f,               &value, &shared_pcs_cfg);
    }
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_rxauiMode_f,                 &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx0_f    + pcs_idx, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx0_f    + pcs_idx, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xauiMode_f,                  &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xlgMode_f,                   &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode0_f       + pcs_idx, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn0_f + pcs_idx, &value, &shared_pcs_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    value = 80;
    step = SharedPcsSerdes1Cfg_t - SharedPcsSerdes0Cfg_t;
    tbl_id = SharedPcsSerdes0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSerdes0Cfg_rxPopCntCfg0_f,        &value, &pcs_serdes_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));

    /*parallelizing check disable*/
    value = 0;
    step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
    tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_anParallelDetectEn0_f, &value, &sgmii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,  &value, &sgmii_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));

    /*additional 100BaseFx config 0*/
    value = 0;
    step = SharedPcsFx1Cfg_t - SharedPcsFx0Cfg_t;
    tbl_id = SharedPcsFx0Cfg_t + pcs_idx * step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxTxForceLinkStatus0_f, &value, &pcs_fx_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxLinkEnable0_f,        &value, &pcs_fx_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_xlg_config(uint8 lchip, uint16 lport)
{
    uint32 value               = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint16 step                = 0;
    uint8  index               = 0;
    uint32 sgmac_idx           = 0;
    uint8  mii_idx             = 0;
    uint8  pcs_idx             = 0;
    uint8  cnt                 = 0;
    Sgmac0RxCfg_m              mac_rx_cfg;
    Sgmac0TxCfg_m              mac_tx_cfg;
    SharedMii0Cfg_m            mii_per_cfg;
    SharedPcsCfg_m             shared_pcs_cfg;
    SharedPcsSgmii0Cfg_m       sgmii_cfg;
    SharedPcsFx0Cfg_m          pcs_fx_cfg;
    SharedPcsSerdes0Cfg_m      pcs_serdes_cfg;
    SharedMiiCfg_m             mii_cfg;
    SharedPcsDsfCfg_m          dsf_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);

    mii_idx    = port_attr->mii_idx;
    pcs_idx    = port_attr->pcs_idx;
    sgmac_idx  = SYS_TMM_CPUMAC_GET_MAC_HW_IDX(port_attr->mac_id);
    
    /* cfg Quad sgmac  move to _sys_tmm_cpumac_set_quad_group_mode*/

    /* cfg sgmac Rx/Tx*/
    value = 1;

    tbl_id = Sgmac0RxCfg_t + sgmac_idx;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, &value, &mac_rx_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    tbl_id = Sgmac0TxCfg_t + sgmac_idx;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, &value, &mac_tx_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxKeepTsEn_f, &value, &mac_tx_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));

    /* cfg Share Mii*/
    tbl_id = SharedMiiCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode1_f,       &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode0_f,       &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiXauiMode_f,         &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiQsgmiiMode_f,       &value, &mii_cfg);
    /*SharedMiiCfg_cfgSharedMiiMuxMode_f move to _sys_tmm_cpumac_set_quad_group_mode*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiTxIpgDelInterval_f, &value, &mii_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    /* cfg per Share Mii*/
    tbl_id = SharedMii0Cfg_t + mii_idx;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFXMode0_f,            &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiUsxgmiiEn0_f,         &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxEvenIgnore0_f,      &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f,    &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,       &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxSampleSlot0_f,      &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateSlot0_f,   &value, &mii_per_cfg);
    value = 8;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiSpeed0_f,             &value, &mii_per_cfg);
    value = 0x3FFF;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      &value, &mii_per_cfg);
    value = 16;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f,    &value, &mii_per_cfg);
    value = 17;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f,    &value, &mii_per_cfg);
    value = 0xb;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAFullThrd0_f,       &value, &mii_per_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFaultMaskLinkEn0_f,   &value, &mii_per_cfg);
    /*config link filter*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f,    &value, &mii_per_cfg);
    value = 0x60;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f, &value, &mii_per_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    /* additional integrity config */
    tbl_id = SharedPcsDsfCfg_t + pcs_idx;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));
    value = 31;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsDsfCfg_cfgDsfDepth0_f, &value, &dsf_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));

    /* cfg SharedPcsCfg */
    value = 0;
    tbl_id = SharedPcsCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_cgMode_f,          &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode0_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode1_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode2_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode3_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode0_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode1_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_rxauiMode_f,       &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx0_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx1_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx2_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx3_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx0_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx1_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx2_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx3_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xauiMode_f,        &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode0_f,       &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode1_f,       &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode2_f,       &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode3_f,       &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn0_f, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn1_f, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn2_f, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn3_f, &value, &shared_pcs_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xlgMode_f,         &value, &shared_pcs_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    tbl_id = SharedPcsSerdes0Cfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));
    value = 80;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSerdes0Cfg_rxPopCntCfg0_f, &value, &pcs_serdes_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));

    /*parallelizing check disable*/
    value = 0;
    step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
    tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_anParallelDetectEn0_f, &value, &sgmii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,  &value, &sgmii_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));

    /*additional 100BaseFx config 0*/
    value = 0;
    step = SharedPcsFx1Cfg_t - SharedPcsFx0Cfg_t;
    for(cnt = 0; cnt < 4; cnt++)
    {
        tbl_id = SharedPcsFx0Cfg_t + cnt * step;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxTxForceLinkStatus0_f, &value, &pcs_fx_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxLinkEnable0_f,        &value, &pcs_fx_cfg);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_xxvg_config(uint8 lchip, uint16 lport)
{
    uint32 value               = 0;
    uint32 tmp_val             = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 step                = 0;
    uint8  index               = 0;
    uint32 sgmac_idx           = 0;
    uint8  mii_idx             = 0;
    uint8  pcs_idx             = 0;
    Sgmac0RxCfg_m              mac_rx_cfg;
    Sgmac0TxCfg_m              mac_tx_cfg;
    SharedMii0Cfg_m            mii_per_cfg;
    SharedPcsCfg_m             shared_pcs_cfg;
    SharedPcsSgmii0Cfg_m       sgmii_cfg;
    SharedPcsFx0Cfg_m          pcs_fx_cfg;
    SharedPcsSerdes0Cfg_m      pcs_serdes_cfg;
    SharedMiiCfg_m             mii_cfg;
    QuadSgmacCfg_m             mac_cfg;
    SharedPcsDsfCfg_m          dsf_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);

    mii_idx    = port_attr->mii_idx;
    pcs_idx    = port_attr->pcs_idx;
    sgmac_idx  = SYS_TMM_CPUMAC_GET_MAC_HW_IDX(port_attr->mac_id);
    
    /* cfg Quad sgmac*/
    tbl_id = QuadSgmacCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));

    /* to support 25/50G mix config inner qm */
    DRV_IOR_FIELD(lchip, tbl_id, QuadSgmacCfg_cfgQuadSgmacRxBufMode_f, &tmp_val, &mac_cfg);
    value = ~(sgmac_idx < 2 ? 1 : 2);
    value &= tmp_val;
    DRV_IOW_FIELD(lchip, tbl_id, QuadSgmacCfg_cfgQuadSgmacRxBufMode_f, &value, &mac_cfg);

    DRV_IOR_FIELD(lchip, tbl_id, QuadSgmacCfg_cfgQuadSgmacTxBufMode_f, &tmp_val, &mac_cfg);
    value = ~(sgmac_idx < 2 ? 1 : 2);
    value &= tmp_val;
    DRV_IOW_FIELD(lchip, tbl_id, QuadSgmacCfg_cfgQuadSgmacTxBufMode_f, &value, &mac_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));

    /* cfg sgmac Rx/Tx*/
    value = (0 == sgmac_idx) ? 2 : ((2 == sgmac_idx) ? 1 : 0);
    step = Sgmac1RxCfg_t - Sgmac0RxCfg_t;
    tbl_id = Sgmac0RxCfg_t + sgmac_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, &value, &mac_rx_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    step = Sgmac1TxCfg_t - Sgmac0TxCfg_t;
    tbl_id = Sgmac0TxCfg_t + sgmac_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, &value, &mac_tx_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxKeepTsEn_f, &value, &mac_tx_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));

    /* cfg Share Mii*/
    tbl_id = SharedMiiCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode1_f,          &value,   &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode0_f,          &value,   &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiXauiMode_f,            &value,   &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiQsgmiiMode_f,          &value,   &mii_cfg);
    /*SharedMiiCfg_cfgSharedMiiMuxMode_f move to _sys_tmm_cpumac_set_quad_group_mode*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiTxIpgDelInterval_f,    &value,   &mii_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    /* cfg Share Mii*/
    value = 0;
    step = SharedMii1Cfg_t - SharedMii0Cfg_t;
    tbl_id = SharedMii0Cfg_t + mii_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFXMode0_f,            &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiUsxgmiiEn0_f,         &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxEvenIgnore0_f,      &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f,    &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateSlot0_f,   &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,       &value, &mii_per_cfg);
    value = 7;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiSpeed0_f,             &value, &mii_per_cfg);

    value = 32;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f,    &value, &mii_per_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f,    &value, &mii_per_cfg);
    value = 0xb;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAFullThrd0_f,       &value, &mii_per_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      &value, &mii_per_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFaultMaskLinkEn0_f,   &value, &mii_per_cfg);
    /*config link filter*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f,    &value, &mii_per_cfg);
    value = 0x60;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f, &value, &mii_per_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    /* additional integrity config */
    tbl_id = SharedPcsDsfCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));
    value = 31;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsDsfCfg_cfgDsfDepth0_f, &value, &dsf_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));

    /* cfg SharedPcsCfg */
    value = 0;
    tbl_id = SharedPcsCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_cgMode_f,                    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode0_f + pcs_idx,         &value, &shared_pcs_cfg);
    if (pcs_idx <= 1)
    {
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode0_f,               &value, &shared_pcs_cfg);
    }
    else
    {
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode1_f,               &value, &shared_pcs_cfg);
    }
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_rxauiMode_f,                 &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx0_f    + pcs_idx, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx0_f    + pcs_idx, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xauiMode_f,                  &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xlgMode_f,                   &value, &shared_pcs_cfg);

    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode0_f       + pcs_idx, &value, &shared_pcs_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn0_f + pcs_idx, &value, &shared_pcs_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    step = SharedPcsSerdes1Cfg_t - SharedPcsSerdes0Cfg_t;
    tbl_id = SharedPcsSerdes0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));
    value = 100;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSerdes0Cfg_rxPopCntCfg0_f, &value, &pcs_serdes_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));

    /*parallelizing check disable*/
    value = 0;
    step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
    tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_anParallelDetectEn0_f,  &value, &sgmii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,   &value, &sgmii_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));

    /*additional 100BaseFx config 0*/
    value = 0;
    step = SharedPcsFx1Cfg_t - SharedPcsFx0Cfg_t;
    tbl_id = SharedPcsFx0Cfg_t + pcs_idx * step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxTxForceLinkStatus0_f, &value, &pcs_fx_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxLinkEnable0_f,        &value, &pcs_fx_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_lg_per_sharedmii_cfg(uint8 lchip, uint32 tbl_id)
{
    uint32 value      = 0;
    uint32 cmd        = 0;
    uint8  index      = 0;
    SharedMii0Cfg_m   mii_per_cfg;

    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFXMode0_f, &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiUsxgmiiEn0_f, &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxEvenIgnore0_f, &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f, &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateSlot0_f, &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxSampleCnt0_f, &value, &mii_per_cfg);
    value = 9;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiSpeed0_f, &value, &mii_per_cfg);
    value = 0x3FFF;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAmInterval0_f, &value, &mii_per_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFaultMaskLinkEn0_f, &value, &mii_per_cfg);
    value = 16;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f, &value, &mii_per_cfg);
    value = 17;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f, &value, &mii_per_cfg);
    value = 0xb;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAFullThrd0_f, &value, &mii_per_cfg);
    /*config link filter*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f, &value, &mii_per_cfg);
    value = 0x60;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f, &value, &mii_per_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));
    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_lg_config(uint8 lchip, uint16 lport)
{
    uint32 value               = 0;
    uint32 tmp_val             = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 step                = 0;
    uint8  index               = 0;
    uint32 sgmac_idx           = 0;
    uint32 mii_idx             = 0;
    uint8  pcs_idx             = 0;
    uint8  lg_index            = 0;
    uint8  cnt                 = 0;
    Sgmac0RxCfg_m              mac_rx_cfg;
    Sgmac0TxCfg_m              mac_tx_cfg;
    SharedPcsCfg_m             shared_pcs_cfg;
    SharedPcsSgmii0Cfg_m       sgmii_cfg;
    SharedPcsFx0Cfg_m          pcs_fx_cfg;
    SharedPcsSerdes0Cfg_m      pcs_serdes_cfg;
    SharedMiiCfg_m             mii_cfg;
    SharedPcsDsfCfg_m          dsf_cfg;
    QuadSgmacCfg_m             mac_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);

    mii_idx    = port_attr->mii_idx;
    pcs_idx    = port_attr->pcs_idx;
    sgmac_idx  = SYS_TMM_CPUMAC_GET_MAC_HW_IDX(port_attr->mac_id);

    /* cfg Quad sgmac*/
    tbl_id = QuadSgmacCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));

    /* to support 25/50G mix config inner qm */
    DRV_IOR_FIELD(lchip, tbl_id, QuadSgmacCfg_cfgQuadSgmacRxBufMode_f, &tmp_val, &mac_cfg);
    value = sgmac_idx < 2 ? 5 : 6;
    value |= tmp_val;
    DRV_IOW_FIELD(lchip, tbl_id, QuadSgmacCfg_cfgQuadSgmacRxBufMode_f, &value,   &mac_cfg);

    DRV_IOR_FIELD(lchip, tbl_id, QuadSgmacCfg_cfgQuadSgmacTxBufMode_f, &tmp_val, &mac_cfg);
    value = sgmac_idx < 2 ? 5 : 6;
    value |= tmp_val;
    DRV_IOW_FIELD(lchip, tbl_id, QuadSgmacCfg_cfgQuadSgmacTxBufMode_f, &value,   &mac_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));


    /* cfg sgmac Rx/Tx*/
    value = (sgmac_idx == 0) ? 1 : 0;
    step = Sgmac1RxCfg_t - Sgmac0RxCfg_t;
    tbl_id = Sgmac0RxCfg_t + sgmac_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, &value, &mac_rx_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    step = Sgmac1TxCfg_t - Sgmac0TxCfg_t;
    tbl_id = Sgmac0TxCfg_t + sgmac_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, &value, &mac_tx_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxKeepTsEn_f, &value, &mac_tx_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));

    /* cfg Share Mii*/
    tbl_id = SharedMiiCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode1_f,       &value,   &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode0_f,       &value,   &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiXauiMode_f,         &value,   &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiQsgmiiMode_f,       &value,   &mii_cfg);
    /*SharedMiiCfg_cfgSharedMiiMuxMode_f move to _sys_tmm_cpumac_set_quad_group_mode*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiTxIpgDelInterval_f, &value,   &mii_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    /* cfg per Share Mii*/
    step = SharedMii1Cfg_t - SharedMii0Cfg_t;
    tbl_id = SharedMii0Cfg_t + mii_idx*step;
    CTC_ERROR_RETURN(_sys_tmm_cpumac_set_lg_per_sharedmii_cfg(lchip, tbl_id));
    tbl_id = SharedMii0Cfg_t + (mii_idx+1)*step;
    CTC_ERROR_RETURN(_sys_tmm_cpumac_set_lg_per_sharedmii_cfg(lchip, tbl_id));

    /* cfg SharedPcsCfg */
    tbl_id = SharedPcsCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    value = 0;
    if (pcs_idx <= 1)
    {
        lg_index = 0;
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode0_f,      &value, &shared_pcs_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode1_f,      &value, &shared_pcs_cfg);

        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx0_f, &value, &shared_pcs_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx1_f, &value, &shared_pcs_cfg);

        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx0_f, &value, &shared_pcs_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx1_f, &value, &shared_pcs_cfg);

        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode0_f,    &value, &shared_pcs_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode1_f,    &value, &shared_pcs_cfg);
    }
    else
    {
        lg_index = 1;
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode2_f,      &value, &shared_pcs_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode3_f,      &value, &shared_pcs_cfg);

        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx2_f, &value, &shared_pcs_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx3_f, &value, &shared_pcs_cfg);

        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx2_f, &value, &shared_pcs_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx3_f, &value, &shared_pcs_cfg);

        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode2_f,    &value, &shared_pcs_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode3_f,    &value, &shared_pcs_cfg);
    }

    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_cgMode_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_rxauiMode_f, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xauiMode_f,  &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xlgMode_f,   &value, &shared_pcs_cfg);

    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode0_f + lg_index,        &value, &shared_pcs_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn0_f + pcs_idx, &value, &shared_pcs_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    /* additional integrity config */
    tbl_id = SharedPcsDsfCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));
    value = 31;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsDsfCfg_cfgDsfDepth0_f, &value, &dsf_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));

    step = SharedPcsSerdes1Cfg_t - SharedPcsSerdes0Cfg_t;
    tbl_id = SharedPcsSerdes0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));
    value = 100;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSerdes0Cfg_rxPopCntCfg0_f, &value, &pcs_serdes_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));

    /*parallelizing check disable*/
    value = 0;
    step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
    tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_anParallelDetectEn0_f, &value, &sgmii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,  &value, &sgmii_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));

    /*additional 100BaseFx config 0*/
    value = 0;
    step = SharedPcsFx1Cfg_t - SharedPcsFx0Cfg_t;
    for(cnt = 0; cnt < 2; cnt++)
    {
        if(pcs_idx != 0)
        {
            cnt += 2;
        }
        tbl_id = SharedPcsFx0Cfg_t + (cnt + pcs_idx) * step;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxTxForceLinkStatus0_f, &value, &pcs_fx_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxLinkEnable0_f,        &value, &pcs_fx_cfg);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_cg_config(uint8 lchip, uint16 lport)
{
    uint32 value               = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint16 step                = 0;
    uint8  index               = 0;
    uint32 sgmac_idx           = 0;
    uint8  pcs_idx             = 0;
    uint8  cnt                 = 0;
    Sgmac0RxCfg_m              mac_rx_cfg;
    Sgmac0TxCfg_m              mac_tx_cfg;
    SharedMii0Cfg_m            mii_per_cfg;
    SharedPcsCfg_m             shared_pcs_cfg;
    SharedPcsSgmii0Cfg_m       sgmii_cfg;
    SharedPcsFx0Cfg_m          pcs_fx_cfg;
    SharedPcsSerdes0Cfg_m      pcs_serdes_cfg;
    SharedMiiCfg_m             mii_cfg;
    SharedPcsDsfCfg_m          dsf_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);

    pcs_idx    = port_attr->pcs_idx;
    sgmac_idx  = SYS_TMM_CPUMAC_GET_MAC_HW_IDX(port_attr->mac_id);
    
    /* cfg Quad sgmac  move to _sys_tmm_cpumac_set_quad_group_mode*/

    /* cfg sgmac Rx/Tx*/
    value = 0;
    tbl_id = Sgmac0RxCfg_t + sgmac_idx;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0RxCfg_cfgSgmac0RxInputWidth_f, &value, &mac_rx_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_cfg));

    tbl_id = Sgmac0TxCfg_t + sgmac_idx;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxOutputWidth_f, &value, &mac_tx_cfg);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Sgmac0TxCfg_cfgSgmac0TxKeepTsEn_f, &value, &mac_tx_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));

    /* cfg Share Mii*/
    tbl_id = SharedMiiCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode1_f,       &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiRXauiMode0_f,       &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiXauiMode_f,         &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiQsgmiiMode_f,       &value, &mii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMiiCfg_cfgMiiTxIpgDelInterval_f, &value, &mii_cfg);
    /*SharedMiiCfg_cfgSharedMiiMuxMode_f move to _sys_tmm_cpumac_set_quad_group_mode*/
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_cfg));

    /* cfg per Share Mii*/
    value = 0;
    tbl_id = SharedMii0Cfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFXMode0_f,            &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiUsxgmiiEn0_f,         &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxEvenIgnore0_f,      &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateCnt0_f,    &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxReplicateSlot0_f,   &value, &mii_per_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxSampleCnt0_f,       &value, &mii_per_cfg);

    value = 10;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiSpeed0_f,             &value, &mii_per_cfg);
    value = 0x3FFF;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAmInterval0_f,      &value, &mii_per_cfg);
    value = 32;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceDecValue0_f,    &value, &mii_per_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxPaceIncValue0_f,    &value, &mii_per_cfg);
    value = 0xb;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiTxAFullThrd0_f,       &value, &mii_per_cfg);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiFaultMaskLinkEn0_f,   &value, &mii_per_cfg);
    /*config link filter*/
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f,    &value, &mii_per_cfg);
    value = 0x60;
    DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f, &value, &mii_per_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

    /* cfg SharedPcsCfg */
    value = 0;
    tbl_id = SharedPcsCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode0_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode1_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode2_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_fxMode3_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode0_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_lgMode1_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_rxauiMode_f,       &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx0_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx1_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx2_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeRx3_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx0_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx1_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx2_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_sgmiiModeTx3_f,    &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn0_f, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn1_f, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn2_f, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_unidirectionEn3_f, &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xauiMode_f,        &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xlgMode_f,         &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode0_f,       &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode1_f,       &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode2_f,       &value, &shared_pcs_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_xxvgMode3_f,       &value, &shared_pcs_cfg);

    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsCfg_cgMode_f,          &value, &shared_pcs_cfg);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &shared_pcs_cfg));

    /* additional integrity config */
    tbl_id = SharedPcsDsfCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));
    value = 31;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsDsfCfg_cfgDsfDepth0_f, &value, &dsf_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &dsf_cfg));

    step = SharedPcsSerdes1Cfg_t - SharedPcsSerdes0Cfg_t;
    tbl_id = SharedPcsSerdes0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));
    value = 100;
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSerdes0Cfg_rxPopCntCfg0_f, &value, &pcs_serdes_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_serdes_cfg));

    /*parallelizing check disable*/
    value = 0;
    step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
    tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_anParallelDetectEn0_f, &value, &sgmii_cfg);
    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSgmii0Cfg_ignoreLinkFailure0_f,  &value, &sgmii_cfg);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_cfg));

    /*additional 100BaseFx config 0*/
    value = 0;
    step = SharedPcsFx1Cfg_t - SharedPcsFx0Cfg_t;
    for(cnt = 0; cnt < 4; cnt++)
    {
        tbl_id = SharedPcsFx0Cfg_t + pcs_idx * step;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxTxForceLinkStatus0_f, &value, &pcs_fx_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedPcsFx0Cfg_cfgFxLinkEnable0_f,        &value, &pcs_fx_cfg);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fx_cfg));
    }

    return CTC_E_NONE;
}

 int32
_sys_tmm_cpumac_set_mac_config(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr)
{
    /*CTC_ERROR_RETURN(_sys_tsingma_mac_set_sgmac_pre_config(lchip, lport));*/
#if !defined(EMULATION_ENV) || defined(PCS_IMG)
    switch (port_attr->pcs_mode)
    {
        case CTC_CHIP_SERDES_SGMII_MODE:
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_sgmii_config(lchip, lport));
            break;
        case CTC_CHIP_SERDES_XFI_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_xfi_config(lchip, lport));
            break;
        case CTC_CHIP_SERDES_XLG_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_xlg_config(lchip, lport));
            break;
        case CTC_CHIP_SERDES_XXVG_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_xxvg_config(lchip, lport));
            break;
        case CTC_CHIP_SERDES_LG_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_lg_config(lchip, lport));
            break;
        case CTC_CHIP_SERDES_CG_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_cg_config(lchip, lport));
            break;
        default:
            break;
    }
    /*quad group public config*/
    CTC_ERROR_RETURN(_sys_tmm_cpumac_set_quad_group_mode(lchip));
#endif

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_additional_cfg(uint8 lchip, uint8 is_init, sys_tmm_ds_target_attr_t *p_ds_attr)
{
    uint8  lane_id;
    uint8  cpumac_skip  = TRUE;
    uint32 cmd          = 0;
    uint32 value        = 0;
    CpuMacHssQuadCfg_m  hss_cfg;
    SharedPcsReserved_m pcs_rsv;
    SharedPcsSerdes0Cfg_m fs_cfg;
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, SYS_TMM_CPUMAC_HSS_ID);
    SYS_CONDITION_RETURN((NULL == p_hss_vec), CTC_E_NONE);

    if(is_init)
    {
        for(lane_id = 0; lane_id < SYS_TMM_CPUMAC_SERDES_NUM; lane_id++)
        {
            if((!SYS_TMM_IS_MODE_NONE(p_hss_vec->serdes_info[lane_id].mode)) || (0 != p_hss_vec->serdes_info[lane_id].is_dyn))
            {
                cpumac_skip = FALSE;
                break;
            }
        }
    }
    else
    {
        SYS_CONDITION_RETURN((NULL == p_ds_attr), CTC_E_INVALID_PTR);
        if(SYS_TMM_CPUMAC_HSS_ID == SYS_TMM_MAP_SERDES_TO_HSS_IDX(p_ds_attr->serdes_list[0].logic_serdes_id))
        {
            cpumac_skip = FALSE;
        }
    }
    SYS_CONDITION_RETURN(cpumac_skip, CTC_E_NONE);

    cmd = DRV_IOR(CpuMacHssQuadCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &hss_cfg));
    value = 3;
    DRV_IOW_FIELD(lchip, CpuMacHssQuadCfg_t, CpuMacHssQuadCfg_cfgHssQuad_0_cfgHssRxReadyGate_f, &value, &hss_cfg);
    DRV_IOW_FIELD(lchip, CpuMacHssQuadCfg_t, CpuMacHssQuadCfg_cfgHssQuad_1_cfgHssRxReadyGate_f, &value, &hss_cfg);
    DRV_IOW_FIELD(lchip, CpuMacHssQuadCfg_t, CpuMacHssQuadCfg_cfgHssQuad_2_cfgHssRxReadyGate_f, &value, &hss_cfg);
    DRV_IOW_FIELD(lchip, CpuMacHssQuadCfg_t, CpuMacHssQuadCfg_cfgHssQuad_3_cfgHssRxReadyGate_f, &value, &hss_cfg);
    cmd = DRV_IOW(CpuMacHssQuadCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &hss_cfg));

    if(is_init)
    {
        value = 1;

        /*lane 3 forceSignalDetect keep same as SharedPcsReserved.reserved*/
        cmd = DRV_IOR(SharedPcsSerdes3Cfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fs_cfg));
        DRV_IOW_FIELD(lchip, SharedPcsSerdes3Cfg_t, SharedPcsSerdes0Cfg_forceSignalDetect0_f, &value, &fs_cfg);
        cmd = DRV_IOW(SharedPcsSerdes3Cfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fs_cfg));

        cmd = DRV_IOR(SharedPcsReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rsv));
        DRV_IOW_FIELD(lchip, SharedPcsReserved_t, SharedPcsReserved_reserved_f, &value, &pcs_rsv);
        cmd = DRV_IOW(SharedPcsReserved_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rsv));
        
        /*CPUMAC  20T clock toggle*/
        for(lane_id = 0; lane_id < SYS_TMM_CPUMAC_SERDES_NUM; lane_id++)
        {
            CTC_ERROR_RETURN(_sys_tmm_cpumac_sgmii_20T_clock_toggle(lchip, p_usw_datapath_master[lchip]->cpumac_map[lane_id].lport));
        }
    }
    else
    {
        /*CPUMAC  20T clock toggle*/
        for(lane_id = 0; lane_id < p_ds_attr->lport_num; lane_id++)
        {
            CTC_ERROR_RETURN(_sys_tmm_cpumac_sgmii_20T_clock_toggle(lchip, p_ds_attr->lport_list[lane_id].lport));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_mac_rx_en(uint8 lchip, uint16 mac_id, uint32 enable)
{
    uint32 factor    = 0;/* 0..39 per txqm */
    uint32 step      = 0;
    uint32 tbl_id    = 0;
    uint32 fld_id    = 0;
    uint32 index     = 0;
    uint32 cmd       = 0;
    uint32 value     = (0 == enable) ? 0 : 1;
    McMacMacRxCfg_m  mac_rx;
    Sgmac0RxCfg_m    cpumac_rx;

    SYS_CONDITION_RETURN(SYS_TMM_USELESS_ID16 == mac_id, CTC_E_NONE);

    if(SYS_TMM_MAX_MAC_NUM > mac_id) /*NW*/
    {
        index  = DRV_INS(SYS_TMM_GET_TXQM_BY_MACID(mac_id), 0);
        step   = McMacMacRxCfg_cfgMcMacMacRx_1_cfgMcMacRxPktEn_f - McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxPktEn_f;
        factor = TXQM_INNER_MAC_ID(mac_id);
        tbl_id = McMacMacRxCfg_t;
        fld_id = McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxPktEn_f + step*factor;

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx));
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mac_rx);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx));
    }
    else /*cpumac*/
    {
        index  = 0;
        step   = Sgmac1RxCfg_t - Sgmac0RxCfg_t;
        factor = mac_id % 4;
        tbl_id = Sgmac0RxCfg_t + step * factor;
        fld_id = Sgmac0RxCfg_cfgSgmac0RxPktEn_f;

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_rx));
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &cpumac_rx);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_rx));
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_mac_rx_en(uint8 lchip, uint16 mac_id, uint32* p_enable)
{
    uint32 factor    = 0;/* 0..39 per txqm */
    uint32 step      = 0;
    uint32 tbl_id    = 0;
    uint32 fld_id    = 0;
    uint32 index     = 0;
    uint32 cmd       = 0;
    uint32 value     = 0;
    McMacMacRxCfg_m  mac_rx;
    Sgmac0RxCfg_m    cpumac_rx;

    SYS_CONDITION_RETURN(SYS_TMM_USELESS_ID16 == mac_id, CTC_E_NONE);

    if(SYS_TMM_MAX_MAC_NUM > mac_id) /*NW*/
    {
        index  = DRV_INS(SYS_TMM_GET_TXQM_BY_MACID(mac_id), 0);
        step   = McMacMacRxCfg_cfgMcMacMacRx_1_cfgMcMacRxPktEn_f - McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxPktEn_f;
        factor = TXQM_INNER_MAC_ID(mac_id);
        tbl_id = McMacMacRxCfg_t;
        fld_id = McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxPktEn_f + step*factor;

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx));
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &mac_rx);
    }
    else /*cpumac*/
    {
        index  = 0;
        step   = Sgmac1RxCfg_t - Sgmac0RxCfg_t;
        factor = mac_id % 4;
        tbl_id = Sgmac0RxCfg_t + step * factor;
        fld_id = Sgmac0RxCfg_cfgSgmac0RxPktEn_f;

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_rx));
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &cpumac_rx);
    }

    SYS_USW_VALID_PTR_WRITE(p_enable, value);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_mac_tx_en(uint8 lchip, uint16 mac_id, uint32 enable)
{
    uint32 factor    = 0;/* 0..39 per txqm */
    uint32 step      = 0;
    uint32 tbl_id    = 0;
    uint32 fld_id    = 0;
    uint32 index     = 0;
    uint32 cmd       = 0;
    uint32 value     = (0 == enable) ? 0 : 1;
    McMacMacTxCfg_m  mac_tx;
    Sgmac0TxCfg_m    cpumac_tx;

    SYS_CONDITION_RETURN(SYS_TMM_USELESS_ID16 == mac_id, CTC_E_NONE);

    if(SYS_TMM_MAX_MAC_NUM > mac_id) /*NW*/
    {
        index  = DRV_INS(SYS_TMM_GET_TXQM_BY_MACID(mac_id), 0);
        step   = McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxPktEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPktEn_f;
        factor = TXQM_INNER_MAC_ID(mac_id);
        tbl_id = McMacMacTxCfg_t;
        fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPktEn_f + step*factor;

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx));
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mac_tx);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx));
    }
    else /*cpumac*/
    {
        index  = 0;
        step   = Sgmac1TxCfg_t - Sgmac0TxCfg_t;
        factor = mac_id % 4;
        tbl_id = Sgmac0TxCfg_t + step * factor;
        fld_id = Sgmac0TxCfg_cfgSgmac0TxPktEn_f;

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_tx));
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &cpumac_tx);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_tx));
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_mac_tx_en(uint8 lchip, uint16 mac_id, uint32* p_enable)
{
    uint32 factor    = 0;/* 0..39 per txqm */
    uint32 step      = 0;
    uint32 tbl_id    = 0;
    uint32 fld_id    = 0;
    uint32 index     = 0;
    uint32 cmd       = 0;
    uint32 value     = 0;
    McMacMacTxCfg_m  mac_tx;
    Sgmac0TxCfg_m    cpumac_tx;

    SYS_CONDITION_RETURN(SYS_TMM_USELESS_ID16 == mac_id, CTC_E_NONE);

    if(SYS_TMM_MAX_MAC_NUM > mac_id) /*NW*/
    {
        index  = DRV_INS(SYS_TMM_GET_TXQM_BY_MACID(mac_id), 0);
        step   = McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxPktEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPktEn_f;
        factor = TXQM_INNER_MAC_ID(mac_id);
        tbl_id = McMacMacTxCfg_t;
        fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPktEn_f + step*factor;

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx));
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &mac_tx);
    }
    else /*cpumac*/
    {
        index  = 0;
        step   = Sgmac1TxCfg_t - Sgmac0TxCfg_t;
        factor = mac_id % 4;
        tbl_id = Sgmac0TxCfg_t + step * factor;
        fld_id = Sgmac0TxCfg_cfgSgmac0TxPktEn_f;

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_tx));
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &cpumac_tx);
    }

    SYS_USW_VALID_PTR_WRITE(p_enable, value);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_init_pre_config(uint8 lchip)
{
    uint8  loigc_serdes_id;
    uint8  txqm_id = 0;
    uint32 pcs_idx;
    uint32 txqm_mac_id;
    uint32 index  = 0;
    uint32 cmd = 0;
    uint8  hss_id = 0;
    uint8  ctcxs_id = 0;
    uint8  is_ctchs = FALSE;
    uint8  hscs = 0;
    uint32 tbl_id;
    uint32 fld_id;
    uint32 value;
    uint32 val_st[2] = {0};
    uint8  x8_x16_index;
    McMacMiiRxCfg_m mii_rx;
    McMacTxSoftReset_m mac_tx_rst;
    McPcsX16LanesInit_m pcs_init;

    /*McMacRxChanMap config all pcs idx to mac*/
    for(loigc_serdes_id = 0; loigc_serdes_id < SYS_TMM_MAX_SERDES_NUM; loigc_serdes_id++)
    {
        hss_id = SYS_TMM_MAP_SERDES_TO_HSS_IDX(loigc_serdes_id);
        SYS_TMM_GET_CTCXS_ID_BY_HSS_ID(hss_id, ctcxs_id, is_ctchs);
        hscs = is_ctchs ? 0 : 1;
        SYS_CONDITION_CONTINUE(TRUE == p_usw_datapath_master[lchip]->hscs_down_flag[hscs][ctcxs_id]);

        SYS_TMM_GET_TXQM_BY_SERDES(loigc_serdes_id, txqm_id);
        txqm_mac_id = SYS_TMM_GET_MACID_PER_TXQM(g_lane_2_pcs_mac_map[loigc_serdes_id].mac_id);
        pcs_idx = g_lane_2_pcs_mac_map[loigc_serdes_id].pcs_idx;
        index = DRV_INS(txqm_id, pcs_idx);

        cmd = DRV_IOW(McMacRxChanMap_t, McMacRxChanMap_chanMap_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &txqm_mac_id));
    }

    /*cfgMcMacMiiRxFaultMaskLinkEn set to default 1*/
    /*cfgMcMacMiiRxFaultFilterEn set to default 1*/
    /*cfgMcMacMiiRxLinkFilterEn set to default 1 (default 1.6ms)*/
    /*McMacTxSoftReset.cfgMcMacMacTxSoftReset set all bits to 0*/
    /*McMacMacRxCfg.cfgMcMacMacRx_0_cfgMcMacRxPktEn default set 0*/
    /*McPcsX16LanesInit/McPcsX8LanesInit.init write 1*/
    for(txqm_id = 0; txqm_id < SYS_TMM_TXQM_NUM_PER_DP*SYS_TMM_DP_NUM; txqm_id++)
    {
        hscs = SYS_TMM_IS_PCS_X16(txqm_id) ? 0 : 1;
        SYS_TMM_GET_PCSXIDX(txqm_id, x8_x16_index);
        SYS_CONDITION_CONTINUE(TRUE == p_usw_datapath_master[lchip]->hscs_down_flag[hscs][x8_x16_index]);
        
        /*cfgMcMacMiiRxFaultMaskLinkEn default 1*/
        /*cfgMcMacMiiRxFaultFilterEn set to default 1*/
        /*cfgMcMacMiiRxLinkFilterEn set to default 1 (default 1.6ms)*/
        index = DRV_INS(txqm_id, 0);
        cmd = DRV_IOR(McMacMiiRxCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_rx));
        value = 1;
        for(txqm_mac_id = 0; txqm_mac_id < SYS_TMM_MAX_MAC_NUM_PER_TXQM; txqm_mac_id++)
        {
            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultMaskLinkEn_f + 
                    (McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiRxFaultMaskLinkEn_f - 
                     McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultMaskLinkEn_f) * txqm_mac_id;
            DRV_IOW_FIELD_NZ(lchip, McMacMiiRxCfg_t, fld_id, &value, &mii_rx, txqm_id, 0);
            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterEn_f + 
                    (McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiRxFaultFilterEn_f - 
                     McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterEn_f) * txqm_mac_id;
            DRV_IOW_FIELD_NZ(lchip, McMacMiiRxCfg_t, fld_id, &value, &mii_rx, txqm_id, 0);
            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterEn_f + 
                    (McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiRxLinkFilterEn_f - 
                     McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterEn_f) * txqm_mac_id;
            DRV_IOW_FIELD_NZ(lchip, McMacMiiRxCfg_t, fld_id, &value, &mii_rx, txqm_id, 0);
        }
        cmd = DRV_IOW(McMacMiiRxCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_rx));

        /*McMacTxSoftReset.cfgMcMacMacTxSoftReset set all bits to 0*/
        index = DRV_INS(txqm_id, 0);
        cmd = DRV_IOR(McMacTxSoftReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_rst));
        DRV_IOW_FIELD(lchip, McMacTxSoftReset_t, McMacTxSoftReset_cfgMcMacMacTxSoftReset_f, val_st, &mac_tx_rst);
        cmd = DRV_IOW(McMacTxSoftReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_rst));

        /*McMacMacRxCfg.cfgMcMacMacRx_0_cfgMcMacRxPktEn default set 0*/
        for(txqm_mac_id = 0; txqm_mac_id < SYS_TMM_MAX_MAC_NUM_PER_TXQM; txqm_mac_id++)
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_rx_en(lchip, (txqm_id * SYS_TMM_MAX_MAC_NUM_PER_TXQM + txqm_mac_id), 0));
        }
        /*cpumac*/
        for(txqm_mac_id = 320; txqm_mac_id < 324; txqm_mac_id++)
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_rx_en(lchip, txqm_mac_id, 0));
        }

        /*McPcsX16LanesInit/McPcsX8LanesInit.init write 1*/
        index = DRV_INS(x8_x16_index, 0);
        tbl_id = SYS_TMM_IS_PCS_X16(txqm_id) ? McPcsX16LanesInit_t      : McPcsX8LanesInit_t;
        fld_id = SYS_TMM_IS_PCS_X16(txqm_id) ? McPcsX16LanesInit_init_f : McPcsX8LanesInit_init_f;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_init));
        value = 1;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &pcs_init);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_init));
    }

    return CTC_E_NONE;
}

/*McPcsX16LanesRxALaneSwapCfg/McPcsX16LanesRxBLaneSwapCfg/McPcsX8LanesRxLaneSwapCfg*/
int32
_sys_tmm_mac_hss_rxswaplane_config(uint8 lchip, uint8 hss_id)
{
    uint32 value = 0;
    uint32 val_str[1] = {0};
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint8  txqm_id;
    uint32 is_pcs_x16 = 0;
    uint32 pcs_x8_x16_index = 0;
    uint32 index  = 0;
    uint8  lane_id = 0;
    uint8  logic_serdes_id = 0;
    uint8  physi_serdes_id = 0;
    int32  ret = 0;
    uint32 cmd = 0;
    uint8  ctcxs_id = 0;
    uint8  is_ctchs = FALSE;
    uint8  hscs = 0;
    uint8  find_flag;
    uint8  cfg_lane_id[SYS_TMM_LANE_NUM_PER_HSS] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};

    /*judge power down*/
    SYS_TMM_GET_CTCXS_ID_BY_HSS_ID(hss_id, ctcxs_id, is_ctchs);
    hscs = is_ctchs ? 0 : 1;
    SYS_CONDITION_RETURN(TRUE == p_usw_datapath_master[lchip]->hscs_down_flag[hscs][ctcxs_id], CTC_E_NONE);

    SYS_TMM_GET_TXQM_ID_BY_HSS_ID(hss_id, txqm_id);
    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(txqm_id, is_pcs_x16, pcs_x8_x16_index);
    index = DRV_INS(pcs_x8_x16_index, 0);
    tbl_id = is_pcs_x16 ? 
             (SYS_TMM_JUDGE_PCSX16A(hss_id) ? McPcsX16LanesRxALaneSwapCfg_t : McPcsX16LanesRxBLaneSwapCfg_t) : 
             McPcsX8LanesRxLaneSwapCfg_t;

    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &val_str));

    /*fill valid serdes mapping*/
    for(lane_id = 0; lane_id < SYS_TMM_LANE_NUM_PER_HSS; lane_id++)
    {
        logic_serdes_id = SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id);
        ret = _sys_usw_datapath_get_physical_serdes_id_by_logical(lchip, logic_serdes_id, &physi_serdes_id);
        SYS_CONDITION_CONTINUE(CTC_E_NONE != ret); /*normal condition, return error means this hss is not used*/

        fld_id = SYS_TMM_MAP_SERDES_TO_LANE_ID(physi_serdes_id);
        value  = SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_id);

        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &val_str);

        cfg_lane_id[fld_id] = value;
    }
    /*fill idle serdes mapping, to ensure every valid serdes mapping unique*/
    for(fld_id = 0; fld_id < SYS_TMM_LANE_NUM_PER_HSS; fld_id++)
    {
        SYS_CONDITION_CONTINUE(0xff != cfg_lane_id[fld_id]);

        for(value = 0; value < SYS_TMM_LANE_NUM_PER_HSS; value++)
        {
            find_flag = FALSE;
            for(lane_id = 0; lane_id < SYS_TMM_LANE_NUM_PER_HSS; lane_id++)
            {
                if(value == cfg_lane_id[lane_id])
                {
                    find_flag = TRUE;
                    break;
                }
            }
            SYS_CONDITION_BREAK(FALSE == find_flag);
        }

        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &val_str);
    }

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &val_str));

    return CTC_E_NONE;
}

/*set McHataTxPortMap_portMap_f*/
/*mac en flow: do valid mapping
init & remap & dyn sw flow: clear to invalid 0x3f*/
int32
_sys_tmm_mac_set_hata_tx_port_map(uint8 lchip, uint8 txqm_id, uint32 txqm_mac_id, uint32 value)
{
    uint32 cmd;
    uint32 index;
    McHataTxPortMap_m hata_map;

    /*set McHataTxPortMap_portMap_f*/
    index  = DRV_INS(txqm_id, txqm_mac_id);
    cmd    = DRV_IOR(McHataTxPortMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_map));
    DRV_IOW_FIELD_NZ(lchip, McHataTxPortMap_t, McHataTxPortMap_portMap_f, &value, &hata_map, txqm_id, txqm_mac_id);
    cmd    = DRV_IOW(McHataTxPortMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_map));

    return CTC_E_NONE;
}

/*set McHataTxChanMap_chanMap_f and McHataTxChanMap_rxChanMap_f*/
/*mac en flow: do valid mapping
init & remap & dyn sw flow: clear to invalid 0x3f*/
int32
_sys_tmm_mac_set_hata_tx_map(uint8 lchip, uint8 txqm_id, uint32 tbl_idx, uint32 fld_id, uint32 value)
{
    uint32 cmd;
    uint32 index;
    McHataTxChanMap_m hata_map;

    SYS_CONDITION_RETURN((McHataTxChanMap_rxChanMap_f < fld_id), CTC_E_INVALID_PARAM);

    /*set McHataTxChanMap_chanMap_f*/
    index  = DRV_INS(txqm_id, tbl_idx);
    cmd    = DRV_IOR(McHataTxChanMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_map));
    DRV_IOW_FIELD_NZ(lchip, McHataTxChanMap_t, fld_id, &value, &hata_map, txqm_id, tbl_idx);
    cmd    = DRV_IOW(McHataTxChanMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_map));

    return CTC_E_NONE;
}

/*McHataSoftResetCfg_cfgMcHataRxSoftReset_f*/
/*McHataSoftResetCfg_cfgMcHataTxSoftReset_f*/
int32
_sys_tmm_mac_set_hata_rst(uint8 lchip, sys_datapath_lport_attr_t* port_attr, uint8 dir, uint8 rst)
{
    uint32 tbl_id     = McHataSoftResetCfg_t;
    uint32 fld_id     = (SYS_DATAPATH_SERDES_DIR_RX == dir) ? 
                        McHataSoftResetCfg_cfgMcHataRxSoftReset_f : McHataSoftResetCfg_cfgMcHataTxSoftReset_f;
    uint32 cmd        = 0;
    uint32 index      = DRV_INS(port_attr->txqm_id, 0);
    uint32 array32[2] = {0};
    uint8  is_pcs_x16 = SYS_TMM_IS_PCS_X16(port_attr->txqm_id);
    McHataSoftResetCfg_m hata_rst;

    SYS_CONDITION_RETURN((SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type), CTC_E_NONE);
    SYS_CONDITION_RETURN((CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode), CTC_E_NONE);
    /*skip config if subversion is A and port mode is SGMII*/
    SYS_CONDITION_RETURN(((SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_A) && 
        ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))), 
        CTC_E_NONE);

    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_rst));

    DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &hata_rst);
    if(0 == rst)
    {
        if(SYS_DATAPATH_SERDES_DIR_RX == dir) /*release RX rst*/
        {
            array32[0] &= ~(1 << (port_attr->pcs_idx));
        }
        else /*release TX rst*/
        {
            array32[0] &= ~(1 << (port_attr->multi_serdes_id[0] % (is_pcs_x16 ? 16 : 8)));
        }
    }
    else
    {
        if(SYS_DATAPATH_SERDES_DIR_RX == dir) /*set RX rst*/
        {
            array32[0] |= (1 << (port_attr->pcs_idx));
        }
        else /*set TX rst*/
        {
            array32[0] |= (1 << (port_attr->multi_serdes_id[0] % (is_pcs_x16 ? 16 : 8)));
        }
    }
    DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &hata_rst, port_attr->txqm_id, 0);
    
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_rst));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_lport_serdes_ocs(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr, uint16 *p_ocs)
{
    uint8  physic_serdes = 0;
    uint8  logic_serdes  = 0;
    sys_datapath_lport_attr_t* p_port_attr = NULL;
    sys_datapath_serdes_info_t* p_serdes   = NULL;

    if(NULL == port_attr)
    {
        CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &p_port_attr));
    }
    else
    {
        p_port_attr = port_attr;
    }

    physic_serdes = p_port_attr->multi_serdes_id[0];
    CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, physic_serdes, &logic_serdes));

    SYS_CONDITION_RETURN((MCHIP_CAP(SYS_CAP_DMPS_SERDES_NUM_PER_SLICE) <= physic_serdes), CTC_E_INVALID_PARAM);

    CTC_ERROR_RETURN(sys_usw_datapath_get_serdes_info(lchip, logic_serdes, &p_serdes));

    SYS_USW_VALID_PTR_WRITE(p_ocs, p_serdes->overclocking_speed);

    return CTC_E_NONE;
}

/*McHataEnable_cfgHataTxEnable_f*/
/*McHataEnable_cfgHataRxEnable_f*/
int32
_sys_tmm_mac_set_hata_en(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr, uint8 dir, uint8 en)
{
    uint32 tbl_id     = McHataEnable_t;
    uint32 fld_id     = (SYS_DATAPATH_SERDES_DIR_RX == dir) ? 
                        McHataEnable_cfgHataRxEnable_f : McHataEnable_cfgHataTxEnable_f;
    uint32 cmd        = 0;
    uint32 index      = DRV_INS(port_attr->txqm_id, 0);
    uint32 array32[2] = {0};
    uint32 fec_val    = CTC_PORT_FEC_TYPE_NONE;
    uint16 inner_mac_id = 0;
    uint16 ocs = 0;
    McHataEnable_m hata_en;

    SYS_CONDITION_RETURN((CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode), CTC_E_NONE);
    /*skip config if port mode is SGMII && (subversion 1.0 || g_hata_sgmii_en 0)*/
    if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
    {
        SYS_CONDITION_RETURN((FALSE == g_hata_sgmii_en), CTC_E_NONE);
        SYS_CONDITION_RETURN((SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_A), CTC_E_NONE);
    }

    /*skip ocs 27.34375G, e.g. 26.52G*/
    CTC_ERROR_RETURN(_sys_tmm_mac_get_lport_serdes_ocs(lchip, lport, port_attr, &ocs));
    SYS_CONDITION_RETURN((CTC_CHIP_SERDES_OCS_MODE_26_52G == ocs), CTC_E_NONE);

    CTC_ERROR_RETURN(_sys_tmm_mac_get_fec_en(lchip, lport, &fec_val));

    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_en));

    DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &hata_en);
    inner_mac_id = TXQM_INNER_MAC_ID(port_attr->mac_id);
    if(1 == en)
    {
        if(inner_mac_id >= 32)
        {
            if((CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val))
            {
                array32[1] &= ~(1 << (inner_mac_id % 8));
            }
            else
            {
                array32[1] |= (1 << (inner_mac_id % 8));
            }
        }
        else
        {
            if((CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val))
            {
                array32[0] &= ~(1 << inner_mac_id);
            }
            else
            {
                array32[0] |= (1 << inner_mac_id);
            }
        }
    }
    else
    {
        if(inner_mac_id >= 32)
        {
            array32[1] &= ~(1 << (inner_mac_id % 8));
        }
        else
        {
            array32[0] &= ~(1 << inner_mac_id);
        }
    }
    DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &hata_en, port_attr->txqm_id, 0);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_en));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_low_corepll_fec_free(uint8 lchip, sys_datapath_lport_attr_t* port_attr)
{
    uint32 pcs_x8_x16_index  = 0;
    uint8  (*fec2pcs_map)[4] = NULL;
    uint8  fec_chan_max;
    uint8  codec_id;
    uint8  fec_chan;
    uint8  fec_idx;
    uint8  pcs_idx = port_attr->pcs_idx;

    /*0. para check*/
    SYS_CONDITION_RETURN((1050 <= p_usw_datapath_master[lchip]->core_plla), CTC_E_NONE);

    /*1. free fec idx, only soft tables are changed*/
    SYS_TMM_GET_PCSXIDX(port_attr->txqm_id, pcs_x8_x16_index);
    if(SYS_TMM_IS_PCS_X16(port_attr->txqm_id))
    {
        fec2pcs_map = p_usw_datapath_master[lchip]->fec2pcs_hs_map;
        fec_chan_max = 8;
        codec_id = (8 > pcs_idx) ? 0 : 1;
    }
    else
    {
        fec2pcs_map = p_usw_datapath_master[lchip]->fec2pcs_cs_map;
        fec_chan_max = 4;
        codec_id = ((0 == pcs_idx) || (1 == pcs_idx) || (6 == pcs_idx) || (7 == pcs_idx)) ? 0 : 1;
    }
    
    for(fec_chan = 0; fec_chan < fec_chan_max; fec_chan++)
    {
        fec_idx = codec_id * fec_chan_max + fec_chan;
        SYS_CONDITION_CONTINUE(port_attr->pcs_idx != fec2pcs_map[fec_idx][pcs_x8_x16_index]);
        fec2pcs_map[fec_idx][pcs_x8_x16_index] = 0xff;
        break;
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_low_corepll_fec2pcs_mapping(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr, 
                                                      uint8* p_fec_chan, uint8* p_fec_idx)
{
    uint32 pcs_x8_x16_index  = 0;
    uint8  (*fec2pcs_map)[4] = NULL;
    uint8  *fec_chan_prio    = NULL;
    uint8  fec_chan_max;
    uint8  codec_id;
    uint8  prio;
    uint8  fec_chan;
    uint8  fec_chan_opt = 0;
    uint8  fec_idx;
    uint8  fec_idx_opt = 0;
    uint8  pcs_idx  = port_attr->pcs_idx;
    uint8  upt_flag = FALSE;
    uint32 fec;
    uint8  fec_chan_prio_hs[8] = {3, 0xff, 1, 0xff, 2, 0xff, 1, 0xff}; //fec chan priority for low corepll, 1~25G 2~25G/50G 3~25G/50G/100G 
    uint8  fec_chan_prio_cs[4] = {3, 1, 2, 1}; //fec chan priority for low corepll, 1~25G 2~25G/50G 3~25G/50G/100G/200G

    fec = p_usw_mac_master[lchip]->mac_prop[lport].port_fec_val;
    SYS_CONDITION_RETURN(((CTC_PORT_FEC_TYPE_RS != fec) && (CTC_PORT_FEC_TYPE_RS528 != fec) && 
                          (CTC_PORT_FEC_TYPE_RS544 != fec) && (CTC_PORT_FEC_TYPE_RS272 != fec)), CTC_E_INVALID_PARAM);

    switch(port_attr->pcs_mode)
    {
        case CTC_CHIP_SERDES_XXVG_MODE:
            prio = 1;
            break;
        case CTC_CHIP_SERDES_LG_MODE:
        case CTC_CHIP_SERDES_LG_R1_MODE:
            prio = 2;
            break;
        case CTC_CHIP_SERDES_CG_MODE:
        case CTC_CHIP_SERDES_CG_R2_MODE:
        case CTC_CHIP_SERDES_CCG_R4_MODE:
            prio = 3;
            break;
        default:
            return CTC_E_INVALID_PARAM;
    }

    SYS_TMM_GET_PCSXIDX(port_attr->txqm_id, pcs_x8_x16_index);

    if(SYS_TMM_IS_PCS_X16(port_attr->txqm_id))
    {
        fec2pcs_map = p_usw_datapath_master[lchip]->fec2pcs_hs_map;
        fec_chan_prio = fec_chan_prio_hs;
        fec_chan_max = 8;
        codec_id = (8 > pcs_idx) ? 0 : 1;
    }
    else
    {
        fec2pcs_map = p_usw_datapath_master[lchip]->fec2pcs_cs_map;
        fec_chan_prio = fec_chan_prio_cs;
        fec_chan_max = 4;
        codec_id = ((0 == pcs_idx) || (1 == pcs_idx) || (6 == pcs_idx) || (7 == pcs_idx)) ? 0 : 1;
    }

    /*find all priority acceptable fec idx and take the largest as optimized idx, because larger fec idx has lower priority*/
    for(fec_chan = 0; fec_chan < fec_chan_max; fec_chan++)
    {
        SYS_CONDITION_CONTINUE((0xff == fec_chan_prio[fec_chan]) || (prio > fec_chan_prio[fec_chan]));
        fec_idx = codec_id * fec_chan_max + fec_chan;
        SYS_CONDITION_CONTINUE(0xff != fec2pcs_map[fec_idx][pcs_x8_x16_index]);
        fec_chan_opt = fec_chan;
        fec_idx_opt  = fec_idx;
        upt_flag     = TRUE;
    }

    if(!upt_flag)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Expecting fec idx not available! pcs_idx %u, mode %u, current map [", 
            pcs_idx, port_attr->pcs_mode);
        for(fec_idx = 0; fec_idx < fec_chan_max*2; fec_idx++)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%u ", fec2pcs_map[fec_idx][pcs_x8_x16_index]);
        }
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "]\n");
        return CTC_E_INVALID_PARAM;
    }

    fec2pcs_map[fec_idx_opt][pcs_x8_x16_index] = pcs_idx;

    SYS_USW_VALID_PTR_WRITE(p_fec_chan, fec_chan_opt);
    SYS_USW_VALID_PTR_WRITE(p_fec_idx,  fec_idx_opt);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_low_corepll_fec_remap(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr)
{
    uint8  fec_chan;
    uint8  fec_idx;
    uint32 fec_map[4] = {0};
    uint32 index = 0;
    uint32 cmd   = 0;
    uint32 value = 0;
    uint32 fld_id;
    uint32 tbl_id;
    uint32 pcs_x8_x16_index  = 0;
    int32  ret = CTC_E_NONE;

    /*0. para check*/
    SYS_CONDITION_RETURN((1050 <= p_usw_datapath_master[lchip]->core_plla), CTC_E_NONE);

    /*1. map pcs to appropriate fec idx*/
    ret = _sys_tmm_mac_low_corepll_fec2pcs_mapping(lchip, lport, port_attr, &fec_chan, &fec_idx);
    SYS_CONDITION_RETURN((CTC_E_NONE != ret), CTC_E_NONE);

    /*2. write tables*/
    SYS_TMM_GET_PCSXIDX(port_attr->txqm_id, pcs_x8_x16_index);
    index  = DRV_INS(pcs_x8_x16_index, 0);
    tbl_id = SYS_TMM_IS_PCS_X16(port_attr->txqm_id) ? McPcsX16LanesFecChanMap_t : McPcsX8LanesFecChanMap_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &fec_map));
    if(SYS_TMM_IS_PCS_X16(port_attr->txqm_id))
    {
        fld_id = McPcsX16LanesFecChanMap_cfgPcsChan0FecChan_f + port_attr->pcs_idx;
        value  = fec_chan;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &fec_map);
        fld_id = McPcsX16LanesFecChanMap_cfgFecChan0PcsChan_f + fec_idx;
        value  = port_attr->pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &fec_map);
    }
    else
    {
        fld_id = McPcsX8LanesFecChanMap_cfgPcsChan0FecChan_f + port_attr->pcs_idx;
        value  = fec_chan;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &fec_map);
        fld_id = McPcsX8LanesFecChanMap_cfgFecChan0PcsChan_f + fec_idx;
        value  = port_attr->pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &fec_map);
    }
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &fec_map));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_init_low_corepll_config(uint8 lchip)
{
    uint16 lport;
    uint32 index = 0;
    uint32 cmd   = 0;
    uint32 value = 0;
    uint32 pcs_x8_x16_index  = 0;
    uint8  fec_chan;
    uint8  fec_idx;
    uint8  pcs_idx;
    uint32 fld_id;
    McPcsX8LanesFecChanMap_m fec_map;
    McPcsX16LanesFecChanMap_m fec_map_hs;
    McPcsX8LanesMcFecCfg_m   x8_fec;
    McPcsX16LanesMcFecCfg_m  x16_fec;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_CONDITION_RETURN((1050 <= p_usw_datapath_master[lchip]->core_plla), CTC_E_NONE);
    for(pcs_x8_x16_index = 0; pcs_x8_x16_index < 4; pcs_x8_x16_index++)
    {
        /*CS*/
        if(FALSE == p_usw_datapath_master[lchip]->hscs_down_flag[1][pcs_x8_x16_index])
        {
            /*McPcsX8Lanes_McPcsX8LanesFecChanMap_cfgFecChan[4~7]PcsChan*/
            /*McPcsX8Lanes_McPcsX8LanesFecChanMap_cfgPcsChan[2~5]FecChan*/
            index = DRV_INS(pcs_x8_x16_index, 0);
            cmd = DRV_IOR(McPcsX8LanesFecChanMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &fec_map));
            value = 4;
            DRV_IOW_FIELD(lchip, McPcsX8LanesFecChanMap_t, McPcsX8LanesFecChanMap_cfgFecChan4PcsChan_f, &value, &fec_map);
            value = 5;
            DRV_IOW_FIELD(lchip, McPcsX8LanesFecChanMap_t, McPcsX8LanesFecChanMap_cfgFecChan5PcsChan_f, &value, &fec_map);
            value = 2;
            DRV_IOW_FIELD(lchip, McPcsX8LanesFecChanMap_t, McPcsX8LanesFecChanMap_cfgFecChan6PcsChan_f, &value, &fec_map);
            value = 3;
            DRV_IOW_FIELD(lchip, McPcsX8LanesFecChanMap_t, McPcsX8LanesFecChanMap_cfgFecChan7PcsChan_f, &value, &fec_map);
            value = 2;
            DRV_IOW_FIELD(lchip, McPcsX8LanesFecChanMap_t, McPcsX8LanesFecChanMap_cfgPcsChan2FecChan_f, &value, &fec_map);
            value = 3;
            DRV_IOW_FIELD(lchip, McPcsX8LanesFecChanMap_t, McPcsX8LanesFecChanMap_cfgPcsChan3FecChan_f, &value, &fec_map);
            value = 0;
            DRV_IOW_FIELD(lchip, McPcsX8LanesFecChanMap_t, McPcsX8LanesFecChanMap_cfgPcsChan4FecChan_f, &value, &fec_map);
            value = 1;
            DRV_IOW_FIELD(lchip, McPcsX8LanesFecChanMap_t, McPcsX8LanesFecChanMap_cfgPcsChan5FecChan_f, &value, &fec_map);
            cmd = DRV_IOW(McPcsX8LanesFecChanMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &fec_map));

            /*McPcsX8LanesMcFecCfg.cfgLowFreqEnMcFec set 1*/
            index = DRV_INS(pcs_x8_x16_index, 0);
            cmd = DRV_IOR(McPcsX8LanesMcFecCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &x8_fec));
            value = 1;
            DRV_IOW_FIELD(lchip, McPcsX8LanesMcFecCfg_t, McPcsX8LanesMcFecCfg_cfgLowFreqEnMcFec_f, &value, &x8_fec);
            cmd = DRV_IOW(McPcsX8LanesMcFecCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &x8_fec));
        }

        /*HS*/
        if(FALSE == p_usw_datapath_master[lchip]->hscs_down_flag[0][pcs_x8_x16_index])
        {
            /*McPcsX16LanesMcFecCfg.cfgLowFreqEnMcFec set 1*/
            index = DRV_INS(pcs_x8_x16_index, 0);
            cmd = DRV_IOR(McPcsX16LanesMcFecCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &x16_fec));
            value = 1;
            DRV_IOW_FIELD(lchip, McPcsX16LanesMcFecCfg_t, McPcsX16LanesMcFecCfg_cfgLowFreqEnMcFec_f, &value, &x16_fec);
            cmd = DRV_IOW(McPcsX16LanesMcFecCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &x16_fec));
        }
    }

    /*FEC chan mapping*/
    sal_memset(p_usw_datapath_master[lchip]->fec2pcs_hs_map, SYS_TMM_USELESS_ID8, sizeof(uint8)*16*4);
    sal_memset(p_usw_datapath_master[lchip]->fec2pcs_cs_map, SYS_TMM_USELESS_ID8, sizeof(uint8)*8*4);
    for(lport = 0; lport < SYS_INTERNAL_PORT_START; lport++)
    {
        CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
        SYS_CONDITION_CONTINUE(SYS_DMPS_NETWORK_PORT != port_attr->port_type);
        _sys_tmm_mac_low_corepll_fec2pcs_mapping(lchip, lport, port_attr, NULL, NULL);
    }
    /*FEC chan config hs*/
    for(pcs_x8_x16_index = 0; pcs_x8_x16_index < 4; pcs_x8_x16_index++)
    {
        SYS_CONDITION_CONTINUE(TRUE == p_usw_datapath_master[lchip]->hscs_down_flag[0][pcs_x8_x16_index]);

        index = DRV_INS(pcs_x8_x16_index, 0);
        cmd = DRV_IOR(McPcsX16LanesFecChanMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &fec_map_hs));
        for(fec_idx = 0; fec_idx < 16; fec_idx++)
        {
            SYS_CONDITION_CONTINUE(0xff == p_usw_datapath_master[lchip]->fec2pcs_hs_map[fec_idx][pcs_x8_x16_index]);
            fec_chan = fec_idx % 8;
            pcs_idx  = p_usw_datapath_master[lchip]->fec2pcs_hs_map[fec_idx][pcs_x8_x16_index];

            fld_id   = McPcsX16LanesFecChanMap_cfgPcsChan0FecChan_f + pcs_idx;
            value    = fec_chan;
            DRV_IOW_FIELD(lchip, McPcsX16LanesFecChanMap_t, fld_id, &value, &fec_map_hs);

            fld_id   = McPcsX16LanesFecChanMap_cfgFecChan0PcsChan_f + fec_idx;
            value    = pcs_idx;
            DRV_IOW_FIELD(lchip, McPcsX16LanesFecChanMap_t, fld_id, &value, &fec_map_hs);
        }
        cmd = DRV_IOW(McPcsX16LanesFecChanMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &fec_map_hs));
    }
    /*FEC chan config cs*/
    for(pcs_x8_x16_index = 0; pcs_x8_x16_index < 4; pcs_x8_x16_index++)
    {
        SYS_CONDITION_CONTINUE(TRUE == p_usw_datapath_master[lchip]->hscs_down_flag[1][pcs_x8_x16_index]);

        index = DRV_INS(pcs_x8_x16_index, 0);
        cmd = DRV_IOR(McPcsX8LanesFecChanMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &fec_map));
        for(fec_idx = 0; fec_idx < 8; fec_idx++)
        {
            SYS_CONDITION_CONTINUE(0xff == p_usw_datapath_master[lchip]->fec2pcs_cs_map[fec_idx][pcs_x8_x16_index]);
            fec_chan = fec_idx % 4;
            pcs_idx  = p_usw_datapath_master[lchip]->fec2pcs_cs_map[fec_idx][pcs_x8_x16_index];

            fld_id   = McPcsX8LanesFecChanMap_cfgPcsChan0FecChan_f + pcs_idx;
            value    = fec_chan;
            DRV_IOW_FIELD(lchip, McPcsX8LanesFecChanMap_t, fld_id, &value, &fec_map);

            fld_id   = McPcsX8LanesFecChanMap_cfgFecChan0PcsChan_f + fec_idx;
            value    = pcs_idx;
            DRV_IOW_FIELD(lchip, McPcsX8LanesFecChanMap_t, fld_id, &value, &fec_map);
        }
        cmd = DRV_IOW(McPcsX8LanesFecChanMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &fec_map));
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_init_post_config(uint8 lchip)
{
    uint8 hss_id = 0;
    uint8 txqm_id;
    uint8 idx;
    uint8 ctcxs_id = 0;
    uint8 is_ctchs = FALSE;
    uint8 hscs = 0;

    /*1. rx swap config*/
    for(hss_id = 0; hss_id < SYS_TMM_MAX_HSS_NUM; hss_id++)
    {
        SYS_TMM_GET_CTCXS_ID_BY_HSS_ID(hss_id, ctcxs_id, is_ctchs);
        hscs = is_ctchs ? 0 : 1;
        SYS_CONDITION_CONTINUE(TRUE == p_usw_datapath_master[lchip]->hscs_down_flag[hscs][ctcxs_id]);

        CTC_ERROR_RETURN(_sys_tmm_mac_hss_rxswaplane_config(lchip, hss_id));

        /*clear McHataTxChanMap_chanMap_f to 0x3f*/
        /*clear McHataTxChanMap_rxChanMap_f to 0x3f*/
        /*clear McHataTxPortMap_portMap_f to 0x3f*/
        SYS_TMM_GET_TXQM_ID_BY_HSS_ID(hss_id, txqm_id);
        for(idx = 0; idx < SYS_TMM_MAX_MAC_NUM_PER_TXQM; idx++)
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, idx, McHataTxChanMap_chanMap_f, 0x3f));
            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, idx, McHataTxChanMap_rxChanMap_f, 0x3f));
            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_port_map(lchip, txqm_id, idx, 0x3f));
        }
    }

    /*2. low core pll config*/
    CTC_ERROR_RETURN(_sys_tmm_mac_init_low_corepll_config(lchip));

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_sgmii_20T_clock_toggle(uint8 lchip, uint8 lport)
{
    uint8 physic_serdes_id =0;
    uint32 is_up = 0;
    uint8 toggle_cnt = 0;
    uint32 intr_stat = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    
/*vchip not support*/
#if (MCHIP_SIM == 1)
    {
        extern bool dal_chip_is_sim(uint8 ldev);
        if (dal_chip_is_sim(SYS_MAP_LDEV(lchip)))
        {
            return 0;
        }
    }
#endif 

    /*when wb reloading, don't toggle 20T clock for CPUMAC*/
    SYS_CONDITION_RETURN((p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING), CTC_E_NONE);

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN(!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type), CTC_E_NONE);

    if((CTC_CHIP_SERDES_SGMII_MODE != port_attr->pcs_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != port_attr->pcs_mode))
    {
        return CTC_E_NONE; 
    }

    physic_serdes_id = port_attr->multi_serdes_id[0];

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_intr(lchip, lport, &intr_stat));
    if(0 != intr_stat)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_set_link_intr(lchip, lport, FALSE));
    }

    /*step1.1 : enable pcs internal loopback*/
    CTC_ERROR_RETURN(_sys_tmm_datapath_set_internal_loopback_pcs(lchip, physic_serdes_id, TRUE));

    /*step1.2 : serdes 0x00a0[13] = 1  delete because default tx disable*/

    /*step1.3 : mac enable*/
    CTC_ERROR_RETURN(_sys_tmm_cpumac_set_mac_en(lchip, lport, TRUE));
    CTC_ERROR_RETURN(_sys_tmm_cpumac_lane3_pcs_rx_reset(lchip, lport, port_attr));

    /*step2 : 20T clock toggle*/
    while(toggle_cnt < 30)
    {
        sal_task_sleep(50);
        CTC_ERROR_RETURN(_sys_tmm_cpumac_get_sgmii_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK, lport, &is_up, FALSE));

        if(is_up)
        {   
            break;
        }
        else
        {
            /*step2.1 : mac disable*/
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_mac_en(lchip, lport, FALSE));
            /*step2.2 :  C9[14] = 0b0*/
            CTC_ERROR_RETURN(sys_tmm_serdes_write_reg(lchip, physic_serdes_id, 0xc9, 0xbfff, 0x0));
            sal_task_sleep(3);
            /*step2.3 :  C9[14] = 0b1*/
            CTC_ERROR_RETURN(sys_tmm_serdes_write_reg(lchip, physic_serdes_id, 0xc9, 0xbfff, 0x1));
            /*step2.4 : mac enable*/
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_mac_en(lchip, lport, TRUE));
            CTC_ERROR_RETURN(_sys_tmm_cpumac_lane3_pcs_rx_reset(lchip, lport, port_attr));
        }
        toggle_cnt ++;

        /*delay 500 ms*/
        sal_task_sleep(450);
    }

    /*step3*/
    /*step3.1 : Set 0xa0[13] to Default Value  delete because default tx disable*/

    /*step3.2 : disable pcs internal loopback*/
    CTC_ERROR_RETURN(_sys_tmm_datapath_set_internal_loopback_pcs(lchip, physic_serdes_id, FALSE));

    CTC_ERROR_RETURN(_sys_tmm_cpumac_set_mac_en(lchip, lport, FALSE));

    if(0 != intr_stat)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_link_intr(lchip, lport, TRUE));
    }

    if(toggle_cnt >= 30)
    {
        return CTC_E_INVALID_CONFIG;
    }
    
    return CTC_E_NONE;
}


STATIC int32
_sys_tmm_mac_init_mac_config(uint8 lchip)
{
    uint16 mac_id   = 0;
    uint16 lport    = 0;
    uint8  cpumac_idx;
    uint8  dp;
    uint8  dp_txqm_id;
    uint8  hscs_idx;
    ctc_port_fec_type_t default_fec_type;
    sys_usw_port_mac_config_t port_mac_config = {0};
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d\n", __FUNCTION__, __LINE__);

    CTC_ERROR_RETURN(_sys_tmm_mac_init_pre_config(lchip));

    /*NETWORK port initial config*/
    for (mac_id = 0; mac_id < SYS_TMM_MAX_MAC_NUM; mac_id++)
    {
        lport = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);
        SYS_CONDITION_CONTINUE(SYS_COMMON_USELESS_MAC == lport);

        CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
        if (SYS_DMPS_NETWORK_PORT == port_attr->port_type)
        {
            port_mac_config.lport = lport;
            port_mac_config.speed_mode = port_attr->speed_mode;
            port_mac_config.speed_value = port_attr->speed_value;
            port_mac_config.interface_type = port_attr->interface_type;
            default_fec_type = CTC_PORT_FEC_TYPE_NONE;
            if(SYS_TMM_MODE_IS_PAM4(port_attr->pcs_mode))
            {
                default_fec_type = CTC_PORT_FEC_TYPE_RS544;
            }

            CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_config(lchip, lport, port_attr->pcs_mode, default_fec_type, SYS_DMPS_NETWORK_PORT, TRUE));

            CTC_ERROR_RETURN(sys_usw_port_mac_config_attach(lchip, &port_mac_config));
        }
        else
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", mac_id);
        }
    }

    CTC_ERROR_RETURN(_sys_tmm_mac_init_post_config(lchip));

    /*CPUMAC initial config*/
    for(cpumac_idx = 0; cpumac_idx < SYS_TMM_CPUMAC_SERDES_NUM; cpumac_idx++)
    {
        lport = p_usw_datapath_master[lchip]->cpumac_map[cpumac_idx].lport;
        SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
        SYS_CONDITION_CONTINUE(!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type));
        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_mac_config(lchip, lport, port_attr));
        port_mac_config.lport = lport;
        port_mac_config.speed_mode = port_attr->speed_mode;
        port_mac_config.speed_value = port_attr->speed_value;
        port_mac_config.interface_type = port_attr->interface_type;
        CTC_ERROR_RETURN(sys_usw_port_mac_config_attach(lchip, &port_mac_config));
    }
    CTC_ERROR_RETURN(_sys_tmm_cpumac_additional_cfg(lchip, TRUE, NULL));

    /*mac calendar*/
    for(dp = 0; dp < SYS_TMM_DP_NUM; dp++)
    {
        for(dp_txqm_id = 0; dp_txqm_id < SYS_TMM_TXQM_NUM_PER_DP; dp_txqm_id++)
        {
            hscs_idx = (0 == dp) ? (dp_txqm_id % 2) : (2 + dp_txqm_id % 2);
            SYS_CONDITION_CONTINUE(p_usw_datapath_master[lchip]->hscs_down_flag[SYS_TMM_IS_PCS_X16(dp_txqm_id) ? 0 : 1][hscs_idx]);
            CTC_ERROR_RETURN(sys_tmm_set_mac_calendar(lchip, dp, dp_txqm_id));
        }
    }

    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_DATAPATH, SYS_WB_APPID_DATAPATH_SUBID_MASTER,        1);
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_DATAPATH, SYS_WB_APPID_DATAPATH_SUBID_HSS_ATTRIBUTE, 1);
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT,     SYS_WB_APPID_PORT_SUBID_MAC_PROP,          1);

    return CTC_E_NONE;
}





#define  __TMM_MAC_ENABLE__

STATIC int32
_sys_tmm_mac_set_mcmac_x8_common_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 val32  = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd    = 0;
    uint32 index  = 0;
    uint32 step   = 0;
    uint32 factor = 0;
    uint32 array32[2] = {0};
    uint32 is_pcs_x16 = 0;
    uint32 pcs_x8_x16_index = 0;
    uint32 tb_idx = 0;
    uint16 inner_mac_id = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    McMacTxSoftReset_m         mac_tx_reset;
    McMacRxSoftReset_m         mac_rx_reset;
    McPcsX8LanesResetCtl_m     pcs_reset_ctl;
    McPcsX8LanesMcFecCfg_m     pcs_fec_cfg;
    McMacMacTxCfg_m            mac_cfg;
    McHataEnable_m             hata_en;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    /*************** (I) memset 0 ****************/
    sal_memset(&mac_tx_reset, 0, sizeof(McMacTxSoftReset_m));
    sal_memset(&mac_rx_reset, 0, sizeof(McMacRxSoftReset_m));
    sal_memset(&pcs_reset_ctl, 0, sizeof(McPcsX8LanesResetCtl_m));
    sal_memset(&pcs_fec_cfg, 0, sizeof(McPcsX8LanesMcFecCfg_m));
    sal_memset(&mac_cfg, 0, sizeof(McMacMacTxCfg_m));

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d, enable:%d\n", port_attr->mac_id, enable);

    /*************** (II) common info ****************/
    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
    if (is_pcs_x16)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% PCS x16 mode cannot use x8 config \n");
        return CTC_E_INVALID_CONFIG;
    }
    inner_mac_id = TXQM_INNER_MAC_ID(port_attr->mac_id);

    /*
      +----<-----<------<-------  enable
      |         MacTx  PcsTx
      |     +---->------>-------  disable
      |     |
     \|/   /|\
      |     |
      |     +--- <------<-------  disable
      |         MacRx  PcsRx
      +---->----->------>-------  enable
     */

    if (enable)   /* enable */
    {
        /*McHataTxChanMap_chanMap_f*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, port_attr->txqm_id, port_attr->multi_serdes_id[0] % SYS_TMM_PCS_X8_LANE_NUM, 
            McHataTxChanMap_chanMap_f, inner_mac_id));

        /*McHataTxPortMap_portMap_f*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_port_map(lchip, port_attr->txqm_id, 
            inner_mac_id, port_attr->multi_serdes_id[0] % 8));

        /*McHataEnable_cfgHataSgmiiMode_f*/
        index = DRV_INS(port_attr->txqm_id, 0);
        tbl_id = McHataEnable_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_en));

        fld_id = McHataEnable_cfgHataSgmiiMode_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val32, &hata_en);
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            val32 |= (1 << (port_attr->multi_serdes_id[0] % 8));
        }
        else
        {
            val32 &= ~(1 << (port_attr->multi_serdes_id[0] % 8));
        }
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &hata_en, port_attr->txqm_id, 0);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_en));

        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_en(lchip, lport, port_attr, SYS_DATAPATH_SERDES_DIR_TX, 1));

        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_TX, 0));

        {
            /*************** (III) McPcsX8LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX8LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX8LanesResetCtl_cfgTxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] &= ~(1 << (port_attr->pcs_idx % 8)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (III) McPcsX8LanesResetCtl end! ****************/
        }
        
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            /*************** (III) McPcsX8LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX8LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX8LanesResetCtl_cfgSgmiiPcsTxSoftRst_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] &= ~(1 << (port_attr->pcs_idx % 8)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (III) McPcsX8LanesResetCtl end! ****************/
        }
        
        if (SYS_DMPS_INACTIVE_NETWORK_PORT != port_attr->port_type)
        {
            /*************** (IV) McMacTxSoftReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(port_attr->txqm_id, 0);

            /* #2, read HW table */
            tbl_id = McMacTxSoftReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));

            fld_id = McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_tx_reset);
            if (inner_mac_id >= 32)
            {
                array32[1] &= ~(1 << (inner_mac_id % 8));
            }
            else
            {
                array32[0] &= ~(1 << inner_mac_id);
            }
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_tx_reset, port_attr->txqm_id, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));
            /*************** (IV) McMacTxSoftReset end! ****************/

            /* #1, calc index */
            index = DRV_INS(port_attr->txqm_id, 0);

            /* #2, read HW table: McMacMacTxCfg */
            tbl_id = McMacMacTxCfg_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));

            /* ##2.1. calc step */
            step = McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxSendEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f;
            factor = inner_mac_id;/* 0..39 per txqm */

            /* ##2.2. modify field value */
            /* ###2.2.1. */
            fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f + step*factor;
            val32 = 1;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &mac_cfg, port_attr->txqm_id, 0);

            /* #3, write HW table: McMacMacTxCfg*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));

            /*************** (V) McMacRxSoftReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(port_attr->txqm_id, 0);

            /* #2, read HW table */
            tbl_id = McMacRxSoftReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));

            fld_id = McMacRxSoftReset_cfgMcMacRxSoftReset_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_rx_reset);
            if (inner_mac_id >= 32)
            {
                array32[1] &= ~(1 << (inner_mac_id % 8));
            }
            else
            {
                array32[0] &= ~(1 << inner_mac_id);
            }
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_rx_reset, port_attr->txqm_id, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));
        }
        /*************** (V) McMacRxSoftReset end! ****************/

        /*McHataTxChanMap_rxChanMap_f*/
        if((CTC_CHIP_SERDES_SGMII_MODE==port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE==port_attr->pcs_mode))
        {
            tb_idx = port_attr->multi_serdes_id[0] % 8 + 16;
            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, port_attr->txqm_id, tb_idx, McHataTxChanMap_rxChanMap_f, 
                inner_mac_id));
        }
        tb_idx = port_attr->pcs_idx;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, port_attr->txqm_id, tb_idx, McHataTxChanMap_rxChanMap_f, 
            inner_mac_id));

        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_en(lchip, lport, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 1));

        /*McMacMiiRxCfg.cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault set 0*/
        if((CTC_CHIP_SERDES_SGMII_MODE != port_attr->pcs_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != port_attr->pcs_mode))
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_tx_force_fault(lchip, lport, 0));
        }

        if(0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold)
        {
            //CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 0));

            if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
                || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
            /*************** (III) McPcsX8LanesResetCtl start! ****************/
                /* #1, calc index */
                index = DRV_INS(pcs_x8_x16_index, 0);

                /* #2, read HW table */
                tbl_id = McPcsX8LanesResetCtl_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

                fld_id = McPcsX8LanesResetCtl_cfgSgmiiPcsRxSoftRst_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
                array32[0] &= ~(1 << (port_attr->pcs_idx % 8)) ;
                DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

                /* #3, write HW table*/
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (III) McPcsX8LanesResetCtl end! ****************/
            }
            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 0));

            /*************** (VI) McPcsX8LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX8LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX8LanesResetCtl_cfgRxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] &= ~(1 << (port_attr->pcs_idx % 8)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (VI) McPcsX8LanesResetCtl end! ****************/
        }
        /*************** (VII) McPcsX8LanesMcFecCfg start! ****************/
        /* #1, calc index */
        index = DRV_INS(pcs_x8_x16_index, 0);

        /* #2, read HW table */
        tbl_id = McPcsX8LanesMcFecCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fec_cfg));

        fld_id = McPcsX8LanesMcFecCfg_cfgSoftRstRxMcFec_f;
        array32[0] = 0;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_fec_cfg, pcs_x8_x16_index, 0);

        fld_id = McPcsX8LanesMcFecCfg_cfgSoftRstTxMcFec_f;
        array32[0] = 0;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_fec_cfg, pcs_x8_x16_index, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fec_cfg));
        /*************** (VII) McPcsX8LanesMcFecCfg end! ****************/
    }
    else     /* disable */
    {
        if(0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold)
        {
            if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
                || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
                /*************** (III) McPcsX8LanesResetCtl start! ****************/
                /* #1, calc index */
                index = DRV_INS(pcs_x8_x16_index, 0);

                /* #2, read HW table */
                tbl_id = McPcsX8LanesResetCtl_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

                fld_id = McPcsX8LanesResetCtl_cfgSgmiiPcsRxSoftRst_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
                array32[0] |= (1 << (port_attr->pcs_idx % 8)) ;
                DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

                /* #3, write HW table*/
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
                /*************** (III) McPcsX8LanesResetCtl end! ****************/
            }

            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 1));
            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_en(lchip, lport, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 0));
            /*************** (III) McPcsX8LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX8LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX8LanesResetCtl_cfgRxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] |= (1 << (port_attr->pcs_idx % 8)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (III) McPcsX8LanesResetCtl end! ****************/
        }

        /*McMacMiiRxCfg.cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault set 1*/
        if((CTC_CHIP_SERDES_SGMII_MODE != port_attr->pcs_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != port_attr->pcs_mode))
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_tx_force_fault(lchip, lport, CTC_PORT_FAULT_FORCE));
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_wait_rx_buf_empty(lchip, port_attr->mac_id));

        if (SYS_DMPS_INACTIVE_NETWORK_PORT != port_attr->port_type)
        {
            /*************** (IV) McMacRxSoftReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(port_attr->txqm_id, 0);

            /* #2, read HW table */
            tbl_id = McMacRxSoftReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));

            fld_id = McMacRxSoftReset_cfgMcMacRxSoftReset_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_rx_reset);
            if (inner_mac_id >= 32)
            {
                array32[1] |= (1 << (inner_mac_id % 8));
            }
            else
            {
                array32[0] |= (1 << inner_mac_id);
            }
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_rx_reset, port_attr->txqm_id, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));
            /*************** (IV) McMacRxSoftReset end! ****************/


            /* #1, calc index */
            index = DRV_INS(port_attr->txqm_id, 0);

            /* #2, read HW table: McMacMacTxCfg */
            tbl_id = McMacMacTxCfg_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));

            /* ##2.1. calc step */
            step = McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxSendEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f;
            factor = inner_mac_id;/* 0..39 per txqm */

            /* ##2.2. modify field value */
            /* ###2.2.1. */
            fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f + step*factor;
            val32 = 0;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &mac_cfg, port_attr->txqm_id, 0);

            /* #3, write HW table: McMacMacTxCfg*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));


            /*************** (IV) McMacTxSoftReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(port_attr->txqm_id, 0);

            /* #2, read HW table */
            tbl_id = McMacTxSoftReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));

            fld_id = McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_tx_reset);
            if (inner_mac_id >= 32)
            {
                array32[1] |= (1 << (inner_mac_id % 8));
            }
            else
            {
                array32[0] |= (1 << inner_mac_id);
            }
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_tx_reset, port_attr->txqm_id, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));
            /*************** (IV) McMacTxSoftReset end! ****************/
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_TX, 1));

        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_en(lchip, lport, port_attr, SYS_DATAPATH_SERDES_DIR_TX, 0));
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            /*************** (III) McPcsX8LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX8LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX8LanesResetCtl_cfgSgmiiPcsTxSoftRst_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] |= (1 << (port_attr->pcs_idx % 8)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (III) McPcsX8LanesResetCtl end! ****************/
        }

        {
            /*************** (VI) McPcsX8LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX8LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX8LanesResetCtl_cfgTxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] |= (1 << (port_attr->pcs_idx % 8)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (VI) McPcsX8LanesResetCtl end! ****************/
        }
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_qsgmii_quad_mac_en(uint8 lchip, uint16 lport, uint8 en_upt_flag, uint8 enable, uint8* p_quad_mac_en)
{
    uint8  internal_mac_idx;
    uint16 mac_id_base;
    uint16 mac_id_delta;
    uint16 lport_tmp;
    uint8  port_mac_en = FALSE;
    uint8  quad_mac_en = FALSE;
    sys_datapath_lport_attr_t* port_attr = NULL;
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if((CTC_CHIP_SERDES_QSGMII_MODE != port_attr->pcs_mode) || !SYS_TMM_IS_MAC_SUPPORT_QSGMII(port_attr->mac_id))
    {
        SYS_USW_VALID_PTR_WRITE(p_quad_mac_en, FALSE);
        return CTC_E_NONE;
    }
    SYS_TMM_GET_QSGMII_INTERNAL_MAC_IDX(port_attr->mac_id, internal_mac_idx);
    SYS_CONDITION_RETURN(SYS_TMM_USELESS_ID8 == internal_mac_idx, CTC_E_INVALID_PARAM);
    mac_id_base = port_attr->mac_id - internal_mac_idx;

    for(mac_id_delta = 0; mac_id_delta < 4; mac_id_delta++)
    {
        if((!en_upt_flag) && (mac_id_delta == internal_mac_idx))
        {
            port_mac_en = enable;
        }
        else
        {
            lport_tmp = sys_usw_datapath_get_lport_with_mac(lchip, mac_id_base+mac_id_delta);
            port_mac_en = p_usw_mac_master[lchip]->mac_prop[lport_tmp].port_mac_en;
        }
        
        if(port_mac_en)
        {
            quad_mac_en = TRUE;
            break;
        }
    }
    
    SYS_USW_VALID_PTR_WRITE(p_quad_mac_en, quad_mac_en);
    return CTC_E_NONE;
}


STATIC int32
_sys_tmm_mac_set_mcmac_x16_qsgmii_en(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr, uint8 enable)
{
    //uint32 addr32 = 0;
    uint32 val32  = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd    = 0;
    uint32 index  = 0;
    uint32 step   = 0;
    uint32 factor = 0;
    uint32 array32[2]  = {0};
    uint32 is_pcs_x16 = 0;
    uint32 pcs_x8_x16_index = 0;
    uint8  quad_mac_en;
    uint16 inner_mac_id = 0;
    McMacTxSoftReset_m         mac_tx_reset;
    McMacRxSoftReset_m         mac_rx_reset;
    McPcsX16LanesResetCtl_m     pcs_reset_ctl;
    McPcsX16LanesMcFecCfg_m     pcs_fec_cfg;
    McMacMacTxCfg_m             mac_cfg;
    McPcsX16LanesQsgmiiReset_m  pcs_qsgmii_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    //TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d\n", __FUNCTION__, __LINE__);

    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    /*************** (I) memset 0 ****************/
    /*sal_memset(&mac_tx_reset, 0, sizeof(McMacTxSoftReset_m));*/
    sal_memset(&mac_rx_reset, 0, sizeof(McMacRxSoftReset_m));
    sal_memset(&pcs_reset_ctl, 0, sizeof(McPcsX16LanesResetCtl_m));
    sal_memset(&pcs_fec_cfg, 0, sizeof(McPcsX16LanesMcFecCfg_m));
    sal_memset(&mac_cfg, 0, sizeof(McMacMacTxCfg_m));
    sal_memset(&pcs_qsgmii_rst, 0, sizeof(McPcsX16LanesQsgmiiReset_m));

    /*************** (II) common info ****************/
    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
    if (!is_pcs_x16)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% PCS x8 mode cannot use x16 config \n");
        return CTC_E_INVALID_CONFIG;
    }
    inner_mac_id = TXQM_INNER_MAC_ID(port_attr->mac_id);

    if (enable)   /* enable */
    {
        index = DRV_INS(pcs_x8_x16_index, 0);

        /* #2, read HW table */
        tbl_id = McPcsX16LanesQsgmiiReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

        /* ##2.1. calc step */
        step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_resetCore_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_resetCore_f;
        factor = port_attr->pcs_idx % 8;

        /* ##2.2. modify field value */
        /* ###2.2.1. */
        fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_resetCore_f + step*factor;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst);
        array32[0] &= ~(1 << (port_attr->mac_id % 4)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst, pcs_x8_x16_index, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

        /*************** (III) McPcsX16LanesResetCtl start! ****************/
        /* #1, calc index */
        index = DRV_INS(pcs_x8_x16_index, 0);

        /* #2, read HW table */
        tbl_id = McPcsX16LanesResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

        fld_id = McPcsX16LanesResetCtl_cfgTxSoftRstChanBmp_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
        array32[0] &= ~(1 << (port_attr->pcs_idx % 16)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
        /*************** (III) McPcsX16LanesResetCtl end! ****************/

        /*************** (III) McPcsX16LanesQsgmiiReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(pcs_x8_x16_index, 0);

        /* #2, read HW table */
        tbl_id = McPcsX16LanesQsgmiiReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

        step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPcsTxRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsTxRst_f;
        factor = port_attr->pcs_idx % 8;

        /* ##2.2. modify field value */
        /* ###2.2.1. */
        fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsTxRst_f + step*factor;
        array32[0] = 0;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst, pcs_x8_x16_index, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));
        /*************** (III) McPcsX16LanesQsgmiiReset end! ****************/
        
        /*************** (III) McPcsX16LanesQsgmiiReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(pcs_x8_x16_index, 0);

        /* #2, read HW table */
        tbl_id = McPcsX16LanesQsgmiiReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

        step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPmaRxRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPmaRxRst_f;
        factor = port_attr->pcs_idx % 8;

        /* ##2.2. modify field value */
        /* ###2.2.1. */
        fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPmaRxRst_f + step*factor;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst);
        array32[0] = 0;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst, pcs_x8_x16_index, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));
        /*************** (III) McPcsX16LanesQsgmiiReset end! ****************/
        
        /*************** (VI) McPcsX16LanesResetCtl start! ****************/
        /* #1, calc index */
        index = DRV_INS(pcs_x8_x16_index, 0);

        /* #2, read HW table */
        tbl_id = McPcsX16LanesResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

        fld_id = McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
        array32[0] &= ~(1 << (port_attr->pcs_idx % 16)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
        /*************** (VI) McPcsX16LanesResetCtl end! ****************/

        /*************** (III) McPcsX16LanesQsgmiiReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(pcs_x8_x16_index, 0);

        /* #2, read HW table */
        tbl_id = McPcsX16LanesQsgmiiReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

        /* ##2.1. calc step */
        step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPcsTxSoftRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsTxSoftRst_f;
        factor = port_attr->pcs_idx % 8;

        /* ##2.2. modify field value */
        /* ###2.2.1. */
        fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsTxSoftRst_f + step*factor;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst);
        array32[0] &= ~(1 << (port_attr->mac_id % 4)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst, pcs_x8_x16_index, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));
        /*************** (III) McPcsX16LanesQsgmiiReset end! ****************/

        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table: McMacMacTxCfg */
        tbl_id = McMacMacTxCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));

        /* ##2.1. calc step */
        step = McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxSendEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f;
        factor = inner_mac_id;/* 0..39 per txqm */

        /* ##2.2. modify field value */
        /* ###2.2.1. */
        fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f + step*factor;
        val32 = 1;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &mac_cfg, port_attr->txqm_id, 0);

        /* #3, write HW table: McMacMacTxCfg*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));

        /*************** (IV) McMacTxSoftReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table */
        tbl_id = McMacTxSoftReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));

        fld_id = McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_tx_reset);
        if (inner_mac_id >= 32)
        {
            array32[1] &= ~(1 << (inner_mac_id % 8));
        }
        else
        {
            array32[0] &= ~(1 << inner_mac_id);
        }
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_tx_reset, port_attr->txqm_id, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));
        /*************** (IV) McMacTxSoftReset end! ****************/
        
        /*************** (III) McPcsX16LanesQsgmiiReset start! ****************/
        if(0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold)
        {
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesQsgmiiReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

            /* ##2.1. calc step */
            step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPcsRxSoftRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsRxSoftRst_f;
            factor = port_attr->pcs_idx % 8;

            /* ##2.2. modify field value */
            /* ###2.2.1. */
            fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsRxSoftRst_f + step*factor;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst);
            array32[0] &= ~(1 << (port_attr->mac_id % 4)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));
        }
        /*************** (III) McPcsX16LanesQsgmiiReset end! ****************/

        /*************** (V) McMacRxSoftReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table */
        tbl_id = McMacRxSoftReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));

        fld_id = McMacRxSoftReset_cfgMcMacRxSoftReset_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_rx_reset);
        if (inner_mac_id >= 32)
        {
            array32[1] &= ~(1 << (inner_mac_id % 8));
        }
        else
        {
            array32[0] &= ~(1 << inner_mac_id);
        }
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_rx_reset, port_attr->txqm_id, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));
        /*************** (V) McMacRxSoftReset end! ****************/
        
        /*************** (VII) McPcsX16LanesMcFecCfg start! ****************/
        /* #1, calc index */
        index = DRV_INS(pcs_x8_x16_index, 0);

        /* #2, read HW table */
        tbl_id = McPcsX16LanesMcFecCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fec_cfg));

        fld_id = McPcsX16LanesMcFecCfg_cfgSoftRstRxMcFec_f;
        array32[0] = 0;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_fec_cfg, pcs_x8_x16_index, 0);

        fld_id = McPcsX16LanesMcFecCfg_cfgSoftRstTxMcFec_f;
        array32[0] = 0;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_fec_cfg, pcs_x8_x16_index, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fec_cfg));
        /*************** (VII) McPcsX16LanesMcFecCfg end! ****************/
    }
    else     /* disable */
    {
        _sys_tmm_mac_get_qsgmii_quad_mac_en(lchip, lport, FALSE, enable, &quad_mac_en);

        /*************** (III) McPcsX16LanesQsgmiiReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(pcs_x8_x16_index, 0);

        /* #2, read HW table */
        tbl_id = McPcsX16LanesQsgmiiReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

        /* ##2.1. calc step */
        step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPcsTxSoftRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsTxSoftRst_f;
        factor = port_attr->pcs_idx % 8;

        /* ##2.2. modify field value */
        /* ###2.2.1. */
        fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsTxSoftRst_f + step*factor;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst);
        array32[0] |= (1 << (port_attr->mac_id % 4)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst, pcs_x8_x16_index, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));
        /*************** (III) McPcsX16LanesQsgmiiReset end! ****************/

        /*************** (IV) McMacTxSoftReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table */
        tbl_id = McMacTxSoftReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));

        fld_id = McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_tx_reset);
        if (inner_mac_id >= 32)
        {
            array32[1] |= (1 << (inner_mac_id % 8));
        }
        else
        {
            array32[0] |= (1 << inner_mac_id);
        }
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_tx_reset, port_attr->txqm_id, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));
        /*************** (IV) McMacTxSoftReset end! ****************/

        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table: McMacMacTxCfg */
        tbl_id = McMacMacTxCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));

        /* ##2.1. calc step */
        step = McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxSendEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f;
        factor = inner_mac_id;/* 0..39 per txqm */

        /* ##2.2. modify field value */
        /* ###2.2.1. */
        fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f + step*factor;
        val32 = 0;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &mac_cfg, port_attr->txqm_id, 0);

        /* #3, write HW table: McMacMacTxCfg*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));

        /*************** (III) McPcsX16LanesQsgmiiReset start! ****************/
        if(0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold)
        {
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesQsgmiiReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));
            /* ##2.1. calc step */
            step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPcsRxSoftRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsRxSoftRst_f;
            factor = port_attr->pcs_idx % 8;

            /* ##2.2. modify field value */
            /* ###2.2.1. */
            fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsRxSoftRst_f + step*factor;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst);
            array32[0] |= (1 << (port_attr->mac_id % 4)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));
        }
        /*************** (III) McPcsX16LanesQsgmiiReset end! ****************/

        /*************** (IV) McMacRxSoftReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table */
        tbl_id = McMacRxSoftReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));

        fld_id = McMacRxSoftReset_cfgMcMacRxSoftReset_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_rx_reset);
        if (inner_mac_id >= 32)
        {
            array32[1] |= (1 << (inner_mac_id % 8));
        }
        else
        {
            array32[0] |= (1 << inner_mac_id);
        }
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_rx_reset, port_attr->txqm_id, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));
        /*************** (IV) McMacRxSoftReset end! ****************/

        if(!quad_mac_en)
        {
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesQsgmiiReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

            step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPcsTxRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsTxRst_f;
            factor = port_attr->pcs_idx % 8;

            /* ##2.2. modify field value */
            /* ###2.2.1. */
            fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsTxRst_f + step*factor;
            array32[0] = 1;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));
            
            /*************** (VI) McPcsX16LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX16LanesResetCtl_cfgTxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] |= (1 << (port_attr->pcs_idx % 16)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (VI) McPcsX16LanesResetCtl end! ****************/
            
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesQsgmiiReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

            /* ##2.1. calc step */
            step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_resetCore_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_resetCore_f;
            factor = port_attr->pcs_idx % 8;

            /* ##2.2. modify field value */
            /* ###2.2.1. */
            fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_resetCore_f + step*factor;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst);
            array32[0] &= ~(1 << (port_attr->mac_id % 4)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

            /*************** (III) McPcsX16LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] |= (1 << (port_attr->pcs_idx % 16)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (III) McPcsX16LanesResetCtl end! ****************/
            /*************** (III) McPcsX16LanesQsgmiiReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesQsgmiiReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));

            /* ##2.1. calc step */
            step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPmaRxRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPmaRxRst_f;
            factor = port_attr->pcs_idx % 8;

            /* ##2.2. modify field value */
            /* ###2.2.1. */
            fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPmaRxRst_f + step*factor;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst);
            array32[0] = 1;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_qsgmii_rst, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_qsgmii_rst));
        }
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_mac_set_mcmac_x16_common_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 val32  = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd    = 0;
    uint32 index  = 0;
    uint32 step   = 0;
    uint32 factor = 0;
    uint32 array32[2]  = {0};
    uint32 is_pcs_x16 = 0;
    uint32 pcs_x8_x16_index = 0;
    uint32 tb_idx = 0;
    uint16 inner_mac_id = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    McMacTxSoftReset_m         mac_tx_reset;
    McMacRxSoftReset_m         mac_rx_reset;
    McPcsX16LanesResetCtl_m     pcs_reset_ctl;
    McPcsX16LanesMcFecCfg_m     pcs_fec_cfg;
    McMacMacTxCfg_m             mac_cfg;

    McPcsX16LanesSgmiiReset_m   pcs_sgmii_rst;
    McHataEnable_m             hata_en;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    //TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d\n", __FUNCTION__, __LINE__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    if (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mcmac_x16_qsgmii_en(lchip, lport, port_attr, enable));
        return CTC_E_NONE;
    }

    /*************** (I) memset 0 ****************/
    /*sal_memset(&mac_tx_reset, 0, sizeof(McMacTxSoftReset_m));*/
    sal_memset(&mac_rx_reset, 0, sizeof(McMacRxSoftReset_m));
    sal_memset(&pcs_reset_ctl, 0, sizeof(McPcsX16LanesResetCtl_m));
    sal_memset(&pcs_fec_cfg, 0, sizeof(McPcsX16LanesMcFecCfg_m));
    sal_memset(&mac_cfg, 0, sizeof(McMacMacTxCfg_m));
    sal_memset(&pcs_sgmii_rst, 0, sizeof(McPcsX16LanesSgmiiReset_m));

    /*************** (II) common info ****************/
    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
    if (!is_pcs_x16)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% PCS x8 mode cannot use x16 config \n");
        return CTC_E_INVALID_CONFIG;
    }
    inner_mac_id = TXQM_INNER_MAC_ID(port_attr->mac_id);


    /*
      +----<-----<------<-------  enable
      |         MacTx  PcsTx
      |     +---->------>-------  disable
      |     |
     \|/   /|\
      |     |
      |     +--- <------<-------  disable
      |         MacRx  PcsRx
      +---->----->------>-------  enable
     */

    if (enable)   /* enable */
    {
        /*McHataTxChanMap_chanMap_f*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, port_attr->txqm_id, port_attr->multi_serdes_id[0] % SYS_TMM_PCS_X16_LANE_NUM, 
            McHataTxChanMap_chanMap_f, inner_mac_id));

        /*McHataTxPortMap_portMap_f*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_port_map(lchip, port_attr->txqm_id, 
            inner_mac_id, port_attr->multi_serdes_id[0] % 16));

        /*McHataEnable_cfgHataSgmiiMode_f*/
        index = DRV_INS(port_attr->txqm_id, 0);
        tbl_id = McHataEnable_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_en));

        fld_id = McHataEnable_cfgHataSgmiiMode_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val32, &hata_en);
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            val32 |= (1 << (port_attr->multi_serdes_id[0] % 16));
        }
        else
        {
            val32 &= ~(1 << (port_attr->multi_serdes_id[0] % 16));
        }
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &hata_en, port_attr->txqm_id, 0);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hata_en));

        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_en(lchip, lport, port_attr, SYS_DATAPATH_SERDES_DIR_TX, 1));

        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_TX, 0));
        
        {
            /*************** (III) McPcsX16LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX16LanesResetCtl_cfgTxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] &= ~(1 << (port_attr->pcs_idx % 16)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (III) McPcsX16LanesResetCtl end! ****************/
        }

        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            /*************** (III) McPcsX16LanesSgmiiReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesSgmiiReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_sgmii_rst));

            fld_id = McPcsX16LanesSgmiiReset_cfgSgmiiPcsTxSoftRst_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_sgmii_rst);
            array32[0] &= ~(1 << (port_attr->pcs_idx % 16)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_sgmii_rst, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_sgmii_rst));
            /*************** (III) McPcsX16LanesSgmiiReset end! ****************/
        }

        /*************** (IV) McMacTxSoftReset start! ****************/
        /*************** (IV) McMacTxSoftReset end! ****************/

        /*************** (IV) McMacTxSoftReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table */
        tbl_id = McMacTxSoftReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));

        fld_id = McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_tx_reset);
        if (inner_mac_id >= 32)
        {
            array32[1] &= ~(1 << (inner_mac_id % 8));
        }
        else
        {
            array32[0] &= ~(1 << inner_mac_id);
        }
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_tx_reset, port_attr->txqm_id, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));
        /*************** (IV) McMacTxSoftReset end! ****************/

        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table: McMacMacTxCfg */
        tbl_id = McMacMacTxCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));

        /* ##2.1. calc step */
        step = McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxSendEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f;
        factor = inner_mac_id;/* 0..39 per txqm */

        /* ##2.2. modify field value */
        /* ###2.2.1. */
        fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f + step*factor;
        val32 = 1;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &mac_cfg, port_attr->txqm_id, 0);

        /* #3, write HW table: McMacMacTxCfg*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));
        

        /*************** (V) McMacRxSoftReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table */
        tbl_id = McMacRxSoftReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));

        fld_id = McMacRxSoftReset_cfgMcMacRxSoftReset_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_rx_reset);
        if (inner_mac_id >= 32)
        {
            array32[1] &= ~(1 << (inner_mac_id % 8));
        }
        else
        {
            array32[0] &= ~(1 << inner_mac_id);
        }
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_rx_reset, port_attr->txqm_id, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));

        /*McHataTxChanMap_rxChanMap_f*/
        tb_idx = port_attr->pcs_idx;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, port_attr->txqm_id, tb_idx, McHataTxChanMap_rxChanMap_f, 
            inner_mac_id));
        if((CTC_CHIP_SERDES_SGMII_MODE==port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE==port_attr->pcs_mode))
        {
            tb_idx = port_attr->multi_serdes_id[0] % 16 + 16;
            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, port_attr->txqm_id, tb_idx, McHataTxChanMap_rxChanMap_f, 
                inner_mac_id));
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_en(lchip, lport, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 1));

        /*McMacMiiRxCfg.cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault set 0*/
        if((CTC_CHIP_SERDES_SGMII_MODE != port_attr->pcs_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != port_attr->pcs_mode))
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_tx_force_fault(lchip, lport, 0));
        }

        /*************** (V) McMacRxSoftReset end! ****************/
        if(0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold)
        {
            //CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 0));

            if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
                || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
                /*************** (VI) McPcsX16LanesSgmiiReset start! ****************/
                    /* #1, calc index */
                    index = DRV_INS(pcs_x8_x16_index, 0);

                    /* #2, read HW table */
                    tbl_id = McPcsX16LanesSgmiiReset_t;
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_sgmii_rst));

                    fld_id = McPcsX16LanesSgmiiReset_cfgSgmiiPcsRxSoftRst_f;
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_sgmii_rst);
                    array32[0] &= ~(1 << (port_attr->pcs_idx % 16)) ;
                    DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_sgmii_rst, pcs_x8_x16_index, 0);

                    /* #3, write HW table*/
                    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_sgmii_rst));
                /*************** (VI) McPcsX16LanesSgmiiReset end! ****************/
            }
            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 0));

            /*************** (VI) McPcsX16LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] &= ~(1 << (port_attr->pcs_idx % 16)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (VI) McPcsX16LanesResetCtl end! ****************/
        }
        
        /*************** (VII) McPcsX16LanesMcFecCfg start! ****************/
        /* #1, calc index */
        index = DRV_INS(pcs_x8_x16_index, 0);

        /* #2, read HW table */
        tbl_id = McPcsX16LanesMcFecCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fec_cfg));

        fld_id = McPcsX16LanesMcFecCfg_cfgSoftRstRxMcFec_f;
        array32[0] = 0;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_fec_cfg, pcs_x8_x16_index, 0);

        fld_id = McPcsX16LanesMcFecCfg_cfgSoftRstTxMcFec_f;
        array32[0] = 0;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_fec_cfg, pcs_x8_x16_index, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_fec_cfg));
        /*************** (VII) McPcsX16LanesMcFecCfg end! ****************/
    }
    else     /* disable */
    {
        if(0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold)
        {
            if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
                || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
            /*************** (VI) McPcsX16LanesSgmiiReset start! ****************/
                /* #1, calc index */
                index = DRV_INS(pcs_x8_x16_index, 0);

                /* #2, read HW table */
                tbl_id = McPcsX16LanesSgmiiReset_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_sgmii_rst));

                fld_id = McPcsX16LanesSgmiiReset_cfgSgmiiPcsRxSoftRst_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_sgmii_rst);
                array32[0] |= (1 << (port_attr->pcs_idx % 16)) ;
                DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_sgmii_rst, pcs_x8_x16_index, 0);

                /* #3, write HW table*/
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_sgmii_rst));
            /*************** (VI) McPcsX16LanesSgmiiReset end! ****************/
            }

            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 1));
            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_en(lchip, lport, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 0));
            /*************** (III) McPcsX16LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] |= (1 << (port_attr->pcs_idx % 16)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (III) McPcsX16LanesResetCtl end! ****************/
        }

        /*McMacMiiRxCfg.cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault set 1*/
        if((CTC_CHIP_SERDES_SGMII_MODE != port_attr->pcs_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != port_attr->pcs_mode))
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_tx_force_fault(lchip, lport, CTC_PORT_FAULT_FORCE));
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_wait_rx_buf_empty(lchip, port_attr->mac_id));
        
        /*************** (IV) McMacRxSoftReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table */
        tbl_id = McMacRxSoftReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));

        fld_id = McMacRxSoftReset_cfgMcMacRxSoftReset_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_rx_reset);
        if (inner_mac_id >= 32)
        {
            array32[1] |= (1 << (inner_mac_id % 8));
        }
        else
        {
            array32[0] |= (1 << inner_mac_id);
        }
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_rx_reset, port_attr->txqm_id, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));
        /*************** (IV) McMacRxSoftReset end! ****************/
        

        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table: McMacMacTxCfg */
        tbl_id = McMacMacTxCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));

        /* ##2.1. calc step */
        step = McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxSendEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f;
        factor = inner_mac_id;/* 0..39 per txqm */

        /* ##2.2. modify field value */
        /* ###2.2.1. */
        fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f + step*factor;
        val32 = 0;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &mac_cfg, port_attr->txqm_id, 0);

        /* #3, write HW table: McMacMacTxCfg*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));


        /*************** (IV) McMacTxSoftReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(port_attr->txqm_id, 0);

        /* #2, read HW table */
        tbl_id = McMacTxSoftReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));

        fld_id = McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_tx_reset);
        if (inner_mac_id >= 32)
        {
            array32[1] |= (1 << (inner_mac_id % 8));
        }
        else
        {
            array32[0] |= (1 << inner_mac_id);
        }
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_tx_reset, port_attr->txqm_id, 0);

        /* #3, write HW table*/
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));
        /*************** (IV) McMacTxSoftReset end! ****************/

        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_TX, 1));

        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_en(lchip, lport, port_attr, SYS_DATAPATH_SERDES_DIR_TX, 0));
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            /*************** (VI) McPcsX16LanesSgmiiReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesSgmiiReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_sgmii_rst));

            fld_id = McPcsX16LanesSgmiiReset_cfgSgmiiPcsTxSoftRst_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_sgmii_rst);
            array32[0] |= (1 << (port_attr->pcs_idx % 16)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_sgmii_rst, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_sgmii_rst));
            /*************** (VI) McPcsX16LanesSgmiiReset end! ****************/
        }

        {
            /*************** (VI) McPcsX16LanesResetCtl start! ****************/
            /* #1, calc index */
            index = DRV_INS(pcs_x8_x16_index, 0);

            /* #2, read HW table */
            tbl_id = McPcsX16LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));

            fld_id = McPcsX16LanesResetCtl_cfgTxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl);
            array32[0] |= (1 << (port_attr->pcs_idx % 16)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_reset_ctl, pcs_x8_x16_index, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_reset_ctl));
            /*************** (VI) McPcsX16LanesResetCtl end! ****************/
        }
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_flexe_mac_en(uint8 lchip, uint16 mac_id, uint8 dir, uint8* p_enable)
{
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd    = 0;
    uint32 index  = 0;
    uint8 txqm_id = 0;
    uint8 reset = 0;
    uint16 inner_mac_id = TXQM_INNER_MAC_ID(mac_id);
    uint32 array32[2]  = {0};
    McMacTxSoftReset_m         mac_tx_reset;
    McMacRxSoftReset_m         mac_rx_reset;
    McMacMacTxCfg_m            mac_cfg;
    McMacReserved_m            mac_rsv;
    McMacPcsCfg_m              mac_pcs_cfg;

    /*************** (I) memset 0 ****************/
    sal_memset(&mac_tx_reset, 0, sizeof(McMacTxSoftReset_m));
    sal_memset(&mac_rx_reset, 0, sizeof(McMacRxSoftReset_m));
    sal_memset(&mac_cfg, 0, sizeof(McMacMacTxCfg_m));
    sal_memset(&mac_rsv, 0, sizeof(McMacReserved_m));
    sal_memset(&mac_pcs_cfg, 0, sizeof(McMacPcsCfg_m));
    
    /*************** (II) common info ****************/

    /*
      +----<-----<------<-------  enable
      |         MacTx  PcsTx
      |     +---->------>-------  disable
      |     |
     \|/   /|\
      |     |
      |     +--- <------<-------  disable
      |         MacRx  PcsRx
      +---->----->------>-------  enable
     */

    txqm_id = mac_id / SYS_TMM_MAX_MAC_NUM_PER_TXQM;
   
    if (SYS_FLEXE_DIR_TX == dir)
    {
        /*************** (IV) McMacTxSoftReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(txqm_id, 0);

        /* #2, read HW table */
        tbl_id = McMacTxSoftReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));

        fld_id = McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_tx_reset);
        if (inner_mac_id >= 32)
        {
            reset = (array32[1] >> (inner_mac_id % 8)) & 0x1;
        }
        else
        {
            reset = (array32[0] >> inner_mac_id) & 0x1;
        }
        /*************** (IV) McMacTxSoftReset end! ****************/
    }
    else   /* SYS_FLEXE_DIR_RX */
    {
        /*************** (IV) McMacRxSoftReset start! ****************/
        /* #1, calc index */
        index = DRV_INS(txqm_id, 0);

        /* #2, read HW table */
        tbl_id = McMacRxSoftReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));

        fld_id = McMacRxSoftReset_cfgMcMacRxSoftReset_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_rx_reset);
        if (inner_mac_id >= 32)
        {
            reset = (array32[1] >> (inner_mac_id % 8)) & 0x1;
        }
        else
        {
            reset = (array32[0] >> inner_mac_id) & 0x1;
        }
        /*************** (IV) McMacRxSoftReset end! ****************/
    }

    *p_enable = !reset;
    
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_flexe_mac_en(uint8 lchip, uint16 mac_id, uint8 dir, uint8 enable)
{
    uint32 val32  = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd    = 0;
    uint32 index  = 0;
    uint32 step   = 0;
    uint32 factor = 0;
    uint8 txqm_id = 0;
    uint16 inner_mac_id = 0;
    uint32 array32[2]  = {0};
    McMacTxSoftReset_m         mac_tx_reset;
    McMacRxSoftReset_m         mac_rx_reset;
    McMacMacTxCfg_m            mac_cfg;
    McMacReserved_m            mac_rsv;
    McMacPcsCfg_m              mac_pcs_cfg;

    /*************** (I) memset 0 ****************/
    sal_memset(&mac_tx_reset, 0, sizeof(McMacTxSoftReset_m));
    sal_memset(&mac_rx_reset, 0, sizeof(McMacRxSoftReset_m));
    sal_memset(&mac_cfg, 0, sizeof(McMacMacTxCfg_m));
    sal_memset(&mac_rsv, 0, sizeof(McMacReserved_m));
    sal_memset(&mac_pcs_cfg, 0, sizeof(McMacPcsCfg_m));
    
    /*************** (II) common info ****************/

    /*
      +----<-----<------<-------  enable
      |         MacTx  PcsTx
      |     +---->------>-------  disable
      |     |
     \|/   /|\
      |     |
      |     +--- <------<-------  disable
      |         MacRx  PcsRx
      +---->----->------>-------  enable
     */

    txqm_id = mac_id / SYS_TMM_MAX_MAC_NUM_PER_TXQM;
    inner_mac_id = TXQM_INNER_MAC_ID(mac_id);

    if (SYS_FLEXE_DIR_TX == dir)
    {
        if (enable)   /* enable */
        {
            /*************** (IV) McMacTxSoftReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(txqm_id, 0);

            /* #2, read HW table */
            tbl_id = McMacTxSoftReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));

            fld_id = McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_tx_reset);
            if (inner_mac_id >= 32)
            {
                array32[1] &= ~(1 << (inner_mac_id % 8));
            }
            else
            {
                array32[0] &= ~(1 << inner_mac_id);
            }
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_tx_reset, txqm_id, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));
            /*************** (IV) McMacTxSoftReset end! ****************/


            /*************** (V) McMacMacTxCfg start! ****************/
            /* #1, calc index */
            index = DRV_INS(txqm_id, 0);

            /* #2, read HW table: McMacMacTxCfg */
            tbl_id = McMacMacTxCfg_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));

            /* ##2.1. calc step */
            step = McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxSendEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f;
            factor = inner_mac_id;/* 0..39 per txqm */

            /* ##2.2. modify field value */
            /* ###2.2.1. */
            fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxSendEn_f + step*factor;
            val32 = 1;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &mac_cfg, txqm_id, 0);

            /* #3, write HW table: McMacMacTxCfg*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_cfg));
            /*************** (V) McMacMacTxCfg end! ****************/
        }
        else     /* disable */
        {
            /*************** (IV) McMacTxSoftReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(txqm_id, 0);

            /* #2, read HW table */
            tbl_id = McMacTxSoftReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));

            fld_id = McMacTxSoftReset_cfgMcMacMiiTxSoftReset_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_tx_reset);
            if (inner_mac_id >= 32)
            {
                array32[1] |= (1 << (inner_mac_id % 8));
            }
            else
            {
                array32[0] |= (1 << inner_mac_id);
            }
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_tx_reset, txqm_id, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_reset));
            /*************** (IV) McMacTxSoftReset end! ****************/
        }
    }
    else   /* SYS_FLEXE_DIR_RX */
    {
        if (enable)   /* enable */
        {            
            /*************** (VII) McMacRxSoftReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(txqm_id, 0);

            /* #2, read HW table */
            tbl_id = McMacRxSoftReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));

            fld_id = McMacRxSoftReset_cfgMcMacRxSoftReset_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_rx_reset);
            if (inner_mac_id >= 32)
            {
                array32[1] &= ~(1 << (inner_mac_id % 8));
            }
            else
            {
                array32[0] &= ~(1 << inner_mac_id);
            }
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_rx_reset, txqm_id, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));
            /*************** (VII) McMacRxSoftReset end! ****************/

            /*************** (VIII) McMacReserved start! ****************/
            /* #1, calc index */
            index = DRV_INS(txqm_id, 0);

            /* #2, read HW table */
            tbl_id = McMacReserved_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rsv));
            
            
            if (inner_mac_id < 32)
            {
                fld_id = McMacReserved_mcMacReserved_0_reserved_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &mac_rsv);
                array32[0] &= ~(1 << inner_mac_id);
            }
            else
            {
                fld_id = McMacReserved_mcMacReserved_1_reserved_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &mac_rsv);
                array32[0] &= ~(1 << (inner_mac_id % 8));
            }
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &mac_rsv, txqm_id, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rsv));
            /*************** (VIII) McMacReserved end! ****************/

            /*************** (VI) McMacPcsCfg start! ****************/
            /* #1, calc index */
            index = DRV_INS(txqm_id, 0);

            /* #2, read HW table: McMacPcsCfg */
            tbl_id = McMacPcsCfg_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_pcs_cfg));

            /* ##2.1. calc step */
            step = McMacPcsCfg_mcMacPcsCfg_1_cfgAlternateEncode_f - McMacPcsCfg_mcMacPcsCfg_0_cfgAlternateEncode_f;
            factor = inner_mac_id;/* 0..39 per txqm */

            /* ##2.2. modify field value */
            /* ###2.2.1. */
            fld_id = McMacPcsCfg_mcMacPcsCfg_0_cfgAlternateEncode_f + step*factor;
            val32 = 1;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &mac_pcs_cfg, txqm_id, 0);

            /* #3, write HW table: McMacPcsCfg*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_pcs_cfg));
            /*************** (VI) McMacPcsCfg end! ****************/

            /*McMacMiiRxCfg.cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault set 0*/
            CTC_ERROR_RETURN(_sys_tmm_mac_set_tx_force_fault_by_mac_id(lchip, mac_id, 0));          
        }
        else     /* disable */
        {
            /*McMacMiiRxCfg.cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault set 1*/
            CTC_ERROR_RETURN(_sys_tmm_mac_set_tx_force_fault_by_mac_id(lchip, mac_id, CTC_PORT_FAULT_FORCE));

            /*************** (VI) McMacPcsCfg start! ****************/
            /* #1, calc index */
            index = DRV_INS(txqm_id, 0);

            /* #2, read HW table: McMacPcsCfg */
            tbl_id = McMacPcsCfg_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_pcs_cfg));

            /* ##2.1. calc step */
            step = McMacPcsCfg_mcMacPcsCfg_1_cfgAlternateEncode_f - McMacPcsCfg_mcMacPcsCfg_0_cfgAlternateEncode_f;
            factor = inner_mac_id;/* 0..39 per txqm */

            /* ##2.2. modify field value */
            /* ###2.2.1. */
            fld_id = McMacPcsCfg_mcMacPcsCfg_0_cfgAlternateEncode_f + step*factor;
            val32 = 0;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &val32, &mac_pcs_cfg, txqm_id, 0);

            /* #3, write HW table: McMacPcsCfg*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_pcs_cfg));
            /*************** (VI) McMacPcsCfg end! ****************/
            
            /*************** (I) McMacReserved start! ****************/
            /* #1, calc index */
            index = DRV_INS(txqm_id, 0);

            /* #2, read HW table */
            tbl_id = McMacReserved_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rsv));
            
            
            if (inner_mac_id < 32)
            {
                fld_id = McMacReserved_mcMacReserved_0_reserved_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &mac_rsv);
                array32[0] |= (1 << inner_mac_id);
            }
            else
            {
                fld_id = McMacReserved_mcMacReserved_1_reserved_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &mac_rsv);
                array32[0] |= (1 << (inner_mac_id % 8));
            }
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &mac_rsv, txqm_id, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rsv));
            /*************** (I) McMacReserved end! ****************/

            CTC_ERROR_RETURN(_sys_tmm_mac_wait_rx_buf_empty(lchip, mac_id));

            /*************** (IV) McMacRxSoftReset start! ****************/
            /* #1, calc index */
            index = DRV_INS(txqm_id, 0);

            /* #2, read HW table */
            tbl_id = McMacRxSoftReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));

            fld_id = McMacRxSoftReset_cfgMcMacRxSoftReset_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, array32, &mac_rx_reset);
            if (inner_mac_id >= 32)
            {
                array32[1] |= (1 << (inner_mac_id % 8));
            }
            else
            {
                array32[0] |= (1 << inner_mac_id);
            }
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, array32, &mac_rx_reset, txqm_id, 0);

            /* #3, write HW table*/
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_rx_reset));
            /*************** (IV) McMacRxSoftReset end! ****************/
        }
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_mcmac_flexe_common_en(uint8 lchip, uint16 lport, uint8 dir, uint8 enable)
{
    sys_datapath_lport_attr_t* port_attr = NULL;
    
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d\n", __FUNCTION__, __LINE__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    CTC_ERROR_RETURN(_sys_tmm_flexe_check_mac_en_condition(lchip, port_attr->mac_id, dir, enable));
    CTC_ERROR_RETURN(_sys_tmm_mac_set_flexe_mac_en(lchip, port_attr->mac_id, dir, enable));

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_mac_set_mcmac_common_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 is_pcs_x16 = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %d\n", __FUNCTION__, __LINE__, lport);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);

    is_pcs_x16 = SYS_TMM_IS_PCS_X16(port_attr->txqm_id);
    if (is_pcs_x16)
    {
        if ((CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
            && (port_attr->pcs_idx % 16 >= 8))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Not support QSGMII mode!\n");
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mcmac_x16_common_en(lchip, lport, enable));
    }
    else
    {
        if (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Not support QSGMII mode!\n");
            return CTC_E_NOT_SUPPORT;
        }
        else 
        {
            if (CTC_PORT_IF_FLEXE == port_attr->interface_type)
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "FlexE client mapping mac %d, only enable McMac, exclude McPcs!\n", port_attr->mac_id);
                if (enable)
                {
                    CTC_ERROR_RETURN(_sys_tmm_mac_set_mcmac_flexe_common_en(lchip, lport, SYS_FLEXE_DIR_TX, TRUE));
                    CTC_ERROR_RETURN(_sys_tmm_mac_set_mcmac_flexe_common_en(lchip, lport, SYS_FLEXE_DIR_RX, TRUE));
                }
                else
                {
                    CTC_ERROR_RETURN(_sys_tmm_mac_set_mcmac_flexe_common_en(lchip, lport, SYS_FLEXE_DIR_RX, FALSE));
                    CTC_ERROR_RETURN(_sys_tmm_mac_set_mcmac_flexe_common_en(lchip, lport, SYS_FLEXE_DIR_TX, FALSE));
                }
            }
            else
            {
                CTC_ERROR_RETURN(_sys_tmm_mac_set_mcmac_x8_common_en(lchip, lport, enable));
            }
        }
    }

    return CTC_E_NONE;
}

/*for qsgmii, if all lport in ths quad group (except current lport) are mac disable, 
then return TRUE to allow serdes tx off, else return FALSE.
Other modes always return TRUE.*/
uint8
_sys_tmm_mac_judge_serdes_tx_off(uint8 lchip, sys_datapath_lport_attr_t* port_attr)
{
    uint16 mac_id;
    uint16 mac_id_base = port_attr->mac_id / 4 * 4;
    uint16 lport;
    uint8  mac_id_delta = 0;

    if((CTC_CHIP_SERDES_QSGMII_MODE != port_attr->pcs_mode) || !SYS_TMM_IS_MAC_SUPPORT_QSGMII(port_attr->mac_id))
    {
        return TRUE;
    }

    for(mac_id_delta = 0; mac_id_delta < 4; mac_id_delta++)
    {
        mac_id = mac_id_base + mac_id_delta;
        SYS_CONDITION_CONTINUE(mac_id == port_attr->mac_id);

        lport = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);
        SYS_CONDITION_RETURN(p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en, FALSE);
    }
    return TRUE;
}

int32
_sys_tmm_mac_set_mac_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint8 serdes_idx = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
 
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num, CTC_E_INVALID_PARAM);

    if (0 == SDK_WORK_PLATFORM)
    {       
        if(!enable && _sys_tmm_mac_judge_serdes_tx_off(lchip, port_attr) && (CTC_PORT_IF_FLEXE != port_attr->interface_type))
        {
            for(serdes_idx = 0; serdes_idx < port_attr->serdes_num; serdes_idx ++)
            {
                CTC_ERROR_RETURN(sys_tmm_serdes_set_tx_en(lchip, port_attr->multi_serdes_id[serdes_idx], FALSE));
            }
            if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
                sal_udelay(32000);
            }
        }
        
        /* PCS/MII/Sgmac/FEC reset or release */
        if (SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
        {
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_mac_en(lchip, lport, enable));
        }
        else if ((port_attr->port_type == SYS_DMPS_NETWORK_PORT) || (port_attr->port_type == SYS_DMPS_INACTIVE_NETWORK_PORT))
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_mcmac_common_en(lchip, lport, enable));
        }

        if(enable && (CTC_PORT_IF_FLEXE != port_attr->interface_type))
        {
            for(serdes_idx = 0; serdes_idx < port_attr->serdes_num; serdes_idx ++)
            {
                CTC_ERROR_RETURN(sys_tmm_serdes_set_tx_en(lchip, port_attr->multi_serdes_id[serdes_idx], TRUE));
            }
        }

    }

    p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en = ((enable)?TRUE:FALSE);


    //CTC_ERROR_RETURN(sys_usw_qos_set_fc_default_profile(lchip, gport));

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_set_fec_clear(uint8 lchip, uint16 lport, ctc_chip_serdes_mode_t mode, uint32 type)
{
    uint8 i = 0;
    uint8 list_size = 0;
    uint8 mii_idx = 0;
    uint8 pcs_idx = 0;
    uint32 cmd = 0;
    uint32 index = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    uint32 (*p_cfg_mapping)[3] = NULL;

    uint32 xfi_xxvg_cfg_mapping[][3] = {
    /*tbl_id                          field_id                                 value*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     0},  /*0*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,                  0},  /*1*/

    {SharedPcsFecCfg_t,     SharedPcsFecCfg_cgfecEn_f,                            0},  /*2*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn0_f,                        0},  /*3*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecRsMode0_f,                    0},  /*4*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xlgPcsFecEn_f,                        0},  /*5*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                       0},  /*6*/
        
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec100GPort_f,            0},  /*7*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0_f,            0},  /*8*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f,      0},  /*9*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f,      0},  /*10*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x3fff},  /*11*/
        
    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                1}};  /*12*/

    uint32 lg_cfg_mapping[][3] = {
    /*tbl_id                          field_id                                 value*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     0},  /*0*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,             0x3fff},  /*1*/
        
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_cgfecEn_f,                            0},  /*2*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn0_f,                        0},  /*3*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecRsMode0_f,                    0},  /*4*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xlgPcsFecEn_f,                        0},  /*5*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                       0},  /*6*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn1_f,                       0},  /*7*/
        
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec100GPort_f,            0},  /*8*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0_f,            0},  /*9*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f,      0},  /*10*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f,      0},  /*11*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort1RsMode_f,      0},  /*12*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x3fff},  /*13*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,  0x3fff},  /*14*/
        
    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1},  /*15*/
    {XgFec1CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1},  /*16*/
    {XgFec2CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1},  /*17*/
    {XgFec3CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1}};  /*18*/

    uint32 xlg_cg_cfg_mapping[][3] = {
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                      0},  /*0*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,              0x3fff},  /*1*/
    {SharedMii1Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                      0},  /*2*/
    {SharedMii1Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,              0x3fff},  /*3*/
    {SharedMii2Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                      0},  /*4*/
    {SharedMii2Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,              0x3fff},  /*5*/
    {SharedMii3Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                      0},  /*6*/
    {SharedMii3Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,              0x3fff},  /*7*/

    {SharedPcsFecCfg_t,     SharedPcsFecCfg_cgfecEn_f,                             0},  /*8*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn0_f,                         0},  /*9*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecRsMode0_f,                     0},  /*10*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn1_f,                         0},  /*11*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecRsMode1_f,                     0},  /*12*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xlgPcsFecEn_f,                         0},  /*13*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                        0},  /*14*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn1_f,                        0},  /*15*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn2_f,                        0},  /*16*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn3_f,                        0},  /*17*/

    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec100GPort_f,             0},  /*18*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0_f,             0},  /*19*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f,       0},  /*20*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort1_f,             0},  /*21*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort1RsMode_f,       0},  /*22*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f,       0},  /*23*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort1RsMode_f,       0},  /*24*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort2RsMode_f,       0},  /*25*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort3RsMode_f,       0},  /*26*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec40GPort_f,              0},  /*27*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,   0x3fff},  /*28*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,   0x3fff},  /*29*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f,   0x3fff},  /*30*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval3_f,   0x3fff},  /*31*/
        
    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1},  /*32*/
    {XgFec2CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1},  /*33*/
    {XgFec3CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1},  /*34*/
    {XgFec6CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 1}};  /*35*/

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d, mode:%d, fec type : %d\n", lport, mode, type);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    mii_idx = port_attr->mii_idx;
    pcs_idx = port_attr->pcs_idx;

    if((CTC_CHIP_SERDES_XFI_MODE == mode) || (CTC_CHIP_SERDES_XXVG_MODE == mode))
    {
        p_cfg_mapping = xfi_xxvg_cfg_mapping;
        list_size = sizeof(xfi_xxvg_cfg_mapping) / sizeof(uint32) / 3;
      
        p_cfg_mapping[0][0] += mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
        p_cfg_mapping[1][0] += mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
        p_cfg_mapping[3][1] += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecEn1_f - SharedPcsFecCfg_lgPcsFecEn0_f);
        p_cfg_mapping[4][1] += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecRsMode1_f - SharedPcsFecCfg_lgPcsFecRsMode0_f);
        p_cfg_mapping[6][1] += (pcs_idx % 4) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[8][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1_f - GlobalCtlSharedFec_cfgSharedFec50GPort0_f);
        p_cfg_mapping[9][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1RsMode_f - GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f);
        p_cfg_mapping[10][1] += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFec25GPort1RsMode_f - GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f);
        p_cfg_mapping[11][1] += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[12][0] += (pcs_idx % 4 )* (XgFec2CtlSharedFec_t - XgFec0CtlSharedFec_t);       
       
    }    
    else if(CTC_CHIP_SERDES_LG_MODE == mode)
    {
        p_cfg_mapping = lg_cfg_mapping;
        list_size = sizeof(lg_cfg_mapping) / sizeof(uint32) / 3;
     
        p_cfg_mapping[0][0] += mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
        p_cfg_mapping[1][0] += mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
        p_cfg_mapping[3][1] += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecEn1_f - SharedPcsFecCfg_lgPcsFecEn0_f);
        p_cfg_mapping[4][1] += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecRsMode1_f - SharedPcsFecCfg_lgPcsFecRsMode0_f);
        p_cfg_mapping[6][1] += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[7][1] += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[9][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1_f - GlobalCtlSharedFec_cfgSharedFec50GPort0_f);
        p_cfg_mapping[10][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1RsMode_f - GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f);
        p_cfg_mapping[11][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec25GPort2RsMode_f - GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f);
        p_cfg_mapping[12][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec25GPort2RsMode_f - GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f);
        p_cfg_mapping[13][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[14][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[15][0] += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[16][0] += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[17][0] += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[18][0] += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);    
    }
    else if((CTC_CHIP_SERDES_XLG_MODE == mode) || (CTC_CHIP_SERDES_CG_MODE == mode))
    {
        p_cfg_mapping = xlg_cg_cfg_mapping;
        list_size = sizeof(xlg_cg_cfg_mapping) / sizeof(uint32) / 3;
    }

    for(i = 0; i < list_size; i++)
    {
        cmd = DRV_IOW(*(p_cfg_mapping[i] + 0), p_cfg_mapping[i][1]);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &p_cfg_mapping[i][2]));
    }

    return CTC_E_NONE;
}


int32
_sys_tmm_cpumac_set_fec_baser(uint8 lchip, uint16 lport, ctc_chip_serdes_mode_t mode, uint32 type)
{
    uint8 i = 0;
    uint8 list_size = 0;
    uint8 pcs_idx = 0;
    uint32 cmd = 0;
    uint32 index = 0;
    uint32 (*p_cfg_mapping)[3] = NULL;
    sys_datapath_lport_attr_t* port_attr = NULL;

    uint32 xfi_cfg_mapping[][3] = {
    /*tbl_id                field_id                                          value*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff},  /*0*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                       1},   /*1*/
    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                0}};  /*2*/

    uint32 xlg_cfg_mapping[][3] = {
    /*tbl_id                field_id                                           value*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff},  /*0*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,  0x13fff},  /*1*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f,  0x13fff},  /*2*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval3_f,  0x13fff},  /*3*/                     
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xlgPcsFecEn_f,                         1},  /*4*/ 
    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0},  /*5*/ 
    {XgFec2CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0},  /*6*/ 
    {XgFec4CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0},  /*7*/ 
    {XgFec6CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0},  /*8*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec40GPort_f,              1}}; /*9*/  

    uint32 xxvg_cfg_mapping[][3] = {
    /*tbl_id                field_id                                            value*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff},  /*0*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                       1},   /*1*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f,      0}};  /*2*/

    uint32 lg_cfg_mapping[][3] = {
    /*tbl_id                field_id                                            value*/   
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff},  /*0*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,  0x13fff},  /*1*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn0_f,                        1},   /*2*/                
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0_f,            1},   /*3*/
    {XgFec0CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0},  /*4*/ 
    {XgFec1CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0},  /*5*/ 
    {XgFec2CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0},  /*6*/ 
    {XgFec3CtlSharedFec_t,  XgFec0CtlSharedFec_cfgXgFec0TxWidth_f,                 0}};  /*7*/  

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d, mode:%d, fec type : %d\n", lport, mode, type);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    pcs_idx = port_attr->pcs_idx;

    if(CTC_CHIP_SERDES_XFI_MODE == mode)
    {
        p_cfg_mapping = xfi_cfg_mapping;
        list_size = sizeof(xfi_cfg_mapping) / sizeof(uint32) / 3;

        p_cfg_mapping[0][1] += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[1][1] += (pcs_idx % 4) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[2][0] += (pcs_idx % 4) * (XgFec2CtlSharedFec_t - XgFec0CtlSharedFec_t);
    }
    else if(CTC_CHIP_SERDES_XXVG_MODE == mode)
    {
        p_cfg_mapping = xxvg_cfg_mapping;
        list_size = sizeof(xxvg_cfg_mapping) / sizeof(uint32) / 3;

        p_cfg_mapping[0][1] += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[1][1] += (pcs_idx % 4) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[2][1] += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFec25GPort1RsMode_f - GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f);
    }
    else if(CTC_CHIP_SERDES_XLG_MODE == mode)
    {
        p_cfg_mapping = xlg_cfg_mapping;
        list_size = sizeof(xlg_cfg_mapping) / sizeof(uint32) / 3;
    }
    else if(CTC_CHIP_SERDES_LG_MODE == mode)
    {
        p_cfg_mapping = lg_cfg_mapping;
        list_size = sizeof(lg_cfg_mapping) / sizeof(uint32) / 3;

        p_cfg_mapping[0][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[1][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[2][1] += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecEn1_f - SharedPcsFecCfg_lgPcsFecEn0_f);
        p_cfg_mapping[3][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1_f - GlobalCtlSharedFec_cfgSharedFec50GPort0_f);

        p_cfg_mapping[4][0] += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[5][0] += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[6][0] += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
        p_cfg_mapping[7][0] += (pcs_idx % 4 / 2) * (XgFec4CtlSharedFec_t - XgFec0CtlSharedFec_t);
    }
    
    for(i = 0; i < list_size; i++)
    {
        cmd = DRV_IOW(p_cfg_mapping[i][0], p_cfg_mapping[i][1]);
        DRV_IOW_PRINT(lchip, p_cfg_mapping[i][0], p_cfg_mapping[i][1], p_cfg_mapping[i][2]);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &p_cfg_mapping[i][2]));
    }

    return CTC_E_NONE;

}

int32
_sys_tmm_cpumac_set_fec_rs(uint8 lchip, uint16 lport, ctc_chip_serdes_mode_t mode, uint32 type)
{   
    uint8 i = 0;
    uint8 list_size = 0;
    uint32 cmd = 0;
    uint32 index = 0;
    uint8 pcs_idx = 0;
    uint8 mii_idx = 0;
    uint32 (*p_cfg_mapping)[3] = NULL;
    sys_datapath_lport_attr_t* port_attr = NULL;

    uint32 xxlg_cfg_mapping[][3] = {
    /*tbl_id                field_id                                          value*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     1},  /*0*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,             0x4fff},  /*1*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_xfiPcsFecEn0_f,                       1},  /*2*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f,      1},  /*3*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff}}; /*4*/

    uint32 lg_cfg_mapping[][3] = {
    /*tbl_id                field_id                                           value*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     1},  /*0*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxAmInterval0_f,             0x4fff},  /*1*/

    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecEn0_f,                        1},  /*2*/
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_lgPcsFecRsMode0_f,                    1},  /*3*/     
    
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x9fff},  /*4*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,  0x9fff},  /*5*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0_f,            1},  /*6*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f,      1}};  /*7*/

    uint32 cg_cfg_mapping[][3] = {
    /*tbl_id                field_id                                              value*/
    {SharedMii0Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     1},  /*0*/
    {SharedMii1Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     1},  /*1*/
    {SharedMii2Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     1},  /*2*/
    {SharedMii3Cfg_t,       SharedMii0Cfg_cfgMiiTxRsFecEn0_f,                     1},  /*3*/
        
    {SharedPcsFecCfg_t,     SharedPcsFecCfg_cgfecEn_f,                            1},  /*4*/

    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f,  0x13fff},  /*5*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f,  0x13fff},  /*6*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f,  0x13fff},  /*7*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFecRxAmInterval3_f,  0x13fff},  /*8*/
    {GlobalCtlSharedFec_t,  GlobalCtlSharedFec_cfgSharedFec100GPort_f,            1}};  /*9*/

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d, mode:%d, fec type : %d\n", lport, mode, type);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    mii_idx = port_attr->mii_idx;
    pcs_idx = port_attr->pcs_idx;

    if(CTC_CHIP_SERDES_XXVG_MODE == mode)
    {
        p_cfg_mapping = xxlg_cfg_mapping;
        list_size = sizeof(xxlg_cfg_mapping) / sizeof(xxlg_cfg_mapping[0]);

        p_cfg_mapping[0][0] +=mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
        p_cfg_mapping[1][0] += mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
        p_cfg_mapping[2][1] += (pcs_idx % 4) * (SharedPcsFecCfg_xfiPcsFecEn1_f - SharedPcsFecCfg_xfiPcsFecEn0_f);
        p_cfg_mapping[3][1] += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFec25GPort1RsMode_f - GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f);
        p_cfg_mapping[4][1] += (pcs_idx % 4) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval1_f - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
    }
    else if(CTC_CHIP_SERDES_LG_MODE == mode)
    {
        p_cfg_mapping = lg_cfg_mapping;
        list_size = sizeof(lg_cfg_mapping) / sizeof(lg_cfg_mapping[0]);

        p_cfg_mapping[0][0] +=mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
        p_cfg_mapping[1][0] += mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
        p_cfg_mapping[2][1] += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecEn1_f - SharedPcsFecCfg_lgPcsFecEn0_f);
        p_cfg_mapping[3][1] += (pcs_idx % 4 / 2) * (SharedPcsFecCfg_lgPcsFecRsMode1_f - SharedPcsFecCfg_lgPcsFecRsMode0_f);
        p_cfg_mapping[4][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[5][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFecRxAmInterval2_f - GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f);
        p_cfg_mapping[6][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1_f - GlobalCtlSharedFec_cfgSharedFec50GPort0_f);
        p_cfg_mapping[7][1] += (pcs_idx % 4 / 2) * (GlobalCtlSharedFec_cfgSharedFec50GPort1RsMode_f - GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f);
    }
    else if(CTC_CHIP_SERDES_CG_MODE == mode)
    {
        p_cfg_mapping = cg_cfg_mapping;
        list_size = sizeof(cg_cfg_mapping) / sizeof(cg_cfg_mapping[0]);
    }

    for(i = 0; i < list_size; i++)
    {
        cmd = DRV_IOW(p_cfg_mapping[i][0], p_cfg_mapping[i][1]);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &p_cfg_mapping[i][2]));
    }

    return CTC_E_NONE;

}

int32
_sys_tmm_mac_get_fec_type_capability(uint8 pcs_mode, uint32* p_value)
{
    CTC_PTR_VALID_CHECK(p_value);

    switch(pcs_mode)
    {
        case CTC_CHIP_SERDES_CDG_R8_MODE:
        case CTC_CHIP_SERDES_CCG_R4_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS544);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS272);
            break;
        case CTC_CHIP_SERDES_CG_R2_MODE:
        case CTC_CHIP_SERDES_LG_R1_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS544);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS272);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS528);
            break;
        case CTC_CHIP_SERDES_XXVG_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS528);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_FC2112);
            break;
            
        case CTC_CHIP_SERDES_LG_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS528);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS544);
            break;
        case CTC_CHIP_SERDES_CG_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_RS528);
            *p_value |= (1 << CTC_PORT_FEC_TYPE_RS544);
            break;
        case CTC_CHIP_SERDES_XFI_MODE:
        case CTC_CHIP_SERDES_XLG_MODE:
            *p_value = (1 << CTC_PORT_FEC_TYPE_FC2112);
            break;
        default:
            *p_value = (1 << CTC_PORT_FEC_TYPE_NONE);
            break;
    }
    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_set_fec_config(uint8 lchip, uint16 lport, ctc_chip_serdes_mode_t mode, uint32 type)
{   
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d, mode:%d, fec type : %d\n", lport, mode, type);
    
    /*param check moved outside before mac dis*/

    /*FEC Configure*/
    if(CTC_PORT_FEC_TYPE_NONE == type)
    {
        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_fec_clear(lchip, lport, mode, type));
        /*update sw table*/
        p_usw_mac_master[lchip]->mac_prop[lport].port_fec_val = type;
        return CTC_E_NONE;
    }

    switch(type)
    {
        case CTC_PORT_FEC_TYPE_RS:
        case CTC_PORT_FEC_TYPE_RS528:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_fec_clear(lchip, lport, mode, type));
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_fec_rs(lchip, lport, mode, type));
            break;
        case CTC_PORT_FEC_TYPE_BASER:
        case CTC_PORT_FEC_TYPE_FC2112:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_fec_clear(lchip, lport, mode, type));
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_fec_baser(lchip, lport, mode, type));
            break;
        default:
            return CTC_E_INVALID_PARAM;
    }

    /*update sw table*/
    p_usw_mac_master[lchip]->mac_prop[lport].port_fec_val = type;

    return CTC_E_NONE;
}

uint8
_sys_tmm_mac_check_fec_speed_compatible(uint32 fec_type, uint8 ovclk_flag)
{
    uint8 valid_flag[CTC_CHIP_MAX_SERDES_OCS_MODE] = {
        FALSE, //CTC_CHIP_SERDES_OCS_MODE_NONE
        FALSE, //CTC_CHIP_SERDES_OCS_MODE_11_06G
        FALSE, //CTC_CHIP_SERDES_OCS_MODE_12_12G
        FALSE, //CTC_CHIP_SERDES_OCS_MODE_12_58G
        TRUE,  //CTC_CHIP_SERDES_OCS_MODE_27_27G
        FALSE, //CTC_CHIP_SERDES_OCS_MODE_10_6G
        TRUE,  //CTC_CHIP_SERDES_OCS_MODE_26_56G
        TRUE,  //CTC_CHIP_SERDES_OCS_MODE_26_52G
        TRUE,  //CTC_CHIP_SERDES_OCS_MODE_26_9G
        TRUE,  //CTC_CHIP_SERDES_OCS_MODE_36_36G
        TRUE,  //CTC_CHIP_SERDES_OCS_MODE_36_76G
        FALSE, //CTC_CHIP_SERDES_OCS_MODE_11_06G11
        FALSE, //CTC_CHIP_SERDES_OCS_MODE_12_58G12
        TRUE,  //CTC_CHIP_SERDES_OCS_MODE_51_56G
        TRUE,  //CTC_CHIP_SERDES_OCS_MODE_52_71G
    };

    SYS_CONDITION_RETURN((CTC_CHIP_MAX_SERDES_OCS_MODE <= ovclk_flag), FALSE);

    if((CTC_PORT_FEC_TYPE_RS544 != fec_type) && (CTC_PORT_FEC_TYPE_RS272 != fec_type))
    {
        /*line rate 53.125G (OCS_MODE_51_56G) is only for RS544 & 272, other FEC cannot work in such rate*/
        /*line rate 26.5625G (OCS_MODE_26_56G) is only for NRZ 100G RS544, other FEC cannot work in such rate*/
        SYS_CONDITION_RETURN((CTC_CHIP_SERDES_OCS_MODE_51_56G == ovclk_flag) || (CTC_CHIP_SERDES_OCS_MODE_26_56G == ovclk_flag), FALSE);
        return TRUE;
    }

    return valid_flag[ovclk_flag];
}

int32
_sys_tmm_mac_set_fec_serdes_speed(uint8 lchip, sys_datapath_lport_attr_t* port_attr, uint32 type)
{
    uint8 physic_serdes_id = 0;
    uint8 logic_serdes_id = 0;
    uint8 serdes_num = port_attr->serdes_num;
    uint8 serdes_idx;
    uint8 base_mode = port_attr->pcs_mode;
    uint8 ovclk_flag; //ctc_chip_serdes_ocs_mode_t
    uint8 src_ovclk_flag;

    SYS_CONDITION_RETURN(((CTC_CHIP_SERDES_LG_MODE != base_mode) && (CTC_CHIP_SERDES_LG_R1_MODE != base_mode) && 
                          (CTC_CHIP_SERDES_CG_MODE != base_mode) && (CTC_CHIP_SERDES_CG_R2_MODE != base_mode) && 
                          (CTC_CHIP_SERDES_CCG_R4_MODE != base_mode) && (CTC_CHIP_SERDES_CDG_R8_MODE != base_mode)), CTC_E_NONE);
    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < serdes_num, CTC_E_INVALID_PARAM);

    physic_serdes_id = port_attr->multi_serdes_id[0];
    CTC_ERROR_RETURN(sys_tmm_serdes_get_glb_info(lchip, physic_serdes_id, SYS_TMM_SERDES_GLB_OVCLK_SPEED, &src_ovclk_flag));

    /*if old ovclk is acceptable for new fec type, do nothing*/
    SYS_CONDITION_RETURN(TRUE == _sys_tmm_mac_check_fec_speed_compatible(type, src_ovclk_flag), CTC_E_NONE);

    switch(type)
    {
        case CTC_PORT_FEC_TYPE_RS544:
            if(SYS_TMM_MODE_IS_PAM4(base_mode))
            {
                ovclk_flag = CTC_CHIP_SERDES_OCS_MODE_51_56G;
            }
            else
            {
                ovclk_flag = CTC_CHIP_SERDES_OCS_MODE_26_56G;
            }
            break;
        case CTC_PORT_FEC_TYPE_RS272:
            if(SYS_TMM_MODE_IS_PAM4(base_mode))
            {
                ovclk_flag = CTC_CHIP_SERDES_OCS_MODE_51_56G;
            }
            else
            {
                ovclk_flag = CTC_CHIP_SERDES_OCS_MODE_26_56G;
            }
            break;
        case CTC_PORT_FEC_TYPE_RS528:
        case CTC_PORT_FEC_TYPE_FC2112:
        case CTC_PORT_FEC_TYPE_NONE:
        default:
            /*for RS528 FEC in 100GR2/50GR1, symbol rate should change from 53.125G to 51.5625G, but 56.25G is unchangeable*/
            if((CTC_CHIP_SERDES_OCS_MODE_51_56G == src_ovclk_flag) || (CTC_CHIP_SERDES_OCS_MODE_26_56G == src_ovclk_flag))
            {
                ovclk_flag = CTC_CHIP_SERDES_OCS_MODE_NONE;
            }
            else
            {
                ovclk_flag = src_ovclk_flag;
            }
            break;
    }
    SYS_CONDITION_RETURN(ovclk_flag == src_ovclk_flag, CTC_E_NONE);

    for(serdes_idx = 0; serdes_idx < serdes_num; serdes_idx++)
    {
        physic_serdes_id = port_attr->multi_serdes_id[serdes_idx];
        _sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, physic_serdes_id, &logic_serdes_id);
        SYS_CONDITION_RETURN((SYS_TMM_USELESS_ID8 == logic_serdes_id), CTC_E_INVALID_PARAM);
        CTC_ERROR_RETURN(sys_tmm_serdes_set_glb_info(lchip, physic_serdes_id, SYS_TMM_SERDES_GLB_OVCLK_SPEED, ovclk_flag));
#ifndef EMULATION_ENV
        CTC_ERROR_RETURN(_sys_tmm_dynamic_switch_serdes_cfg(lchip, physic_serdes_id, logic_serdes_id, base_mode, base_mode, ovclk_flag));
#endif
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_fec_en(uint8 lchip, uint16 lport, ctc_chip_serdes_mode_t mode, uint32 type)
{
    uint8 fec_old = p_usw_mac_master[lchip]->mac_prop[lport].port_fec_val;
    uint8 fec_new = CTC_PORT_FEC_TYPE_NONE;
    uint8 mac_toggle_flag = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_FEC_TYPE_NORMALIZE(type, fec_new);
    SYS_CONDITION_RETURN((fec_old == fec_new), CTC_E_NONE);

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    /*CPUMAC param check*/
    if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        if((CTC_PORT_FEC_TYPE_RS544 == fec_new) || (CTC_PORT_FEC_TYPE_RS272 == fec_new))
        {
            return CTC_E_INVALID_CONFIG;
        }
        if(((CTC_PORT_FEC_TYPE_BASER == fec_new) || (CTC_PORT_FEC_TYPE_FC2112 == fec_new))
            && ((CTC_CHIP_SERDES_XXVG_MODE != mode) && (CTC_CHIP_SERDES_LG_MODE != mode)
            && (CTC_CHIP_SERDES_XFI_MODE != mode) && (CTC_CHIP_SERDES_XLG_MODE  != mode)))
        {
            return CTC_E_INVALID_CONFIG;
        }
        
        if(((CTC_PORT_FEC_TYPE_RS == fec_new) || (CTC_PORT_FEC_TYPE_RS528 == fec_new))  
            && ((CTC_CHIP_SERDES_XXVG_MODE != mode) && (CTC_CHIP_SERDES_LG_MODE  != mode)
            && (CTC_CHIP_SERDES_CG_MODE  != mode)))
        {
            return CTC_E_INVALID_CONFIG;
        }
    }
    /*network param check*/
    else
    {
        if((CTC_PORT_FEC_TYPE_NONE != fec_new) && (MAX_MODE_FEC == g_mode_with_fec_map[mode][FEC_TYPE_NORMALIZE(fec_new)]))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Unsupported FEC type %u, mode %u\n", fec_new, mode);
            return CTC_E_INVALID_CONFIG;
        }
        if((CTC_PORT_FEC_TYPE_NONE == fec_new) && 
           ((CTC_CHIP_SERDES_CCG_R4_MODE == mode) || (CTC_CHIP_SERDES_CDG_R8_MODE == mode)))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Unsupported FEC NONE, mode %u\n", mode);
            return CTC_E_INVALID_CONFIG;
        }
    }

    /* toggle mac/pcs reset while mac/pcs is already release reset */
    if (p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en)
    {
        mac_toggle_flag = 1;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_en(lchip, lport, FALSE));
    }

    if ((SYS_DMPS_NETWORK_PORT == port_attr->port_type) || (SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type))
    {
        /*change serdes line speed*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_fec_serdes_speed(lchip, port_attr, (uint32)fec_new));
        /*low corepll fec map clear before config*/
        CTC_ERROR_RETURN(_sys_tmm_mac_low_corepll_fec_free(lchip, port_attr));
        /*set fec config*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_config(lchip, lport, mode, fec_new, port_attr->port_type, FALSE));
        /*low corepll fec map remap after config*/
        CTC_ERROR_RETURN(_sys_tmm_mac_low_corepll_fec_remap(lchip, lport, port_attr));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_fec_config(lchip, lport, mode, (uint32)fec_new));
    }

    /* toggle mac/pcs reset while mac/pcs is already release reset */
    if (mac_toggle_flag)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
    }

    return CTC_E_NONE;
}

/*
Get FEC status by global port id
*/
int32
_sys_tmm_mac_get_fec_en(uint8 lchip, uint16 lport, uint32* p_value)
{
    sys_datapath_lport_attr_t* port_attr = NULL;
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        *p_value = CTC_PORT_FEC_TYPE_NONE;
    }
    else
    {
        *p_value = p_usw_mac_master[lchip]->mac_prop[lport].port_fec_val;
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_fec_en(uint8 lchip, uint16 lport, uint32* p_value)
{

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_fec_en(lchip, lport, p_value));
    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_auto_neg(uint8 lchip, uint16 lport, uint32 type, uint32 value)
{
    uint32 cmd        = 0;
    uint32 tbl_id     = 0;
    uint32 field_id   = 0;
    uint16 step       = 0;
    uint32 mode_value = 0;
    uint8  pcs_idx    = 0;
    uint32 factor = 0;
    uint32 index = 0;
    uint32 curr_val = 0;
    uint32 is_pcs_x16 = 0;  
    uint32 pcs_x8_x16_index = 0;
    McPcsX16LanesSgmiiCfg_m sgmii_modecfg16;
    McPcsX8LanesSgmiiCfg_m sgmii_modecfg8;
    McPcsX16LanesQsgmiiCfg_m qsgmii_modecfg16;
    SharedPcsCfg0_m       pcs_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_INIT_CHECK();
    sal_memset(&sgmii_modecfg16, 0, sizeof(McPcsX16LanesSgmiiCfg_m));
    sal_memset(&sgmii_modecfg8, 0, sizeof(McPcsX8LanesSgmiiCfg_m));
    sal_memset(&qsgmii_modecfg16, 0, sizeof(McPcsX16LanesQsgmiiCfg_m));
    sal_memset(&pcs_cfg, 0, sizeof(SharedPcsCfg0_m));

    if (CTC_PORT_PROP_AUTO_NEG_EN == type)
    {
        CTC_ERROR_RETURN(sys_tmm_mac_get_auto_neg(lchip, lport, type, &curr_val));
        if ((curr_val && value) || ((!curr_val)&&(!value)))
        {
            /* No change */
            return CTC_E_NONE;
        }
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }

    /* SGMII/QSGMII mode auto neg */
    if(SYS_MAC_IS_MODE_SUPPORT_CL37(port_attr->pcs_mode))        
    {
        /* Cfg auto neg enable/disable */
        if(CTC_PORT_PROP_AUTO_NEG_EN == type)
        {
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_cl37_auto_neg_en(lchip, lport, value));
        }
        /* Cfg auto MODE */
        else if(CTC_PORT_PROP_AUTO_NEG_MODE == type)
        {
            if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
            {
                index = 0;
                pcs_idx = port_attr->pcs_idx;

                /* CPUMAC inherit from tsingma  1000Base-X(2'b00), SGMII-Slaver(2'b10) */
                if(CTC_PORT_AUTO_NEG_MODE_1000BASE_X == value)
                {
                    mode_value = 0;
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_speed(lchip, lport, CTC_PORT_SPEED_1G));
                }
                else if(CTC_PORT_AUTO_NEG_MODE_SGMII_SLAVER == value)
                {
                    mode_value = 2;
                }

                if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || 
                   (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
                {
                    step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
                    tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
                    field_id = SharedPcsSgmii0Cfg_anegMode0_f;
                    cmd = DRV_IOW(tbl_id, field_id);
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(DRV_FIELD_IOCTL(lchip, index, cmd, &mode_value));
                }
            }
            else
            {
                SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
                index = DRV_INS(pcs_x8_x16_index, 0);
                pcs_idx = port_attr->pcs_idx;

                if(CTC_PORT_AUTO_NEG_MODE_1000BASE_X == value)
                {
                    mode_value = 0;
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_speed(lchip, lport, CTC_PORT_SPEED_1G));
                }
                else if(CTC_PORT_AUTO_NEG_MODE_SGMII_SLAVER == value)
                {
                    mode_value = 2;
                }
                else if(CTC_PORT_AUTO_NEG_MODE_SGMII_MASTER == value)
                {
                    mode_value = 1;
                }

                if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || 
                    (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
                {
                    /*HS PORT*/
                    if (1==is_pcs_x16)
                    {
                        
                        tbl_id=McPcsX16LanesSgmiiCfg_t;
                        step=McPcsX16LanesSgmiiCfg_cfgSgmii_1_anegMode_f-McPcsX16LanesSgmiiCfg_cfgSgmii_0_anegMode_f;
                        factor= pcs_idx;                   
                        field_id=McPcsX16LanesSgmiiCfg_cfgSgmii_0_anegMode_f+step*factor;
                        cmd = DRV_IOW(tbl_id, field_id);
                        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(DRV_FIELD_IOCTL(lchip, index, cmd, &mode_value));
                    }
                    /*CS PORT*/
                    else if(0==is_pcs_x16)                
                    {                
                        /*mode */
                        tbl_id=McPcsX8LanesSgmiiCfg_t;
                        step=McPcsX8LanesSgmiiCfg_cfgSgmii_1_anegMode_f-McPcsX8LanesSgmiiCfg_cfgSgmii_0_anegMode_f;
                        factor= pcs_idx;                  
                        field_id=McPcsX8LanesSgmiiCfg_cfgSgmii_0_anegMode_f+step*factor;         
                        cmd = DRV_IOW(tbl_id, field_id);
                        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(DRV_FIELD_IOCTL(lchip, index, cmd, &mode_value));
                    }
                }
                else if(CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
                {           
                    /*mode */
                    tbl_id=McPcsX16LanesQsgmiiCfg_t;
                    step=McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_anegMode_f-McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anegMode_f;
                    factor = port_attr->mac_id-(SYS_TMM_MAX_MAC_NUM_PER_TXQM*port_attr->txqm_id);          
                    field_id=McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anegMode_f+step*factor;         
                    cmd = DRV_IOW(tbl_id, field_id);
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(DRV_FIELD_IOCTL(lchip, index, cmd, &mode_value));
                }
            }
        }
        else if (CTC_PORT_PROP_AUTO_NEG_FEC == type)
        {
            MAC_UNLOCK;
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% FEC not supported\n");
            return CTC_E_INVALID_PARAM;
        }
    
    }
    /* 802.3 cl73 auto neg */
    else if(SYS_MAC_IS_MODE_SUPPORT_CL73(port_attr->pcs_mode))
    {
        /* Cfg auto neg enable/disable */
        if (CTC_PORT_PROP_AUTO_NEG_EN == type)
        {
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_cl73_auto_neg_en(lchip, lport, value, FALSE));
        }
        else if (CTC_PORT_PROP_AUTO_NEG_FEC == type)
        {
            port_attr->an_fec = 0;
            if (CTC_PORT_FEC_TYPE_NONE != value)
            {
                if (value & (1 << CTC_PORT_FEC_TYPE_RS))
                {
                    port_attr->an_fec |= (1 << CTC_PORT_FEC_TYPE_RS);
                }
                if (value & (1 << CTC_PORT_FEC_TYPE_BASER))
                {
                    port_attr->an_fec |= (1 << CTC_PORT_FEC_TYPE_BASER);
                }
            }
        }
        else if(CTC_PORT_PROP_AUTO_NEG_MODE == type)
        {
            if(CTC_PORT_AUTO_NEG_MODE_OVER_CLOCK == value)
            {
                port_attr->an_speed_mode = SYS_MAC_AN_SPEED_312D5M;
            }
            else
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% AN mode cannot be changed in CL73, keep in 312.5M\n");
                MAC_UNLOCK;
                return CTC_E_INVALID_PARAM;
            }
        }
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR," %% port 0x%x mode %d do not support Auto-Nego \n", lport, port_attr->pcs_mode);
        MAC_UNLOCK;
        return CTC_E_INVALID_CONFIG;
    }

    MAC_UNLOCK;

    return CTC_E_NONE;
}



#define  __TMM_GET_LINK_STATUS__


STATIC int32
_sys_tmm_mac_get_mii_link_status(uint8 lchip, uint8 type, uint16 lport, uint32* p_value, uint32 unidir_en)
{
    //uint32 is_pcs_x16 = 0;
    //uint32 pcs_x8_x16_index = 0;
    uint32 index  = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd    = 0;
    uint32 step   = 0;
    uint32 factor = 0;
    uint32 val32  = 0;
    /*uint8  dp_id  = 0;*/
    //McPcsX8LanesRxChanMon_m  pcsx8_status;
    //McPcsX16LanesRxChanMon_m  pcsx16_status;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);

    //sal_memset(&pcsx8_status, 0, sizeof(McPcsX8LanesRxChanMon_m));
    //sal_memset(&pcsx16_status, 0, sizeof(McPcsX16LanesRxChanMon_m));

#if 0   /* PCS status */
    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);

    index = DRV_INS(pcs_x8_x16_index, 0);
    factor = port_attr->pcs_idx % (is_pcs_x16?16:8);   /* 0..16(X16) or 0..8(X8) per txqm */
    if (is_pcs_x16)
    {
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            tbl_id = McPcsX16LanesRxChanMon_t;
            step   = McPcsX16LanesSgmiiMon_monSgmii_1_anLinkStatus_f - McPcsX16LanesSgmiiMon_monSgmii_0_anLinkStatus_f;
            fld_id = McPcsX16LanesSgmiiMon_monSgmii_0_anLinkStatus_f + step * factor;
        }
        else if (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
        {
            tbl_id = McPcsX16LanesQsgmiiMon_t;
            step   = McPcsX16LanesQsgmiiMon_monQsgmiiSgmii_1_anLinkStatus_f - McPcsX16LanesQsgmiiMon_monQsgmiiSgmii_0_anLinkStatus_f;
            fld_id = McPcsX16LanesQsgmiiMon_monQsgmiiSgmii_0_anLinkStatus_f + step * factor;
        }
        else
        {
            tbl_id = McPcsX16LanesRxChanMon_t;
            step   = McPcsX16LanesRxChanMon_monRxStatusChan_1_monRxSyncStatus_f - McPcsX16LanesRxChanMon_monRxStatusChan_0_monRxSyncStatus_f;
            fld_id = McPcsX16LanesRxChanMon_monRxStatusChan_0_monRxSyncStatus_f + step * factor;
        }
    }
    else
    {
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            tbl_id = McPcsX8LanesRxChanMon_t;
            step   = McPcsX8LanesSgmiiMon_monSgmii_1_anLinkStatus_f - McPcsX8LanesSgmiiMon_monSgmii_0_anLinkStatus_f;
            fld_id = McPcsX8LanesSgmiiMon_monSgmii_0_anLinkStatus_f + step * factor;
        }
        else
        {
            tbl_id = McPcsX8LanesRxChanMon_t;
            step   = McPcsX8LanesRxChanMon_monRxStatusChan_1_monRxSyncStatus_f - McPcsX8LanesRxChanMon_monRxStatusChan_0_monRxSyncStatus_f;
            fld_id = McPcsX8LanesRxChanMon_monRxStatusChan_0_monRxSyncStatus_f + step * factor;
        }
    }
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &val32));
#else   /* Mii status */
    /* #1, calc index */
    index = port_attr->txqm_id;

    /* #2, read HW table: McMacMiiTxCfg */
    tbl_id = McMacMiiRxDebugStats_t;

    /* ##2.1. calc step */
    step = McMacMiiRxDebugStats_dbgMcMacMiiRx_1_dbgMiiRxLinkStatus_f - McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxLinkStatus_f;
    factor = TXQM_INNER_MAC_ID(port_attr->mac_id);/* 0..39 per txqm */ 

    /* ##2.2. get field value */
    fld_id = McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxLinkStatus_f + step*factor;

    /* #3, read HW table */
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &val32));
    
#endif

    SYS_USW_VALID_PTR_WRITE(p_value, val32);

    return CTC_E_NONE;
}


STATIC int32
_sys_tmm_mac_get_mii_link_status_raw(uint8 lchip, uint16 lport, uint32* p_value)
{
    uint32 index  = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd    = 0;
    uint32 step   = 0;
    uint32 factor = 0;
    uint32 val32  = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "mac_id:%d\n", port_attr->mac_id);

   /* Mii status */
    /* #1, calc index */
    index = port_attr->txqm_id;

    /* #2, read HW table: McMacMiiTxCfg */
    tbl_id = McMacMiiRxDebugStats_t;

    /* ##2.1. calc step */
    step = McMacMiiRxDebugStats_dbgMcMacMiiRx_1_dbgMiiRxLinkStatusRaw_f - McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxLinkStatusRaw_f;
    factor = TXQM_INNER_MAC_ID(port_attr->mac_id);/* 0..39 per txqm */ 

    /* ##2.2. get field value */
    fld_id = McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxLinkStatusRaw_f + step*factor;

    /* #3, read HW table */
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &val32));

    SYS_USW_VALID_PTR_WRITE(p_value, val32);

    return CTC_E_NONE;
}

#define __TMM_DYNAMIC_SWITCH__

int32
_sys_tmm_ds_add_lport_to_target(uint8 lchip, uint16 lport, uint16 chan_id, sys_tmm_ds_target_attr_t *target, 
                                          uint8 upt_flag, uint8 force_flag, uint8 serdes_list_idx, uint8 relate_flag)
{
    uint8 i;
    uint8 is_exist = FALSE;
    uint8 is_relate_exist = FALSE;
    uint8 idx;

    /*0. find lport in list*/
    for(i = 0; i < target->lport_num; i++)
    {
        if(target->lport_list[i].lport == lport)
        {
            is_exist = TRUE;
            break;
        }
    }

    /*1. save relate_flag*/
    /*if serdes_list_idx is exist and updating relate_flag is NEW, change relate_flag*/
    /*else, add this serdes_list_idx to array serdes_relate*/
    for(idx = 0; idx < target->lport_list[i].serdes_relate_num; idx++)
    {
        if(serdes_list_idx == target->lport_list[i].serdes_relate[idx].serdes_list_idx)
        {
            is_relate_exist = TRUE;
            break;
        }
    }
    if(is_relate_exist)
    {
        if(SYS_DS_LPORT_SERDES_NEW == relate_flag)
        {
            target->lport_list[i].serdes_relate[idx].relate_flag = relate_flag;
        }
    }
    else
    {
        target->lport_list[i].serdes_relate[idx].serdes_list_idx = serdes_list_idx;
        target->lport_list[i].serdes_relate[idx].relate_flag     = relate_flag;
        (target->lport_list[i].serdes_relate_num)++;
    }

    /*2. save lport list*/
    /*if exist and not force update, exit*/
    /*else, add this lport to list*/
    if(is_exist && (SYS_DS_LPORT_NO_FORCE_UPT == force_flag))
    {
        return CTC_E_NONE;
    }

    target->lport_list[i].lport    = lport;
    target->lport_list[i].upt_flag = upt_flag;
    target->lport_list[i].chan_id  = chan_id;
    if(!is_exist)
    {
        (target->lport_num)++;
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_ds_add_influenced_serdes(uint8 lchip,
                                         sys_datapath_lport_attr_t* src_port_attr,
                                         uint8 dst_mode,
                                         sys_tmm_ds_target_attr_t *target)
{
    _tmm_port_serdes_ratio_t src_ratio;
    _tmm_port_serdes_ratio_t dst_ratio;
    uint8 i = 0;
    uint8 serdes_offset = 0;
    uint8 serdes_new_base = 0;
    uint8 src_mode = src_port_attr->pcs_mode;
    uint8 influenced_serdes_num[PORT_SERDES_RATIO_BUTT][PORT_SERDES_RATIO_BUTT] = {
    /*src mode: 0-0 1-1 1-2 1-4 1-8 4-1*/
               {0,  1,  2,  4,  8,  1}, //dst mode: 0-0
               {1,  1,  2,  4,  8,  1}, //dst mode: 1-1
               {2,  2,  2,  4,  8,  2}, //dst mode: 1-2
               {4,  4,  4,  4,  8,  4}, //dst mode: 1-4
               {8,  8,  8,  8,  8,  8}, //dst mode: 1-8
               {1,  1,  2,  4,  0,  0}, //dst mode: 4-1
    };
    uint8  hss_id = 0;
    uint8  inner_lane_id = 0;
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    SYS_TMM_GET_PORT_SERDES_RATIO_BY_MODE(src_mode, src_ratio);
    SYS_TMM_GET_PORT_SERDES_RATIO_BY_MODE(dst_mode, dst_ratio);
    
    /*1. influenced serdes*/
    target->serdes_num = influenced_serdes_num[dst_ratio][src_ratio];
    /*1.1 old serdes*/
    for (i = 0; i < src_port_attr->serdes_num; i++)
    {
        _sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, 
            src_port_attr->multi_serdes_id[i], &(target->serdes_list[i].logic_serdes_id));
        SYS_CONDITION_CONTINUE(SYS_TMM_USELESS_ID8 == target->serdes_list[i].logic_serdes_id);
        target->serdes_list[i].dst_mode = dst_mode;
        /*get src mode from serdes info*/
        hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(target->serdes_list[i].logic_serdes_id);
        p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
        SYS_CONDITION_CONTINUE(p_hss_vec == NULL);
        inner_lane_id = SYS_TMM_MAP_SERDES_TO_LANE_ID(target->serdes_list[i].logic_serdes_id);
        target->serdes_list[i].src_mode = p_hss_vec->serdes_info[inner_lane_id].mode;
        target->serdes_list[i].dst_lport_idx = SYS_TMM_USELESS_ID8;
    }
    /*1.2 new serdes*/
    serdes_new_base = target->serdes_list[i-1].logic_serdes_id;
    if(target->serdes_num > src_port_attr->serdes_num)
    {
        for(serdes_offset = 1; serdes_offset <= (target->serdes_num - src_port_attr->serdes_num); serdes_offset++)
        {
            target->serdes_list[i].logic_serdes_id = serdes_new_base + serdes_offset;
            target->serdes_list[i].dst_mode        = dst_mode;
            hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(target->serdes_list[i].logic_serdes_id);
            p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
            SYS_CONDITION_CONTINUE(p_hss_vec == NULL);
            inner_lane_id = SYS_TMM_MAP_SERDES_TO_LANE_ID(target->serdes_list[i].logic_serdes_id);
            target->serdes_list[i].src_mode = p_hss_vec->serdes_info[inner_lane_id].mode;
            target->serdes_list[i].dst_lport_idx = SYS_TMM_USELESS_ID8;
            i++;
        }
    }
    
    return CTC_E_NONE;
}

int32
_sys_tmm_ds_add_influenced_lport_by_serdes(uint8 lchip, uint8 serdes_list_idx, sys_tmm_ds_target_attr_t *target)
{
    uint8  pcs_l_id_old     = 0;
    uint8  pcs_l_id_new     = 0;
    uint8  lane_num_old     = 0;
    uint8  lane_num_new     = 0;
    uint8  logic_serdes_id  = target->serdes_list[serdes_list_idx].logic_serdes_id;
    uint8  hss_id           = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logic_serdes_id);
    uint8  inner_lane_id    = SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_id);
    uint8  lane_id_tmp      = 0;
    uint16 lport_old        = 0;
    uint16 lport_new        = 0;
    uint16 chan_id_old      = 0;
    uint16 chan_id_new      = 0;
    uint8  new_port_num     = 1;
    uint8  upt_flag_old     = SYS_DS_LPORT_REMAIN; //drop or remain
    uint8  upt_flag_new     = SYS_DS_LPORT_REMAIN; //remain or add

    sys_datapath_hss_attribute_t* p_hss_vec = NULL;
    sys_datapath_serdes_info_t*   p_serdes  = NULL;

    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    if (p_hss_vec == NULL)
    {
        return CTC_E_INVALID_PTR;
    }
    p_serdes = &(p_hss_vec->serdes_info[inner_lane_id]);

    SYS_TMM_GET_LANE_NUM_BY_MODE(target->serdes_list[serdes_list_idx].src_mode, lane_num_old);
    SYS_TMM_GET_LANE_NUM_BY_MODE(target->serdes_list[serdes_list_idx].dst_mode, lane_num_new);

    if(CTC_CHIP_SERDES_QSGMII_MODE == target->serdes_list[serdes_list_idx].dst_mode)
    {
        new_port_num = 4;
    }

    pcs_l_id_old  = p_serdes->pcs_l_id; 
    lport_old     = p_serdes->lport;
    inner_lane_id = p_serdes->lane_id;
    chan_id_old   = p_serdes->chan_id;
    
    /*2. lport info collect*/
    if(lane_num_new > lane_num_old)
    {
        pcs_l_id_new = serdes_list_idx;
        lane_id_tmp  = SYS_TMM_MAP_SERDES_TO_LANE_ID(target->serdes_list[0].logic_serdes_id);
        lport_new    = p_hss_vec->serdes_info[lane_id_tmp].lport;
        chan_id_new  = p_hss_vec->serdes_info[lane_id_tmp].chan_id;

        upt_flag_old = (0 == pcs_l_id_new) ? SYS_DS_LPORT_REMAIN : SYS_DS_LPORT_DROP;
        upt_flag_new = SYS_DS_LPORT_REMAIN;
    }
    else if(lane_num_new < lane_num_old)
    {
        pcs_l_id_new = pcs_l_id_old % lane_num_new;
        if((0 == pcs_l_id_new) && (0 == pcs_l_id_old))
        {
            lport_new    = lport_old;
            chan_id_new  = chan_id_old;
            
            upt_flag_old = SYS_DS_LPORT_REMAIN;
            upt_flag_new = SYS_DS_LPORT_REMAIN;
        }
        else if((0 != pcs_l_id_new) && (0 != pcs_l_id_old))
        {
            lport_new    = target->lport_list[target->lport_num - pcs_l_id_new].lport;
            chan_id_new  = target->lport_list[target->lport_num - pcs_l_id_new].chan_id;
            
            upt_flag_old = SYS_DS_LPORT_REMAIN;
            upt_flag_new = SYS_DS_LPORT_REMAIN;
        }
        else
        {
            CTC_ERROR_RETURN(_sys_tmm_datapath_alloc_lport(lchip, logic_serdes_id, &chan_id_new, &lport_new, new_port_num));
            
            upt_flag_old = SYS_DS_LPORT_REMAIN;
            upt_flag_new = SYS_DS_LPORT_ADD;
        }
    }
    else
    {
        /*pcs_l_id_new = pcs_l_id_old;*/
        lport_new    = lport_old;
        chan_id_new  = chan_id_old;
        upt_flag_old = SYS_DS_LPORT_REMAIN;
        upt_flag_new = SYS_DS_LPORT_REMAIN;
    }
    /*ds_print_target(255, target);*/

    /*3. add lport to target*/
    if(SYS_DS_LPORT_DROP == upt_flag_old)
    {
        _sys_tmm_ds_add_lport_to_target(lchip, lport_new, chan_id_new, target, upt_flag_new, 
            SYS_DS_LPORT_NO_FORCE_UPT, serdes_list_idx, SYS_DS_LPORT_SERDES_NEW);
        _sys_tmm_ds_add_lport_to_target(lchip, lport_old, chan_id_old, target, upt_flag_old, 
            SYS_DS_LPORT_NO_FORCE_UPT, serdes_list_idx, SYS_DS_LPORT_SERDES_OLD);
    }
    else
    {
        _sys_tmm_ds_add_lport_to_target(lchip, lport_new, chan_id_new, target, upt_flag_new, 
            SYS_DS_LPORT_NO_FORCE_UPT, serdes_list_idx, SYS_DS_LPORT_SERDES_NEW);
    }

    if(CTC_CHIP_SERDES_QSGMII_MODE == target->serdes_list[serdes_list_idx].src_mode)
    {
        _sys_tmm_ds_add_lport_to_target(lchip, lport_old+1, chan_id_old+1, target, SYS_DS_LPORT_DROP, 
            SYS_DS_LPORT_NO_FORCE_UPT, serdes_list_idx, SYS_DS_LPORT_SERDES_OLD);
        _sys_tmm_ds_add_lport_to_target(lchip, lport_old+2, chan_id_old+2, target, SYS_DS_LPORT_DROP, 
            SYS_DS_LPORT_NO_FORCE_UPT, serdes_list_idx, SYS_DS_LPORT_SERDES_OLD);
        _sys_tmm_ds_add_lport_to_target(lchip, lport_old+3, chan_id_old+3, target, SYS_DS_LPORT_DROP, 
            SYS_DS_LPORT_NO_FORCE_UPT, serdes_list_idx, SYS_DS_LPORT_SERDES_OLD);
    }

    if(CTC_CHIP_SERDES_QSGMII_MODE == target->serdes_list[serdes_list_idx].dst_mode)
    {
        _sys_tmm_ds_add_lport_to_target(lchip, lport_new+1, chan_id_new+1, target, SYS_DS_LPORT_ADD, 
            SYS_DS_LPORT_NO_FORCE_UPT, serdes_list_idx, SYS_DS_LPORT_SERDES_NEW);
        _sys_tmm_ds_add_lport_to_target(lchip, lport_new+2, chan_id_new+2, target, SYS_DS_LPORT_ADD, 
            SYS_DS_LPORT_NO_FORCE_UPT, serdes_list_idx, SYS_DS_LPORT_SERDES_NEW);
        _sys_tmm_ds_add_lport_to_target(lchip, lport_new+3, chan_id_new+3, target, SYS_DS_LPORT_ADD, 
            SYS_DS_LPORT_NO_FORCE_UPT, serdes_list_idx, SYS_DS_LPORT_SERDES_NEW);
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_txqm_bandwidth(uint8 lchip, uint8 txqm_id, uint32* p_bandwidth)
{
    uint16 mac_id_start = txqm_id * SYS_TMM_MAX_MAC_NUM_PER_TXQM;
    uint16 mac_id_end   = mac_id_start + SYS_TMM_MAX_MAC_NUM_PER_TXQM;
    uint16 mac_id;
    uint16 lport;
    uint32 speed_mode;
    uint32 speed;
    uint32 bandwidth = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    for(mac_id = mac_id_start; mac_id < mac_id_end; mac_id++)
    {
        lport = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);
        port_attr = sys_usw_datapath_get_port_capability(lchip, lport);
        SYS_CONDITION_CONTINUE((NULL == port_attr) || (port_attr->port_type != SYS_DMPS_NETWORK_PORT));
        SYS_TMM_GET_PORT_SPEED(port_attr->pcs_mode, speed_mode);
        SYS_DATAPATH_MODE_TO_SPEED(speed_mode, speed);
        bandwidth += speed;
    }

    SYS_USW_VALID_PTR_WRITE(p_bandwidth, bandwidth);
    
    return CTC_E_NONE;
}

int32
sys_tmm_mac_ds_add_serdes_lport_to_target(uint8 lchip, uint8* src_quad_comb, uint8* dst_quad_comb, 
                                                        uint8 logic_serdes_id, uint8 dst_mode, sys_tmm_ds_target_attr_t *target, 
                                                        uint16 overclocking_speed)
{
    uint8 serdes_idx = 0;
    uint8 lane_id_tmp;
    uint8 quad_lane_idx;
    uint8 quad_port_idx;
    uint8 comb_idx;
    uint8 chan_tmp;
    uint16 lport_tmp;
    int32 ret;
    uint8 find_flag;
    uint8 lane_num;
    uint8 logic_serdes_tmp = 0;
    uint8 lport_idx = 0;
    uint8 quad = SYS_TMM_LANE_NUM_PER_HSS/2;
    uint8 src_lport_comb[16];
    uint8 dst_lport_comb[16];
    uint8 src_chan_comb[16];
    uint8 dst_chan_comb[16];
    uint8 src_qsgmii[4];
    uint8 dst_qsgmii[4];
    uint8 hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logic_serdes_id);
    uint8 lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_id);
    uint8 quad_lane_base = lane_id/4*4;
    uint8 i;
    sys_tmm_ds_lport_serdes_relate_t* p_serdes_relate = NULL;
    
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    sal_memset(src_lport_comb, 0xff,  16 * sizeof(uint8));
    sal_memset(dst_lport_comb, 0xff,  16 * sizeof(uint8));
    sal_memset(src_chan_comb,  0xff,  16 * sizeof(uint8));
    sal_memset(dst_chan_comb,  0xff,  16 * sizeof(uint8));
    sal_memset(src_qsgmii,     FALSE, 4 * sizeof(uint8));
    sal_memset(dst_qsgmii,     FALSE, 4 * sizeof(uint8));

    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    SYS_CONDITION_RETURN(p_hss_vec == NULL, CTC_E_NONE);
    
    /*add serdes*/
    for(quad_lane_idx = 0; quad_lane_idx < quad; quad_lane_idx++)
    {
        /*if no change between src and dst lport, skip add to target*/
        if(dst_quad_comb[quad_lane_idx] == src_quad_comb[quad_lane_idx])
        {
            SYS_TMM_GET_LANE_NUM_BY_MODE(dst_mode, lane_num);
            SYS_CONDITION_CONTINUE((quad_lane_idx < lane_id % quad) || (quad_lane_idx > lane_id % quad + lane_num - 1));
        }

        lane_id_tmp = quad_lane_base+quad_lane_idx;
        target->serdes_list[serdes_idx].logic_serdes_id = SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id_tmp);
        target->serdes_list[serdes_idx].src_mode        = p_hss_vec->serdes_info[lane_id_tmp].mode;
        /*add dst_mode to list. for 50GR2->50GR1, lane 1 & 3 should be dropped*/
        if((SYS_DATAPATH_HSS_TYPE_15G == p_hss_vec->hss_type) && 
           (CTC_CHIP_SERDES_LG_MODE == p_hss_vec->serdes_info[lane_id_tmp].mode) && 
           (CTC_CHIP_SERDES_LG_R1_MODE == dst_mode) && (1 == quad_lane_idx % 2))
        {
            target->serdes_list[serdes_idx].dst_mode    = CTC_CHIP_SERDES_NONE_MODE;
        }
        else
        {
            target->serdes_list[serdes_idx].dst_mode    = dst_mode;
        }

        if(CTC_CHIP_SERDES_QSGMII_MODE == target->serdes_list[serdes_idx].src_mode)
        {
            src_qsgmii[quad_lane_idx] = TRUE;
        }
        if(CTC_CHIP_SERDES_QSGMII_MODE == target->serdes_list[serdes_idx].dst_mode)
        {
            dst_qsgmii[quad_lane_idx] = TRUE;
        }
        
        (target->serdes_num)++;
        serdes_idx++;
    }

    /*add port*/
    /*get old port combination*/
    for(quad_lane_idx = 0; quad_lane_idx < quad; quad_lane_idx++)
    {
        lane_id_tmp = quad_lane_base+quad_lane_idx;
        SYS_CONDITION_CONTINUE(0 != p_hss_vec->serdes_info[lane_id_tmp].pcs_l_id);
        
        for(quad_port_idx = 0; quad_port_idx < quad; quad_port_idx++)
        {
            comb_idx = quad_lane_idx*quad+quad_port_idx;
            SYS_CONDITION_CONTINUE((CTC_CHIP_SERDES_QSGMII_MODE != p_hss_vec->serdes_info[lane_id_tmp].mode) && 
                                   (0 != quad_port_idx));
            src_lport_comb[comb_idx] = p_hss_vec->serdes_info[lane_id_tmp].lport + quad_port_idx;
            src_chan_comb[comb_idx]  = p_hss_vec->serdes_info[lane_id_tmp].chan_id + quad_port_idx;
        }
    }

    /*get new port combination*/
    for(quad_lane_idx = 0; quad_lane_idx < quad; quad_lane_idx++)
    {
        if((dst_quad_comb[quad_lane_idx] == src_quad_comb[quad_lane_idx]) && 
           (dst_qsgmii[quad_lane_idx] == src_qsgmii[quad_lane_idx]))
        {
            sal_memcpy(&(dst_lport_comb[quad_lane_idx*quad]), &(src_lport_comb[quad_lane_idx*quad]), quad*sizeof(uint8));
            sal_memcpy(&(dst_chan_comb[quad_lane_idx*quad]),  &(src_chan_comb[quad_lane_idx*quad]),  quad*sizeof(uint8));
            continue;
        }

        /*mode none is not added to dst*/
        SYS_CONDITION_CONTINUE(0 == dst_quad_comb[quad_lane_idx]);
        lane_num = dst_quad_comb[quad_lane_idx];
        logic_serdes_tmp = logic_serdes_id/quad*quad+quad_lane_idx;
        
        SYS_CONDITION_CONTINUE(0 != logic_serdes_tmp % lane_num);

        ret = sys_tmm_get_lport_chan_map(lchip, logic_serdes_tmp, &chan_tmp, &lport_tmp);
        SYS_CONDITION_CONTINUE(CTC_E_NONE != ret);
        
        for(quad_port_idx = 0; quad_port_idx < quad; quad_port_idx++)
        {
            comb_idx = quad_lane_idx*quad+quad_port_idx;
            SYS_CONDITION_CONTINUE((!dst_qsgmii[quad_lane_idx]) && (0 != quad_port_idx));
            dst_lport_comb[comb_idx] = lport_tmp + quad_port_idx;
            dst_chan_comb[comb_idx]  = chan_tmp + quad_port_idx;
        }
    }

    /*compare*/
    for(quad_lane_idx = 0; quad_lane_idx < quad; quad_lane_idx++)
    {
        lane_id_tmp = quad_lane_base+quad_lane_idx;
        
        for(quad_port_idx = 0; quad_port_idx < quad; quad_port_idx++)
        {
            comb_idx = quad_lane_idx*quad+quad_port_idx;
            /*if no change between src and dst lport, skip add to target*/            
            if(dst_quad_comb[quad_lane_idx] == src_quad_comb[quad_lane_idx])
            {
                SYS_TMM_GET_LANE_NUM_BY_MODE(dst_mode, lane_num);
                SYS_CONDITION_CONTINUE((quad_lane_idx < lane_id % quad) || (quad_lane_idx > lane_id % quad + lane_num - 1));
            }

            SYS_CONDITION_CONTINUE((0xff == src_lport_comb[comb_idx]) && (0xff == dst_lport_comb[comb_idx]));
            
            /*if src and dst lport are euqal, remain this port*/
            if(src_lport_comb[comb_idx] == dst_lport_comb[comb_idx])
            {
                target->lport_list[lport_idx].lport    = dst_lport_comb[comb_idx];
                target->lport_list[lport_idx].chan_id  = dst_chan_comb[comb_idx];
                target->lport_list[lport_idx].upt_flag = SYS_DS_LPORT_REMAIN;
                /*add port-serdes relation*/
                SYS_TMM_GET_LANE_NUM_BY_MODE(dst_mode, lane_num);
                for(serdes_idx = 0; serdes_idx < target->serdes_num; serdes_idx++)
                {
                    /*add serdes relation to port list*/
                    i = target->lport_list[lport_idx].serdes_relate_num;
                    p_serdes_relate = &(target->lport_list[lport_idx].serdes_relate[i]);

                    p_serdes_relate->serdes_list_idx = serdes_idx;
                    p_serdes_relate->relate_flag = (serdes_idx < lane_num) ? SYS_DS_LPORT_SERDES_NEW : SYS_DS_LPORT_SERDES_OLD;
                    (target->lport_list[lport_idx].serdes_relate_num)++;
                    /*add related lport idx to serdes list*/
                    SYS_CONDITION_CONTINUE(SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id_tmp) != 
                                           target->serdes_list[serdes_idx].logic_serdes_id);
                    target->serdes_list[serdes_idx].dst_lport_idx = lport_idx;
                }
                lport_idx++;
                (target->lport_num)++;
            }
            /*if src lport exist & dst lport vanished, drop this port*/
            else if((0xff != src_lport_comb[comb_idx]) && (0xff == dst_lport_comb[comb_idx]))
            {
                target->lport_list[lport_idx].lport    = src_lport_comb[comb_idx];
                target->lport_list[lport_idx].chan_id  = src_chan_comb[comb_idx];
                target->lport_list[lport_idx].upt_flag = SYS_DS_LPORT_DROP;
                
                find_flag = FALSE;

                for(serdes_idx = 0; serdes_idx < target->serdes_num; serdes_idx++)
                {
                    /*find this serdes start & end point before add*/
                    if(SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id_tmp) == target->serdes_list[serdes_idx].logic_serdes_id)
                    {
                        find_flag = TRUE;
                    }
                    else if(target->lport_list[lport_idx].serdes_relate_num >= src_quad_comb[quad_lane_idx])
                    {
                        find_flag = FALSE;
                    }
                    SYS_CONDITION_CONTINUE(!find_flag);
                    
                    /*add serdes relation to port list*/
                    i = target->lport_list[lport_idx].serdes_relate_num;
                    p_serdes_relate = &(target->lport_list[lport_idx].serdes_relate[i]);

                    p_serdes_relate->serdes_list_idx = serdes_idx;
                    p_serdes_relate->relate_flag = SYS_DS_LPORT_SERDES_OLD;
                    (target->lport_list[lport_idx].serdes_relate_num)++;
                }
                lport_idx++;
                (target->lport_num)++;
            }
            /*if src lport vanished & dst lport exist, add this port*/
            else if((0xff == src_lport_comb[comb_idx]) && (0xff != dst_lport_comb[comb_idx]))
            {
                target->lport_list[lport_idx].lport    = dst_lport_comb[comb_idx];
                target->lport_list[lport_idx].chan_id  = dst_chan_comb[comb_idx];
                target->lport_list[lport_idx].upt_flag = SYS_DS_LPORT_ADD;

                find_flag = FALSE;

                for(serdes_idx = 0; serdes_idx < target->serdes_num; serdes_idx++)
                {
                    /*find this serdes start & end point before add*/
                    if(SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id_tmp) == target->serdes_list[serdes_idx].logic_serdes_id)
                    {
                        find_flag = TRUE;
                    }
                    else if(target->lport_list[lport_idx].serdes_relate_num >= dst_quad_comb[quad_lane_idx])
                    {
                        find_flag = FALSE;
                    }
                    SYS_CONDITION_CONTINUE(!find_flag);
                    
                    /*add serdes relation to port list*/
                    i = target->lport_list[lport_idx].serdes_relate_num;
                    p_serdes_relate = &(target->lport_list[lport_idx].serdes_relate[i]);

                    p_serdes_relate->serdes_list_idx = serdes_idx;
                    p_serdes_relate->relate_flag = SYS_DS_LPORT_SERDES_NEW;
                    (target->lport_list[lport_idx].serdes_relate_num)++;
                    /*add related lport idx to serdes list*/
                    /*skip condition: current lport is a new QSGMII, but not 1st lport in this quad*/
                    SYS_CONDITION_CONTINUE((0 != quad_port_idx) && (TRUE == dst_qsgmii[quad_lane_idx]));
                    target->serdes_list[serdes_idx].dst_lport_idx = lport_idx;
                }
                lport_idx++;
                (target->lport_num)++;
            }
            /*illegal: src & dst lport all exist but not equal*/
            else
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% src and dst lport combination error!\n");
            }
        }
    }

    /*add ovclk*/
    for(serdes_idx = 0; serdes_idx < target->serdes_num; serdes_idx++)
    {
        target->serdes_list[serdes_idx].ovclk_flag = 
            ((CTC_CHIP_SERDES_OCS_MODE_NONE == overclocking_speed) && 
            SYS_TMM_MODE_IS_PAM4(target->serdes_list[serdes_idx].dst_mode)) ? 
            CTC_CHIP_SERDES_OCS_MODE_51_56G : overclocking_speed;
    }

    return CTC_E_NONE;
}

/*for 400G <-> other, only CS support 400G*/
int32
sys_tmm_mac_ds_add_serdes_lport_to_target_cdg(uint8 lchip, uint8 logic_serdes_id, uint8 dst_mode, 
                                                             sys_tmm_ds_target_attr_t *target, uint16 overclocking_speed)
{
    uint8 serdes_idx = 0;
    uint8 lane_id_tmp;
    uint8 comb_idx;
    uint8 dp_chan_id;
    uint8 find_flag;
    uint8 lane_num;
    uint8 logic_serdes_tmp = 0;
    uint8 lport_idx = 0;
    uint8 src_lport_comb[8];
    uint8 dst_lport_comb[8];
    uint8 src_serdes_num[8];
    uint8 dst_serdes_num[8];
    uint8 src_chan_comb[8];
    uint8 dst_chan_comb[8];
    uint8 dp_id     = SYS_TMM_GET_DP_ID_FROM_SERDES(logic_serdes_id);
    uint8 hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logic_serdes_id);
    /*uint8 lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_id);*/
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    sal_memset(src_lport_comb, 0xff, SYS_TMM_LANE_NUM_PER_HSS * sizeof(uint8));
    sal_memset(dst_lport_comb, 0xff, SYS_TMM_LANE_NUM_PER_HSS * sizeof(uint8));
    sal_memset(src_chan_comb,  0xff, SYS_TMM_LANE_NUM_PER_HSS * sizeof(uint8));
    sal_memset(dst_chan_comb,  0xff, SYS_TMM_LANE_NUM_PER_HSS * sizeof(uint8));
    sal_memset(src_serdes_num, 0xff, SYS_TMM_LANE_NUM_PER_HSS * sizeof(uint8));
    sal_memset(dst_serdes_num, 0xff, SYS_TMM_LANE_NUM_PER_HSS * sizeof(uint8));

    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    SYS_CONDITION_RETURN(p_hss_vec == NULL, CTC_E_NONE);
    
    /*add serdes*/
    for(lane_id_tmp = 0; lane_id_tmp < SYS_TMM_LANE_NUM_PER_HSS; lane_id_tmp++)
    {
        target->serdes_list[serdes_idx].logic_serdes_id = SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id_tmp);
        target->serdes_list[serdes_idx].src_mode        = p_hss_vec->serdes_info[lane_id_tmp].mode;
        target->serdes_list[serdes_idx].dst_mode        = dst_mode;

        SYS_TMM_GET_LANE_NUM_BY_MODE(target->serdes_list[serdes_idx].src_mode, src_serdes_num[lane_id_tmp]);
        SYS_TMM_GET_LANE_NUM_BY_MODE(target->serdes_list[serdes_idx].dst_mode, dst_serdes_num[lane_id_tmp]);
        
        (target->serdes_num)++;
        serdes_idx++;
    }

    /*add port*/
    /*get old port combination*/
    for(comb_idx = 0; comb_idx < SYS_TMM_LANE_NUM_PER_HSS; comb_idx++)
    {
        SYS_CONDITION_CONTINUE(0 != p_hss_vec->serdes_info[comb_idx].pcs_l_id);
        SYS_CONDITION_CONTINUE(SYS_TMM_IS_MODE_NONE(p_hss_vec->serdes_info[comb_idx].mode));
        src_lport_comb[comb_idx] = p_hss_vec->serdes_info[comb_idx].lport;
        src_chan_comb[comb_idx]  = p_hss_vec->serdes_info[comb_idx].chan_id;
    }
    
    /*get new port combination*/
    SYS_TMM_GET_LANE_NUM_BY_MODE(dst_mode, lane_num);
    for(comb_idx = 0; comb_idx < SYS_TMM_LANE_NUM_PER_HSS; comb_idx++)
    {
        SYS_CONDITION_CONTINUE(SYS_TMM_IS_MODE_NONE(dst_mode));
        logic_serdes_tmp = SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, comb_idx);
        
        SYS_CONDITION_CONTINUE(0 != comb_idx % lane_num);

        find_flag = FALSE;
        for(dp_chan_id = 0; dp_chan_id < SYS_TMM_CHANNEL_NUM_PER_DP; dp_chan_id++)
        {
            if(p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan_id].logic_serdes_id == logic_serdes_tmp)
            {
                find_flag = TRUE;
                break;
            }
        }
        SYS_CONDITION_CONTINUE(!find_flag);
        
        dst_lport_comb[comb_idx] = p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan_id].lport;
        dst_chan_comb[comb_idx]  = SYS_GET_CHANNEL_BY_DP_CHANID(dp_chan_id, dp_id);
    }

    /*compare*/
    for(comb_idx = 0; comb_idx < SYS_TMM_LANE_NUM_PER_HSS; comb_idx++)
    {
        SYS_CONDITION_CONTINUE((0xff == src_lport_comb[comb_idx]) && (0xff == dst_lport_comb[comb_idx]));

        lane_id_tmp = comb_idx;
        
        /*if src and dst lport are equal, remain this port*/
        if(src_lport_comb[comb_idx] == dst_lport_comb[comb_idx])
        {
            target->lport_list[lport_idx].lport    = dst_lport_comb[comb_idx];
            target->lport_list[lport_idx].chan_id  = dst_chan_comb[comb_idx];
            target->lport_list[lport_idx].upt_flag = SYS_DS_LPORT_REMAIN;
            /*add port-serdes relation*/
            for(serdes_idx = 0; serdes_idx < target->serdes_num; serdes_idx++)
            {
                /*add serdes relation to port list*/
                target->lport_list[lport_idx].serdes_relate[target->lport_list[lport_idx].serdes_relate_num].serdes_list_idx
                    = serdes_idx;
                target->lport_list[lport_idx].serdes_relate[target->lport_list[lport_idx].serdes_relate_num].relate_flag
                    = (serdes_idx < lane_num) ? SYS_DS_LPORT_SERDES_NEW : SYS_DS_LPORT_SERDES_OLD;
                (target->lport_list[lport_idx].serdes_relate_num)++;
                /*add related lport idx to serdes list*/
                SYS_CONDITION_CONTINUE(SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id_tmp) != 
                                       target->serdes_list[serdes_idx].logic_serdes_id);
                target->serdes_list[serdes_idx].dst_lport_idx = lport_idx;
            }
            lport_idx++;
            (target->lport_num)++;
        }
        /*if src lport exist & dst lport vanished, drop this port*/
        else if((0xff != src_lport_comb[comb_idx]) && (0xff == dst_lport_comb[comb_idx]))
        {
            target->lport_list[lport_idx].lport    = src_lport_comb[comb_idx];
            target->lport_list[lport_idx].chan_id  = src_chan_comb[comb_idx];
            target->lport_list[lport_idx].upt_flag = SYS_DS_LPORT_DROP;
            
            find_flag = FALSE;
            for(serdes_idx = 0; serdes_idx < target->serdes_num; serdes_idx++)
            {
                /*find this serdes start & end point before add*/
                if(SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id_tmp) == target->serdes_list[serdes_idx].logic_serdes_id)
                {
                    find_flag = TRUE;
                }
                else if(target->lport_list[lport_idx].serdes_relate_num >= src_serdes_num[comb_idx])
                {
                    find_flag = FALSE;
                }
                SYS_CONDITION_CONTINUE(!find_flag);
                
                /*add serdes relation to port list*/
                target->lport_list[lport_idx].serdes_relate[target->lport_list[lport_idx].serdes_relate_num].serdes_list_idx
                    = serdes_idx;
                target->lport_list[lport_idx].serdes_relate[target->lport_list[lport_idx].serdes_relate_num].relate_flag
                    = SYS_DS_LPORT_SERDES_OLD;
                (target->lport_list[lport_idx].serdes_relate_num)++;
            }
            lport_idx++;
            (target->lport_num)++;
        }
        /*if src lport vanished & dst lport exist, add this port*/
        else if((0xff == src_lport_comb[comb_idx]) && (0xff != dst_lport_comb[comb_idx]))
        {
            target->lport_list[lport_idx].lport    = dst_lport_comb[comb_idx];
            target->lport_list[lport_idx].chan_id  = dst_chan_comb[comb_idx];
            target->lport_list[lport_idx].upt_flag = SYS_DS_LPORT_ADD;

            find_flag = FALSE;
            for(serdes_idx = 0; serdes_idx < target->serdes_num; serdes_idx++)
            {
                /*find this serdes start & end point before add*/
                if(SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id_tmp) == target->serdes_list[serdes_idx].logic_serdes_id)
                {
                    find_flag = TRUE;
                }
                else if(target->lport_list[lport_idx].serdes_relate_num >= dst_serdes_num[comb_idx])
                {
                    find_flag = FALSE;
                }
                SYS_CONDITION_CONTINUE(!find_flag);
                
                /*add serdes relation to port list*/
                target->lport_list[lport_idx].serdes_relate[target->lport_list[lport_idx].serdes_relate_num].serdes_list_idx
                    = serdes_idx;
                target->lport_list[lport_idx].serdes_relate[target->lport_list[lport_idx].serdes_relate_num].relate_flag
                    = SYS_DS_LPORT_SERDES_NEW;
                (target->lport_list[lport_idx].serdes_relate_num)++;
                /*add related lport idx to serdes list*/
                target->serdes_list[serdes_idx].dst_lport_idx = lport_idx;
            }
            lport_idx++;
            (target->lport_num)++;
        }
        /*illegal: src & dst lport all exist but not equal*/
        else
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% CDG: src and dst lport combination error!\n");
        }
    }

    /*add ovclk*/
    for(serdes_idx = 0; serdes_idx < target->serdes_num; serdes_idx++)
    {
        target->serdes_list[serdes_idx].ovclk_flag = 
            ((CTC_CHIP_SERDES_OCS_MODE_NONE == overclocking_speed) && 
            SYS_TMM_MODE_IS_PAM4(target->serdes_list[serdes_idx].dst_mode)) ? 
            CTC_CHIP_SERDES_OCS_MODE_51_56G : overclocking_speed;
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_dynamic_switch_para_check(uint8 lchip, uint8 logic_serdes_id, uint8 dst_mode, uint8 ovclk, uint8* p_dup_flag)
{
    uint16 lport;
    uint8  hss_id;
    uint8  lane_id;
    uint8  src_mode; 
    uint8  src_ovclk = 0;
    sys_datapath_lport_attr_t*    port_attr = NULL;
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    hss_id    = SYS_TMM_CPUMAC_HSS_ID;
    lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_id);
    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    SYS_CONDITION_RETURN((NULL == p_hss_vec), CTC_E_INVALID_PTR);
    src_mode  = p_hss_vec->serdes_info[lane_id].mode;
    src_ovclk = p_hss_vec->serdes_info[lane_id].overclocking_speed;
    if((src_ovclk == ovclk) && (src_mode == dst_mode))
    {
        SYS_USW_VALID_PTR_WRITE(p_dup_flag, TRUE);
        return CTC_E_NONE;
    }
    else
    {
        SYS_USW_VALID_PTR_WRITE(p_dup_flag, FALSE);
    }

    if((CTC_CHIP_SERDES_XFI_MODE != dst_mode) && (CTC_CHIP_SERDES_SGMII_MODE != dst_mode) && 
       (CTC_CHIP_SERDES_XLG_MODE != dst_mode) && (CTC_CHIP_SERDES_CG_MODE != dst_mode) && 
       (CTC_CHIP_SERDES_2DOT5G_MODE != dst_mode) && (CTC_CHIP_SERDES_XXVG_MODE != dst_mode) && 
       (CTC_CHIP_SERDES_LG_MODE != dst_mode) &&  (CTC_CHIP_SERDES_NONE_MODE != dst_mode))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Unsupported mode %u, logic serdes %u\n", 
            dst_mode, logic_serdes_id);
        return CTC_E_NOT_SUPPORT;
    }

    /* When cpumac_dp0_network_en not equal cpumac_dp1_network_en, dno't support 40G/100G */
    if(((CTC_CHIP_SERDES_XLG_MODE == dst_mode) || (CTC_CHIP_SERDES_CG_MODE == dst_mode)) && 
           (p_usw_datapath_master[lchip]->cpumac_dp0_network_en !=    p_usw_datapath_master[lchip]->cpumac_dp1_network_en))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Unsupported mode %u, logic serdes %u\n", 
            dst_mode, logic_serdes_id);
        return CTC_E_NOT_SUPPORT;
    }
 
    if (TMM_SERDES_DYN_FORBID_QI != p_hss_vec->serdes_info[lane_id].is_dyn)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Dynamic switch is not supported! hss_id %u, lane_id %u\n", 
            hss_id, lane_id);
        return CTC_E_NOT_SUPPORT;
    } 
 
    /*port attr check*/
    lport = p_hss_vec->serdes_info[lane_id].lport;
    port_attr = sys_usw_datapath_get_port_capability(lchip, lport);
    if((NULL != port_attr) && (!SYS_TMM_IS_MODE_NONE(src_mode)))
    {
        if(!SYS_DMPS_CPU_MAC_PORT)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC is not used! lport %u\n", lport);
            return CTC_E_INVALID_CONFIG;
        } 
    }
    
    return CTC_E_NONE;
}

int32
sys_tmm_dynamic_switch_para_check(uint8 lchip, uint8 logic_serdes_id, uint8 dst_mode, uint8 dst_ovclk, 
                                             uint8* p_dup_flag, uint8 remap_flag)
{
    uint16 lport;
    uint8  hss_id;
    uint8  lane_id;
    uint8  idx;
    uint8  lane_quad_base;
    uint8  src_mode;
    uint8  hss_type;
    uint8  src_ovclk = 0;
    uint8  dst_ovclk_fix;
    uint8  dp_id = SYS_TMM_GET_DP_ID_FROM_SERDES(logic_serdes_id);
    uint8  txqm_id = 0;
    uint8  dp_txqm_id = 0;
    uint16 dp_mac_id = 0;
    uint16 txqm_mac_id = 0;
    uint32 quad_bw[4] = {0};
    uint32 max_bw_txqm      = (500 == p_usw_datapath_master[lchip]->core_plla) ? 200 : 
                              (800 == p_usw_datapath_master[lchip]->core_plla) ? 250 : 400;
    sys_cal_info_collect_t*    cal_info = NULL;
    sys_datapath_lport_attr_t*    port_attr = NULL;
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    CTC_ERROR_RETURN(_sys_tmm_datapath_check_subtype_pcsmode(lchip, dst_mode, logic_serdes_id));

    if(SYS_TMM_CPUMAC_SERDES_START_ID <= logic_serdes_id)
    {
        CTC_ERROR_RETURN(_sys_tmm_cpumac_dynamic_switch_para_check(lchip, logic_serdes_id, dst_mode, dst_ovclk, p_dup_flag));
        return CTC_E_NONE;
    }

    dst_ovclk_fix = (SYS_TMM_MODE_IS_PAM4(dst_mode) && (CTC_CHIP_SERDES_OCS_MODE_NONE == dst_ovclk)) ? 
                    CTC_CHIP_SERDES_OCS_MODE_51_56G : dst_ovclk;

    hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logic_serdes_id);
    lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_id);
    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    SYS_CONDITION_RETURN((NULL == p_hss_vec), CTC_E_INVALID_PTR);
    src_mode  = p_hss_vec->serdes_info[lane_id].mode;
    src_ovclk = p_hss_vec->serdes_info[lane_id].overclocking_speed;

    if((src_ovclk == dst_ovclk_fix) && (src_mode == dst_mode))
    {
        SYS_USW_VALID_PTR_WRITE(p_dup_flag, TRUE);
        return CTC_E_NONE;
    }
    else
    {
        SYS_USW_VALID_PTR_WRITE(p_dup_flag, FALSE);
    }

    if((CTC_CHIP_SERDES_XFI_MODE != dst_mode) && (CTC_CHIP_SERDES_SGMII_MODE != dst_mode) && 
       (CTC_CHIP_SERDES_QSGMII_MODE != dst_mode) && (CTC_CHIP_SERDES_XLG_MODE != dst_mode) && 
       (CTC_CHIP_SERDES_CG_MODE != dst_mode) && (CTC_CHIP_SERDES_2DOT5G_MODE != dst_mode) && 
       (CTC_CHIP_SERDES_XXVG_MODE != dst_mode) && (CTC_CHIP_SERDES_LG_MODE != dst_mode) && 
       (CTC_CHIP_SERDES_LG_R1_MODE != dst_mode) && (CTC_CHIP_SERDES_CG_R2_MODE != dst_mode) && 
       (CTC_CHIP_SERDES_CCG_R4_MODE != dst_mode) && (CTC_CHIP_SERDES_CDG_R8_MODE != dst_mode) &&
       (CTC_CHIP_SERDES_NONE_MODE != dst_mode))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Unsupported mode %u, logic serdes %u\n", 
            dst_mode, logic_serdes_id);
        return CTC_E_NOT_SUPPORT;
    }

    if (TMM_SERDES_DYN_FORBID_ALL == p_hss_vec->serdes_info[lane_id].is_dyn)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Dynamic switch is not supported! hss_id %u, lane_id %u\n", 
            hss_id, lane_id);
        return CTC_E_NOT_SUPPORT;
    }

    /*HS quad lane, only 0 & 2 support PAM4 modes*/
    if(SYS_DATAPATH_HSS_TYPE_15G == p_hss_vec->hss_type)
    {
        if(SYS_TMM_MODE_IS_PAM4(dst_mode) && ((1 == (lane_id % 4)) || (3 == (lane_id % 4))))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% HS quad lane only 0 & 2 or 4 & 6 support PAM4 modes! lane_id %u\n", 
                lane_id);
            return CTC_E_NOT_SUPPORT;
        }
    }

    /*QSGMII check*/
    if(CTC_CHIP_SERDES_QSGMII_MODE == dst_mode)
    {
        if(!SYS_TMM_IS_LOGICAL_SERDES_SUPPORT_QSGMII(logic_serdes_id))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% This port cannot be QSGMII mode! logic_serdes_id %u\n", 
                logic_serdes_id);
            return CTC_E_NOT_SUPPORT;
        }
        if(TMM_SERDES_DYN_FORBID_QI == p_hss_vec->serdes_info[lane_id].is_dyn)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% QSGMII switch is forbidden! logic_serdes_id %u\n", 
                logic_serdes_id);
            return CTC_E_NOT_SUPPORT;
        }
        else if((remap_flag) && (HSS15G_LANE_NUM > (lane_id+1)) && 
            (TMM_SERDES_DYN_FORBID_QI == p_hss_vec->serdes_info[lane_id+1].is_dyn))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% QSGMII switch is forbidden! logic_serdes_id %u\n", 
                logic_serdes_id+1);
            return CTC_E_NOT_SUPPORT;
        }
    }

    /*HS0&1 do not support 200G/400G*/
    SYS_TMM_GET_HSS_TYPE(hss_id, hss_type);
    if(((CTC_CHIP_SERDES_CCG_R4_MODE == dst_mode) || (CTC_CHIP_SERDES_CDG_R8_MODE == dst_mode)) && 
        (SYS_DATAPATH_HSS_TYPE_28G != hss_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% This port cannot be 200G/400G mode! logic_serdes_id %u\n", 
            logic_serdes_id);
        return CTC_E_NOT_SUPPORT;
    }

    /*port attr check*/
    lport = p_hss_vec->serdes_info[lane_id].lport;
    port_attr = sys_usw_datapath_get_port_capability(lchip, lport);
    if((NULL != port_attr) && (!SYS_TMM_IS_MODE_NONE(src_mode)))
    {
        if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC is not used! lport %u\n", lport);
            return CTC_E_INVALID_CONFIG;
        }

        if(CTC_PORT_XPIPE_TYPE_0 != port_attr->xpipe_en)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "  %% X-PIPE is enable, cannot do switch! lport %u\n", lport);
            return CTC_E_NOT_SUPPORT;
        }
    }

    lane_quad_base = lane_id/4*4;
    if((SYS_DATAPATH_HSS_TYPE_15G == hss_type) && (CTC_CHIP_SERDES_CG_R2_MODE == dst_mode) && (src_ovclk == dst_ovclk_fix) && 
       (SYS_TMM_USELESS_ID8 == p_hss_vec->serdes_info[lane_quad_base+2].physical_serdes_id))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% This logic serdes has no serdes! lane %u\n", lane_quad_base+2);
        return CTC_E_NOT_SUPPORT;
    }

    if(remap_flag)
    {
        if((CTC_CHIP_SERDES_XLG_MODE == dst_mode) || (CTC_CHIP_SERDES_CG_MODE == dst_mode))
        {
            for(idx = 0; idx < 4; idx++)
            {
                if((SYS_TMM_USELESS_ID8 == p_hss_vec->serdes_info[lane_quad_base+idx].physical_serdes_id))
                {
                    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% This logic serdes has no serdes! lane %u\n", lane_quad_base+idx);
                    return CTC_E_NOT_SUPPORT;
                }
            }
        }

        if(CTC_CHIP_SERDES_CG_R2_MODE == dst_mode)
        {
            cal_info = (sys_cal_info_collect_t*)mem_malloc(MEM_DMPS_MODULE, 
                (SYS_TMM_MAX_MAC_NUM_PER_DP+SYS_TMM_CPUMAC_SERDES_NUM/2) * sizeof(sys_cal_info_collect_t));
            SYS_CONDITION_RETURN(NULL == cal_info, CTC_E_NO_MEMORY);

            SYS_TMM_GET_TXQM_ID_BY_HSS_ID(hss_id, txqm_id);
            dp_txqm_id = txqm_id % SYS_TMM_TXQM_NUM_PER_DP;
            (void)sys_tmm_calendar_speed_info_collect(lchip, cal_info, dp_id, dp_txqm_id, SYS_TMM_MAC_FIXLEN_CAL);
            for(txqm_mac_id = 0; txqm_mac_id < SYS_TMM_MAX_MAC_NUM_PER_TXQM; txqm_mac_id++)
            {
                dp_mac_id = txqm_mac_id + dp_txqm_id*SYS_TMM_MAX_MAC_NUM_PER_TXQM;
                SYS_CONDITION_CONTINUE(cal_info[dp_mac_id].cl_type == SYS_ALLOC_NONE_MODE);
                idx = txqm_mac_id < 16 ? 0 : (txqm_mac_id < 32 ? 1 : (txqm_mac_id < 36 ? 2 : 3));
                quad_bw[idx] += cal_info[dp_mac_id].speed;
            }
            mem_free(cal_info);

            idx = logic_serdes_id % 16 / 4;
            quad_bw[idx] = 100;
            if(quad_bw[0] + quad_bw[1] + quad_bw[2] + quad_bw[3] > max_bw_txqm)
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Total BW exceeds %u\n", max_bw_txqm);
                return CTC_E_NOT_SUPPORT;
            }
        }
    }
    
    return CTC_E_NONE;
}

/*only 100GR2 need remap, including other -> 100GR2 and 100GR2 -> other*/
uint8
sys_tmm_dynamic_switch_judge_remap(uint8 lchip, uint8 logic_serdes_id, uint8 dst_mode)
{
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    uint8 hss_id  = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logic_serdes_id);
    uint8 lane_id = SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_id);

    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    SYS_CONDITION_RETURN((NULL == p_hss_vec), FALSE);

    if(SYS_DATAPATH_HSS_TYPE_15G == p_hss_vec->hss_type)
    {
        if((CTC_CHIP_SERDES_CG_R2_MODE == dst_mode) && (CTC_CHIP_SERDES_CG_R2_MODE != p_hss_vec->serdes_info[lane_id/4*4].mode))
        {
            return TRUE;
        }
        if((CTC_CHIP_SERDES_CG_R2_MODE == p_hss_vec->serdes_info[lane_id/4*4].mode) && (CTC_CHIP_SERDES_CG_R2_MODE != dst_mode))
        {
            if((0 == lane_id % 4) || (1 == lane_id % 4))
            {
                return TRUE;
            }
        }
    }

    return FALSE;
}

int32
sys_tmm_dynamic_switch_logic_1_2_swap(uint8 lchip, uint8 logic_serdes_raw)
{
    uint8 hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logic_serdes_raw);
    uint8 lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_raw);
    uint8 quad_base = lane_id/4*4;
    uint8 lsd_tmp1  = 0;
    uint8 lsd_tmp2  = 0;
    uint8 logic_id_buf;
    uint8 txqm_id;
    uint32 tb_idx;
    uint8 dp_chan1  = SYS_TMM_CHANNEL_NUM_PER_DP;
    uint8 dp_chan2  = SYS_TMM_CHANNEL_NUM_PER_DP;
    uint8 num1      = 0;
    uint8 num2      = 0;
    uint8 lsd1      = 0;
    uint8 lsd2      = 0;
    uint8 idx;
    uint8 dp_chan_id;
    uint8 dp_id = SYS_TMM_GET_DP_ID_FROM_SERDES(logic_serdes_raw);
    sys_datapath_serdes_info_t       serdes_info = {0};
    sys_datapath_hss_attribute_t*    p_hss_vec   = NULL;
    sys_datapath_lport_attr_t*       port_attr = NULL;

    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s entered! logic_serdes_raw %d\n", __FUNCTION__, logic_serdes_raw);

    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    SYS_CONDITION_RETURN((NULL == p_hss_vec), CTC_E_INVALID_PTR);

    /*1. soft tables exchange*/
    /*serdes_info*/
    sal_memcpy(&serdes_info, &(p_hss_vec->serdes_info[quad_base+1]), sizeof(sys_datapath_serdes_info_t));
    sal_memcpy(&(p_hss_vec->serdes_info[quad_base+1]), &(p_hss_vec->serdes_info[quad_base+2]), 
        sizeof(sys_datapath_serdes_info_t));
    sal_memcpy(&(p_hss_vec->serdes_info[quad_base+2]), &serdes_info, sizeof(sys_datapath_serdes_info_t));

    logic_id_buf = p_hss_vec->serdes_info[quad_base+1].lane_id;
    p_hss_vec->serdes_info[quad_base+1].lane_id = p_hss_vec->serdes_info[quad_base+2].lane_id;
    p_hss_vec->serdes_info[quad_base+2].lane_id = logic_id_buf;
    logic_id_buf = p_hss_vec->serdes_info[quad_base+1].group;
    p_hss_vec->serdes_info[quad_base+1].group = p_hss_vec->serdes_info[quad_base+2].group;
    p_hss_vec->serdes_info[quad_base+2].group = logic_id_buf;
    /*chan_2_logic_serdes*/
    lsd_tmp1 = SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, quad_base+1);
    lsd_tmp2 = SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, quad_base+2);
    for(dp_chan_id = 0; dp_chan_id < SYS_TMM_CHANNEL_NUM_PER_DP; dp_chan_id++)
    {
        if(p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan_id].logic_serdes_id == lsd_tmp1)
        {
            num1++;
            dp_chan1 = dp_chan_id;
        }
        if(p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan_id].logic_serdes_id == lsd_tmp2)
        {
            num2++;
            dp_chan2 = dp_chan_id;
        }
    }
    dp_chan1 -= (num1 - 1);
    dp_chan2 -= (num2 - 1);
    lsd1 = (SYS_TMM_CHANNEL_NUM_PER_DP <= dp_chan1) ? lsd_tmp1 : 
        p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan1].logic_serdes_id;
    lsd2 = (SYS_TMM_CHANNEL_NUM_PER_DP <= dp_chan2) ? lsd_tmp2 : 
        p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan2].logic_serdes_id;
    if((SYS_TMM_CHANNEL_NUM_PER_DP > dp_chan1) && (SYS_TMM_CHANNEL_NUM_PER_DP <= dp_chan2))
    {
        for(idx = 0; idx < num1; idx++)
        {
            p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan1+idx].logic_serdes_id = lsd2;
        }
    }
    if((SYS_TMM_CHANNEL_NUM_PER_DP > dp_chan2) && (SYS_TMM_CHANNEL_NUM_PER_DP <= dp_chan1))
    {
        for(idx = 0; idx < num2; idx++)
        {
            p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][dp_chan2+idx].logic_serdes_id = lsd1;
        }
    }

    /*2. hw table reconfig*/
    CTC_ERROR_RETURN(_sys_tmm_mac_hss_rxswaplane_config(lchip, hss_id));
    
    /*clear McHataTxChanMap_chanMap_f to 0x3f*/
    SYS_TMM_GET_TXQM_ID_BY_HSS_ID(hss_id, txqm_id);
    tb_idx = p_hss_vec->serdes_info[quad_base+1].physical_serdes_id % 
        (SYS_TMM_IS_PCS_X16(txqm_id) ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM);
    CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tb_idx, McHataTxChanMap_chanMap_f, 0x3f));
    tb_idx = p_hss_vec->serdes_info[quad_base+2].physical_serdes_id % 
        (SYS_TMM_IS_PCS_X16(txqm_id) ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM);
    CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tb_idx, McHataTxChanMap_chanMap_f, 0x3f));
    
    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, p_hss_vec->serdes_info[quad_base+1].lport, &port_attr));
    if(!SYS_TMM_IS_MODE_NONE(port_attr->pcs_mode))
    {
        tb_idx = port_attr->pcs_idx;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tb_idx, McHataTxChanMap_rxChanMap_f, 0x3f));
        tb_idx = port_attr->multi_serdes_id[0] % 
            (SYS_TMM_IS_PCS_X16(txqm_id) ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM) + 16;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tb_idx, McHataTxChanMap_rxChanMap_f, 0x3f));
        tb_idx = TXQM_INNER_MAC_ID(port_attr->mac_id);
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_port_map(lchip, txqm_id, tb_idx, 0x3f));
    }
    
    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, p_hss_vec->serdes_info[quad_base+2].lport, &port_attr));
    if(!SYS_TMM_IS_MODE_NONE(port_attr->pcs_mode))
    {
        tb_idx = port_attr->pcs_idx;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tb_idx, McHataTxChanMap_rxChanMap_f, 0x3f));
        tb_idx = port_attr->multi_serdes_id[0] % 
            (SYS_TMM_IS_PCS_X16(txqm_id) ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM) + 16;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tb_idx, McHataTxChanMap_rxChanMap_f, 0x3f));
        tb_idx = TXQM_INNER_MAC_ID(port_attr->mac_id);
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_port_map(lchip, txqm_id, tb_idx, 0x3f));
    }

    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s end!\n", __FUNCTION__);

    return CTC_E_NONE;
}

/*McMacTxChanIdLaneCfg.cfgTxChanIdLane_[0-15]_cfgTxChanIdLane[5:0]*/
/*McPcsX8LanesRxPhyLaneCfg.cfgRxPhyLane_[0-7]_cfgRxChanId[4:0] and X16 A, B*/
/*McPcsX8LanesRxLaneSwapCfg.cfgRxSwapLane_[0-7]_cfgRxLaneId[2:0] and X16 A, B*/
/*McPcsX8LanesTxLaneMapCfg.cfgTxLaneMapLane_[0-7]_cfgTxChanId[4:0] and X16*/
/*McPcsX8LanesTxLaneMapCfg.cfgTxLaneMapLane_[0-7]_cfgTxLaneId[2:0] and X16*/
int32
sys_tmm_logic_physic_swap_hw_table_upt(uint8 lchip, sys_tmm_logic_physic_remap_t* p_logic_2_physic)
{
    uint8  lane_id;
    uint8  is_x16     = 0;
    uint8  hss_id     = p_logic_2_physic->hss_id;
    uint32 mac_lane   = 0;
    uint8  txqm_id    = 0;
    uint8  x8_x16_idx = 0;
    uint32 tbl_id     = 0;
    uint32 fld_id     = 0;
    uint32 index      = 0;
    uint32 cmd        = 0;
    uint32 value      = 0;
    McMacTxChanIdLaneCfg_m     mac_tx_cfg;
    McPcsX8LanesRxPhyLaneCfg_m pcs_rx_cfg;
    uint32 pcs_tx_map[16] = {0};

    /*McMacTxChanIdLaneCfg.cfgTxChanIdLane_[0-15]_cfgTxChanIdLane[5:0]*/
    tbl_id = McMacTxChanIdLaneCfg_t;
    value = 0x3f;
    SYS_TMM_GET_TXQM_ID_BY_HSS_ID(hss_id, txqm_id);
    is_x16 = SYS_TMM_IS_PCS_X16(txqm_id);

    index = DRV_INS(txqm_id, 0);
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));
    for(lane_id = 0; lane_id < SYS_TMM_LANE_NUM_PER_HSS; lane_id++)
    {
        SYS_CONDITION_CONTINUE(0 == p_logic_2_physic->logic_lane[lane_id].change_flag);
        SYS_CONDITION_CONTINUE(SYS_TMM_USELESS_ID8  == p_logic_2_physic->logic_lane[lane_id].physic_serdes_id);

        mac_lane = p_logic_2_physic->logic_lane[lane_id].physic_serdes_id % 
                   (is_x16 ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM);
        fld_id   = McMacTxChanIdLaneCfg_cfgTxChanIdLane_0_cfgTxChanIdLane_f + mac_lane * 
                   (McMacTxChanIdLaneCfg_cfgTxChanIdLane_1_cfgTxChanIdLane_f - 
                   McMacTxChanIdLaneCfg_cfgTxChanIdLane_0_cfgTxChanIdLane_f);

        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mac_tx_cfg);
    }
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));

    /*McPcsX8LanesRxPhyLaneCfg.cfgRxPhyLane_[0-7]_cfgRxChanId[4:0] and X16 A, B*/
    tbl_id = is_x16 ? 
             (SYS_TMM_JUDGE_PCSX16A(hss_id) ? McPcsX16LanesRxAPhyLaneCfg_t : McPcsX16LanesRxBPhyLaneCfg_t) : 
             McPcsX8LanesRxPhyLaneCfg_t;
    value = 0x1f;
    SYS_TMM_GET_PCSXIDX(txqm_id, x8_x16_idx);

    index = DRV_INS(x8_x16_idx, 0);
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_rx_cfg));
    for(lane_id = 0; lane_id < SYS_TMM_LANE_NUM_PER_HSS; lane_id++)
    {
        SYS_CONDITION_CONTINUE(0 == p_logic_2_physic->logic_lane[lane_id].change_flag);
        SYS_CONDITION_CONTINUE(SYS_TMM_USELESS_ID8 == p_logic_2_physic->logic_lane[lane_id].physic_serdes_id);

        switch(tbl_id)
        {
            case McPcsX16LanesRxAPhyLaneCfg_t:
                fld_id = McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f + 
                         p_logic_2_physic->logic_lane[lane_id].physic_lane * 
                         (McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_1_cfgRxChanId_f - 
                         McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f);
                break;
            case McPcsX16LanesRxBPhyLaneCfg_t:
                fld_id = McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f + 
                         p_logic_2_physic->logic_lane[lane_id].physic_lane * 
                         (McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_1_cfgRxChanId_f - 
                         McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f);
                break;
            case McPcsX8LanesRxPhyLaneCfg_t:
            default:
                fld_id = McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f + 
                         p_logic_2_physic->logic_lane[lane_id].physic_lane * 
                         (McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_1_cfgRxChanId_f - 
                         McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f);
                break;
        }
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &pcs_rx_cfg);
    }
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_rx_cfg));

    /*McPcsX8LanesRxLaneSwapCfg.cfgRxSwapLane_[0-7]_cfgRxLaneId[2:0] and X16 A, B*/
    CTC_ERROR_RETURN(_sys_tmm_mac_hss_rxswaplane_config(lchip, hss_id));

    /*McPcsX8LanesTxLaneMapCfg.cfgTxLaneMapLane_[0-7]_cfgTxChanId[4:0] and X16*/
    tbl_id = is_x16 ? McPcsX16LanesTxLaneMapCfg_t : McPcsX8LanesTxLaneMapCfg_t;
    value = 0x1f;

    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_tx_map));
    for(lane_id = 0; lane_id < SYS_TMM_LANE_NUM_PER_HSS; lane_id++)
    {
        SYS_CONDITION_CONTINUE(0 == p_logic_2_physic->logic_lane[lane_id].change_flag);
        SYS_CONDITION_CONTINUE(SYS_TMM_USELESS_ID8 == p_logic_2_physic->logic_lane[lane_id].physic_serdes_id);
        
        if(is_x16)
        {
            fld_id = McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f + mac_lane * 
                     (McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxChanId_f - 
                     McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f);
        }
        else
        {
            fld_id = McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f + mac_lane * 
                     (McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxChanId_f - 
                     McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f);
        }
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &pcs_tx_map);
    }
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_tx_map));
    
    /*clear McHataTxChanMap_chanMap_f to 0x3f*/
    /*clear McHataTxChanMap_rxChanMap_f to 0x3f*/
    /*clear McHataTxPortMap_portMap_f to 0x3f*/
    for(lane_id = 0; lane_id < SYS_TMM_LANE_NUM_PER_HSS; lane_id++)
    {
        SYS_CONDITION_CONTINUE(0 == p_logic_2_physic->logic_lane[lane_id].change_flag);
        SYS_CONDITION_CONTINUE(SYS_TMM_USELESS_ID8 == p_logic_2_physic->logic_lane[lane_id].physic_serdes_old);
        tbl_id = p_logic_2_physic->logic_lane[lane_id].physic_serdes_old % 
            (is_x16 ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM);
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tbl_id, McHataTxChanMap_chanMap_f, 0x3f));
        tbl_id = ((1 == p_logic_2_physic->hss_id) || (3 == p_logic_2_physic->hss_id) || 
            (7 == p_logic_2_physic->hss_id) || (9 == p_logic_2_physic->hss_id)) ? (lane_id+8) : lane_id;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tbl_id, McHataTxChanMap_rxChanMap_f, 0x3f));
        tbl_id = p_logic_2_physic->logic_lane[lane_id].physic_serdes_old % 
            (is_x16 ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM) + 16;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tbl_id, McHataTxChanMap_rxChanMap_f, 0x3f));

        tbl_id = lane_id + (((1 == p_logic_2_physic->hss_id) || (3 == p_logic_2_physic->hss_id) || 
            (7 == p_logic_2_physic->hss_id) || (9 == p_logic_2_physic->hss_id)) ? 32 : 0);
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_port_map(lchip, txqm_id, tbl_id, 0x3f));
    }
        
    /*McPcsX8LanesTxLaneMapCfg.cfgTxLaneMapLane_[0-7]_cfgTxLaneId[2:0] and X16  omitted*/

    return CTC_E_NONE;
}

int32
sys_tmm_logic_physic_swap_soft_table_upt(uint8 lchip, sys_tmm_logic_physic_remap_t* p_logic_2_physic, 
                                                      uint8 valid_lsd_old[], uint8 valid_lsd_new[], uint8 valid_cnt)
{
    uint8 lane_id         = 0;
    uint8 lane_id1        = 0;
    uint8 chan_idx        = 0;
    uint8 dp_id           = SYS_TMM_GET_DP_ID_FROM_HSSID(p_logic_2_physic->hss_id);
    ctc_chip_serdes_info_t serdes_switch = {0};
    sys_datapath_serdes_info_t serdes_info_buf[SYS_TMM_LANE_NUM_PER_HSS] = {{0}};
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;
    sys_tmm_logic_physic_remap_elem_t* p_psd = NULL;

    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, p_logic_2_physic->hss_id);
    SYS_CONDITION_RETURN((NULL == p_hss_vec), CTC_E_INVALID_PTR);

    /*1.  switch influenced serdes to none mode*/
    for(lane_id = 0; lane_id < SYS_TMM_LANE_NUM_PER_HSS; lane_id++)
    {
        p_psd = &(p_logic_2_physic->logic_lane[lane_id]);
        SYS_CONDITION_CONTINUE(0 == p_psd->change_flag);
        
        serdes_switch.serdes_mode = CTC_CHIP_SERDES_NONE_MODE;
        if(p_psd->physic_serdes_old == p_psd->physic_serdes_id)
        {
            serdes_switch.serdes_id = p_psd->physic_serdes_old;
            (void)_sys_tmm_serdes_set_mode_proc(lchip, &serdes_switch);
        }
        else
        {
            if(SYS_TMM_USELESS_ID8 != p_psd->physic_serdes_id)
            {
                serdes_switch.serdes_id = p_psd->physic_serdes_id;
                (void)_sys_tmm_serdes_set_mode_proc(lchip, &serdes_switch);
            }
            if(SYS_TMM_USELESS_ID8 != p_psd->physic_serdes_old)
            {
                serdes_switch.serdes_id = p_psd->physic_serdes_old;
                (void)_sys_tmm_serdes_set_mode_proc(lchip, &serdes_switch);
            }
        }
    }

    /*2.  serdes info soft table update*/
    /*2.1 reassign hss serdes info*/
    for(lane_id = 0; lane_id < SYS_TMM_LANE_NUM_PER_HSS; lane_id++)
    {
        p_psd = &(p_logic_2_physic->logic_lane[lane_id]);
        /*for abandoned serdes 0xff, save serdes_info_buf as invalid*/
        if(SYS_TMM_USELESS_ID8 == p_psd->physic_serdes_id)
        {
            serdes_info_buf[lane_id].lport              = SYS_TMM_USELESS_ID16;
            serdes_info_buf[lane_id].physical_serdes_id = SYS_TMM_USELESS_ID8;
            serdes_info_buf[lane_id].lane_id            = lane_id;
            serdes_info_buf[lane_id].group              = lane_id;
        }
        /*for valid serdes, save serdes_info_buf as old serdes info */
        else
        {
            /*find this physic serdes in serdes info soft table, then copy to serdes_info_buf*/
            for(lane_id1 = 0; lane_id1 < SYS_TMM_LANE_NUM_PER_HSS; lane_id1++)
            {
                SYS_CONDITION_BREAK(p_hss_vec->serdes_info[lane_id1].physical_serdes_id == p_psd->physic_serdes_id);
            }
            if(SYS_TMM_LANE_NUM_PER_HSS > lane_id1)
            {
                sal_memcpy(&(serdes_info_buf[lane_id]), &(p_hss_vec->serdes_info[lane_id1]), sizeof(sys_datapath_serdes_info_t));
                serdes_info_buf[lane_id].lane_id = lane_id;
                serdes_info_buf[lane_id].group   = lane_id;
            }
        }
    }
    /*2.2 update new info to soft table*/
    sal_memcpy(p_hss_vec->serdes_info, &serdes_info_buf, HSS15G_LANE_NUM * sizeof(sys_datapath_serdes_info_t));

    /*3. update chan_2_logic_serdes*/
    lane_id1 = 0;
    for(chan_idx = 0; chan_idx < 128; chan_idx++)
    {
        SYS_CONDITION_BREAK(lane_id1 >= valid_cnt);
        SYS_CONDITION_CONTINUE(p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][chan_idx].logic_serdes_id != \
            SYS_TMM_GET_SERDES_ID_BY_LANE(p_logic_2_physic->hss_id, valid_lsd_old[lane_id1]));

        p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][chan_idx].logic_serdes_id = \
            SYS_TMM_GET_SERDES_ID_BY_LANE(p_logic_2_physic->hss_id, valid_lsd_new[lane_id1]);
        SYS_CONDITION_BREAK(chan_idx+1 >= 128);
        if(p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp_id][chan_idx+1].logic_serdes_id != \
            SYS_TMM_GET_SERDES_ID_BY_LANE(p_logic_2_physic->hss_id, valid_lsd_old[lane_id1]))
        {
            lane_id1++;
        }
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_serdes_map(uint8 lchip, void* p_data)
{
    uint16* p_map                 = ((ctc_chip_serdes_map_cfg_t*)p_data)->serdes_id;
    uint8  hss_id                = SYS_TMM_CPUMAC_HSS_ID;
    uint8  physic_id_start       = 0;
    uint8  physic_id_end         = 0;
    uint8  lane_id;
    uint8  lane_idx;
    uint8  idx;
    uint8  remap_flag[2]         = {FALSE, FALSE};
    uint8  valid_idx[2]          = {0};
    uint8  valid_lsd[2][SYS_TMM_LANE_NUM_PER_HSS] = {{0}};
    uint8  exist_flag[SYS_TMM_LANE_NUM_PER_HSS] = {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE};
    sys_tmm_logic_physic_remap_t logic_2_physic;
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;
    sys_tmm_logic_physic_remap_elem_t *p_psd = NULL;

    /*0. para check*/
    for(lane_id = 0; lane_id < CTC_HSS_SERDES_NUM; lane_id++)
    {
        SYS_CONDITION_BREAK(SYS_TMM_USELESS_ID8 != p_map[lane_id]);
    }
    if(CTC_HSS_SERDES_NUM <= lane_id)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% No valid serdes id!\n");
        return CTC_E_INVALID_PARAM;
    }
    hss_id = SYS_TMM_MAP_SERDES_TO_HSS_IDX(p_map[lane_id]);
    if(SYS_TMM_CPUMAC_HSS_ID <= hss_id)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% HSS %u do not support swap!\n", hss_id);
        return CTC_E_INVALID_PARAM;
    }

    sal_memset(&logic_2_physic, 0xff, sizeof(sys_tmm_logic_physic_remap_t));
    logic_2_physic.hss_id = hss_id;

    physic_id_start       = SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, 0);
    physic_id_end         = SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, 7);

    MAC_LOCK;

    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    if(p_hss_vec == NULL)
    {
        MAC_UNLOCK;
        return CTC_E_INVALID_PTR;
    }

    for(lane_id = 0; lane_id < SYS_TMM_LANE_NUM_PER_HSS; lane_id++)
    {
        if(((physic_id_start > p_map[lane_id]) || (physic_id_end < p_map[lane_id])) && 
           (SYS_TMM_USELESS_ID8 != p_map[lane_id]))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Serdes %u exceeds current hss!\n", p_map[lane_id]);
            MAC_UNLOCK;
            return CTC_E_INVALID_PARAM;
        }
        p_psd = &(logic_2_physic.logic_lane[lane_id]);
        if(SYS_TMM_USELESS_ID8 != p_psd->physic_serdes_id)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Serdes %u duplicates!\n", p_map[lane_id]);
            MAC_UNLOCK;
            return CTC_E_INVALID_PARAM;
        }

        if(SYS_TMM_USELESS_ID8 != p_map[lane_id])
        {
            if(CTC_E_NONE != _sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, p_map[lane_id], NULL))
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Serdes %u invalid!\n", p_map[lane_id]);
                MAC_UNLOCK;
                return CTC_E_INVALID_PARAM;
            }

            if(exist_flag[p_map[lane_id] % SYS_TMM_LANE_NUM_PER_HSS])
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Serdes %u duplicate!\n", p_map[lane_id]);
                MAC_UNLOCK;
                return CTC_E_INVALID_PARAM;
            }
            else
            {
                exist_flag[p_map[lane_id] % SYS_TMM_LANE_NUM_PER_HSS] = TRUE;
            }
        }

        /*fill logic_2_physic*/
        p_psd->physic_serdes_old = p_hss_vec->serdes_info[lane_id].physical_serdes_id;
        p_psd->physic_serdes_id  = p_map[lane_id];
        p_psd->physic_lane       = p_map[lane_id] % SYS_TMM_LANE_NUM_PER_HSS;
        if(SYS_TMM_USELESS_ID8 != p_psd->physic_serdes_old)
        {
            valid_lsd[0][valid_idx[0]] = lane_id;
            valid_idx[0]++;
        }
        if(SYS_TMM_USELESS_ID8 != p_psd->physic_serdes_id)
        {
            valid_lsd[1][valid_idx[1]] = lane_id;
            valid_idx[1]++;
        }
        if(p_psd->physic_serdes_id != p_psd->physic_serdes_old)
        {
            p_psd->change_flag = 1;
            if(!remap_flag[lane_id/4])
            {
                remap_flag[lane_id/4] = sys_tmm_dynamic_switch_judge_remap(lchip, 
                    SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id), CTC_CHIP_SERDES_NONE_MODE);
            }
        }
        else
        {
            p_psd->change_flag = 0;
        }
    }
    if(valid_idx[0] != valid_idx[1])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Valid mapping serdes number changed! %u %u\n", valid_idx[0], valid_idx[1]);
        MAC_UNLOCK;
        return CTC_E_INVALID_PARAM;
    }

    for(lane_idx = 0; lane_idx < valid_idx[0]; lane_idx++)
    {
        SYS_CONDITION_CONTINUE(valid_lsd[0][lane_idx] == valid_lsd[1][lane_idx]);
        /*add change flag for 0 1 255 255 -> 255 1 0 255*/
        for(idx = 0; idx < 2; idx++)
        {
            lane_id = valid_lsd[idx][lane_idx];
            SYS_CONDITION_CONTINUE(logic_2_physic.logic_lane[lane_id].change_flag);
            logic_2_physic.logic_lane[lane_id].change_flag = 2;
        }
        /*fix old valid logic serdes list based on 100GR2 remap_flag*/
        if((1 == valid_lsd[0][lane_idx] % 4) && (remap_flag[valid_lsd[0][lane_idx]/4]))
        {
            valid_lsd[0][lane_idx] += 1;
        }
    }

    /*1. soft tables reconfig*/
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_logic_physic_swap_soft_table_upt(lchip, &logic_2_physic, 
        valid_lsd[0], valid_lsd[1], valid_idx[0]));

    /*2. hw table reconfig*/
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_logic_physic_swap_hw_table_upt(lchip, &logic_2_physic));

    MAC_UNLOCK;

    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s end!\n", __FUNCTION__);

    return CTC_E_NONE;
}

int32
sys_tmm_mac_dynamic_switch_glb_info_check(uint8 lchip, uint8 hss_id, uint8 lane_id, 
                                                         sys_tmm_ds_target_attr_t *target)
{
    uint8  lane_id_base = lane_id / 4 * 4;
    uint8  quad_lane_idx;
    uint8  logic_serdes_id;
    uint8  serdes_list_idx;
    uint8  find_flag;
    uint8  speed;
    uint8  lane_num;
    uint32 speed_val;
    uint32 speed_sum = 0;
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    /*check is_dyn*/
    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    SYS_CONDITION_RETURN((NULL == p_hss_vec), CTC_E_INVALID_PTR);
    for(serdes_list_idx = 0; serdes_list_idx < target->serdes_num; serdes_list_idx++)
    {
        logic_serdes_id = target->serdes_list[serdes_list_idx].logic_serdes_id;
        switch(p_hss_vec->serdes_info[SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_id)].is_dyn)
        {
            case TMM_SERDES_DYN_FORBID_ALL:
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Logic serdes %u fobid dynamic switch!\n", logic_serdes_id);
                return CTC_E_NOT_SUPPORT;
            case TMM_SERDES_DYN_FORBID_QI:
                if(CTC_CHIP_SERDES_QSGMII_MODE == target->serdes_list[serdes_list_idx].dst_mode)
                {
                    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Logic serdes %u fobid QSGMII!\n", logic_serdes_id);
                    return CTC_E_NOT_SUPPORT;
                }
            case TMM_SERDES_DYN_ALLOW_ALL:
            default:
                break;
        }
    }

    /*check speed sum after ds (not really change tables)*/
    /*calculate speed sum of quad lanes*/
    SYS_CONDITION_RETURN((SYS_DATAPATH_HSS_TYPE_15G != p_hss_vec->hss_type), CTC_E_NONE);
    for(quad_lane_idx = 0; quad_lane_idx < 4; quad_lane_idx++)
    {
        logic_serdes_id = SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, (lane_id_base + quad_lane_idx));
        find_flag = FALSE;
        for(serdes_list_idx = 0; serdes_list_idx < target->serdes_num; serdes_list_idx++)
        {
            if(target->serdes_list[serdes_list_idx].logic_serdes_id == logic_serdes_id)
            {
                find_flag = TRUE;
                break;
            }
        }
        /*if this lane need change, add new speed to sum, else add serdes info speed to sum*/
        if(find_flag)
        {
            SYS_TMM_GET_LANE_NUM_BY_MODE(target->serdes_list[serdes_list_idx].dst_mode, lane_num);
            if(0 == target->serdes_list[serdes_list_idx].logic_serdes_id % lane_num)
            {
                SYS_TMM_GET_PORT_SPEED(target->serdes_list[serdes_list_idx].dst_mode, speed);
                SYS_DATAPATH_MODE_TO_SPEED(speed, speed_val);
                speed_sum += speed_val;
            }
        }
        else
        {
            if(0 == p_hss_vec->serdes_info[lane_id_base + quad_lane_idx].pcs_l_id)
            {
                SYS_TMM_GET_PORT_SPEED(p_hss_vec->serdes_info[lane_id_base + quad_lane_idx].mode, speed);
                SYS_DATAPATH_MODE_TO_SPEED(speed, speed_val);
                speed_sum += speed_val;
            }
        }
    }

    /*judgement*/
    if(100 < speed_sum)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Speed sum in quad lane exceeds 100G! hss_id %u, lane_id %u, speed_sum %u\n", 
            hss_id, lane_id, speed_sum);
        return CTC_E_NOT_SUPPORT;
    }
    
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_ds_get_quad_lane_num(uint8 lchip, uint8 hss_id, uint8 lane_id, uint8 dst_mode, 
                                             uint8 src_quad_comb[4], uint8 dst_quad_comb[4])
{
    uint8 quad_mode_comb_dict[26][4] = {
       /*quantity of serdes occupied by current mode*/
       /*lane 0  lane 1  lane 2  lane 3*/
        {1,      1,      1,      1}, /*0 */
        {1,      1,      1,      0}, /*1 */
        {1,      1,      2,      2}, /*2 */
        {1,      1,      0,      1}, /*3 */
        {1,      1,      0,      0}, /*4 */
        {1,      0,      1,      1}, /*5 */
        {1,      0,      1,      0}, /*6 */
        {1,      0,      2,      2}, /*7 */
        {1,      0,      0,      1}, /*8 */
        {1,      0,      0,      0}, /*9 */
        {2,      2,      1,      1}, /*10*/
        {2,      2,      1,      0}, /*11*/
        {2,      2,      2,      2}, /*12*/
        {2,      2,      0,      1}, /*13*/
        {2,      2,      0,      0}, /*14*/
        {4,      4,      4,      4}, /*15*/
        {0,      1,      1,      1}, /*16*/
        {0,      1,      1,      0}, /*17*/
        {0,      1,      2,      2}, /*18*/
        {0,      1,      0,      1}, /*19*/
        {0,      1,      0,      0}, /*20*/
        {0,      0,      1,      1}, /*21*/
        {0,      0,      1,      0}, /*22*/
        {0,      0,      2,      2}, /*23*/
        {0,      0,      0,      1}, /*24*/
        {0,      0,      0,      0}, /*25*/
    };
    uint8 switch_result[26][16] = {
       /*L0_S0  L1_S0  L2_S0  L3_S0  L0_S1  L1_S1  L2_S1  L3_S1  L0_S2  L1_S2  L2_S2  L3_S2  L0_S4  L1_S4  L2_S4  L3_S4 src combination*/
        {16,    5 ,    3 ,    1 ,    0,     0 ,    0 ,    0 ,    10,    10,    2 ,    2 ,    15,    15,    15,    15},   /*0 */ 
        {17,    6 ,    4 ,    1 ,    1,     1 ,    1 ,    0 ,    11,    11,    2 ,    2 ,    15,    15,    15,    15},   /*1 */ 
        {18,    7 ,    4 ,    4 ,    2,     2 ,    0 ,    0 ,    12,    12,    2 ,    2 ,    15,    15,    15,    15},   /*2 */ 
        {19,    8 ,    3 ,    4 ,    3,     3 ,    0 ,    3 ,    13,    13,    2 ,    2 ,    15,    15,    15,    15},   /*3 */ 
        {20,    9 ,    4 ,    4 ,    4,     4 ,    1 ,    3 ,    14,    14,    2 ,    2 ,    15,    15,    15,    15},   /*4 */ 
        {21,    5 ,    8 ,    6 ,    5,     0 ,    5 ,    5 ,    10,    10,    7 ,    7 ,    15,    15,    15,    15},   /*5 */ 
        {22,    6 ,    9 ,    6 ,    6,     1 ,    6 ,    5 ,    11,    11,    7 ,    7 ,    15,    15,    15,    15},   /*6 */ 
        {23,    7 ,    9 ,    9 ,    7,     2 ,    5 ,    5 ,    12,    12,    7 ,    7 ,    15,    15,    15,    15},   /*7 */ 
        {24,    8 ,    8 ,    9 ,    8,     3 ,    5 ,    8 ,    13,    13,    7 ,    7 ,    15,    15,    15,    15},   /*8 */ 
        {25,    9 ,    9 ,    9 ,    9,     4 ,    6 ,    8 ,    14,    14,    7 ,    7 ,    15,    15,    15,    15},   /*9 */ 
        {21,    21,    13,    11,    0,     0 ,    10,    10,    10,    10,    12,    12,    15,    15,    15,    15},   /*10*/ 
        {22,    22,    14,    11,    1,     1 ,    11,    10,    11,    11,    12,    12,    15,    15,    15,    15},   /*11*/ 
        {23,    23,    14,    14,    2,     2 ,    10,    10,    12,    12,    12,    12,    15,    15,    15,    15},   /*12*/ 
        {24,    24,    13,    14,    3,     3 ,    10,    13,    13,    13,    12,    12,    15,    15,    15,    15},   /*13*/ 
        {25,    25,    14,    14,    4,     4 ,    11,    13,    14,    14,    12,    12,    15,    15,    15,    15},   /*14*/ 
        {25,    25,    25,    25,    0,     0 ,    0 ,    0 ,    12,    12,    12,    12,    15,    15,    15,    15},   /*15*/ 
        {16,    21,    19,    17,    0,     16,    16,    16,    10,    10,    18,    18,    15,    15,    15,    15},   /*16*/ 
        {17,    22,    20,    17,    1,     17,    17,    16,    11,    11,    18,    18,    15,    15,    15,    15},   /*17*/ 
        {18,    23,    20,    20,    2,     18,    16,    16,    12,    12,    18,    18,    15,    15,    15,    15},   /*18*/ 
        {19,    24,    19,    20,    3,     19,    16,    19,    13,    13,    18,    18,    15,    15,    15,    15},   /*19*/ 
        {20,    25,    20,    20,    4,     20,    17,    19,    14,    14,    18,    18,    15,    15,    15,    15},   /*20*/ 
        {21,    21,    24,    22,    5,     16,    21,    21,    10,    10,    23,    23,    15,    15,    15,    15},   /*21*/ 
        {22,    22,    25,    22,    6,     17,    22,    21,    11,    11,    23,    23,    15,    15,    15,    15},   /*22*/ 
        {23,    23,    25,    25,    7,     18,    21,    21,    12,    12,    23,    23,    15,    15,    15,    15},   /*23*/ 
        {24,    24,    24,    25,    8,     19,    21,    24,    13,    13,    23,    23,    15,    15,    15,    15},   /*24*/ 
        {25,    25,    25,    25,    9,     20,    22,    24,    14,    14,    23,    23,    15,    15,    15,    15},   /*25*/ 
    };
    uint8 quad_mode[4] = {0};
    uint8 quad_lane_base;
    uint8 quad_lane_idx;
    uint8 dst_serdes_num;
    uint8 action;   /*_tmm_dyn_switch_quad_action_t*/
    uint8 comb_idx;
    uint8 find_flag;
    uint8 comb_num = 26;
    uint8 act_num = 16;
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    /*get src quad lane num*/
    quad_lane_base = lane_id/4*4;
    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    SYS_CONDITION_RETURN((NULL == p_hss_vec), CTC_E_INVALID_PTR);
    for(quad_lane_idx = 0; quad_lane_idx < 4; quad_lane_idx++)
    {
        quad_mode[quad_lane_idx] = p_hss_vec->serdes_info[quad_lane_base+quad_lane_idx].mode;
        if(CTC_CHIP_SERDES_NONE_MODE == quad_mode[quad_lane_idx])
        {
            src_quad_comb[quad_lane_idx] = 0;
        }
        else
        {
            SYS_TMM_GET_LANE_NUM_BY_MODE(quad_mode[quad_lane_idx], src_quad_comb[quad_lane_idx]);
        }
    }

    /*get dst quad lane num*/
    /*calculate switch action*/
    if(CTC_CHIP_SERDES_NONE_MODE == dst_mode)
    {
        dst_serdes_num = 0;
    }
    else
    {
        SYS_TMM_GET_LANE_NUM_BY_MODE(dst_mode, dst_serdes_num);
    }
    action = ((4 == dst_serdes_num) ? 3 : dst_serdes_num)*4 + lane_id%4;

    /*find src quad combination*/
    for(comb_idx = 0; comb_idx < comb_num; comb_idx++)
    {
        find_flag = TRUE;
        for(quad_lane_idx = 0; quad_lane_idx < 4; quad_lane_idx++)
        {
             if(src_quad_comb[quad_lane_idx] != quad_mode_comb_dict[comb_idx][quad_lane_idx])
             {
                 find_flag = FALSE;
                 break;
             }
        }
        if(TRUE == find_flag)
        {
            break;
        }
    }

    /*get dst quad combination*/
    SYS_CONDITION_RETURN(((comb_num <= comb_idx) || (act_num <= action)), CTC_E_INVALID_PARAM);
    for(quad_lane_idx = 0; quad_lane_idx < 4; quad_lane_idx++)
    {
        dst_quad_comb[quad_lane_idx] = quad_mode_comb_dict[switch_result[comb_idx][action]][quad_lane_idx];
    }

    /*50GR2 -> 50GR1, lane 1 & 3 drop*/
    if((CTC_CHIP_SERDES_LG_R1_MODE == dst_mode) && (SYS_DATAPATH_HSS_TYPE_15G == p_hss_vec->hss_type))
    {
        if(((2 == src_quad_comb[0]) && (2 == src_quad_comb[1])) && ((1 == dst_quad_comb[0]) && (1 == dst_quad_comb[1])))
        {
            dst_quad_comb[1] = 0;
        }
        if(((2 == src_quad_comb[2]) && (2 == src_quad_comb[3])) && ((1 == dst_quad_comb[2]) && (1 == dst_quad_comb[3])))
        {
            dst_quad_comb[3] = 0;
        }
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_datapath_dynamic_switch_get_info(uint8 lchip, uint8 logic_serdes_id, uint8 src_mode, uint8 dst_mode, 
                                          sys_tmm_ds_target_attr_t *target, uint16 overclocking_speed)
{
    uint8 hss_id;
    uint8 lane_id;
    uint8 src_quad_comb[4] = {0};
    uint8 dst_quad_comb[4] = {0};

    /*info collection*/
    hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logic_serdes_id);
    lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_id);
    /*400G special operation*/
    if((CTC_CHIP_SERDES_CDG_R8_MODE == src_mode) || (CTC_CHIP_SERDES_CDG_R8_MODE == dst_mode))
    {
        sys_tmm_mac_ds_add_serdes_lport_to_target_cdg(lchip, logic_serdes_id, dst_mode, target, overclocking_speed);
        return CTC_E_NONE;
    }

    /*get src & dst quad lane number*/
    CTC_ERROR_RETURN(_sys_tmm_mac_ds_get_quad_lane_num(lchip, hss_id, lane_id, dst_mode, src_quad_comb, dst_quad_comb));
    
    /*parser influenced serdes & port*/
    sys_tmm_mac_ds_add_serdes_lport_to_target(lchip, src_quad_comb, dst_quad_comb, logic_serdes_id, dst_mode, target, overclocking_speed);

    /*check speed sum after ds (not really change tables)*/
    CTC_ERROR_RETURN(sys_tmm_mac_dynamic_switch_glb_info_check(lchip, hss_id, lane_id, target));

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_dynamic_switch_prop_clear(uint8 lchip, sys_tmm_ds_target_attr_t *p_ds_attr)
{
    uint32 i;
    uint8  gchip      = 0;
    uint16 tmp_lport  = 0;
    uint8  mode       = 0;
    uint32 cl37_en    = 0;
    ctc_chip_serdes_loopback_t lb_param = {0};
    sys_datapath_lport_attr_t* port_attr_tmp = NULL;

    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));

    /* clear serdes-based property */
    for (i = 0; i < p_ds_attr->serdes_num; i++)
    {
        /* disable serdes loopback */
        CTC_ERROR_RETURN(_sys_usw_datapath_get_physical_serdes_id_by_logical(lchip, 
            p_ds_attr->serdes_list[i].logic_serdes_id, ((uint8*) &(lb_param.serdes_id))));
        for(mode = 0; mode < 2; mode++)
        {
            lb_param.mode = mode;
            CTC_ERROR_RETURN(_sys_tmm_datapath_get_serdes_loopback(lchip, &lb_param));
            if(lb_param.enable)
            {
                lb_param.enable = 0;
                CTC_ERROR_RETURN(_sys_tmm_datapath_set_serdes_loopback(lchip, &lb_param));
            }
        }
    }

    /* clear port-based property */
    for (i = 0; i < p_ds_attr->lport_num; i++)
    {
        SYS_CONDITION_CONTINUE(SYS_DS_LPORT_ADD == p_ds_attr->lport_list[i].upt_flag);

        tmp_lport = p_ds_attr->lport_list[i].lport;
        CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, tmp_lport, &port_attr_tmp));

        /* clear mac enable cfg */
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_en(lchip, tmp_lport, FALSE));

        /* set mac rx pkt disable */
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_rx_en(lchip, port_attr_tmp->mac_id, 0));


        /*disable cl73 AN*/
        if(TRUE != port_attr_tmp->an_done_opr)
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_cl73_auto_neg_en(lchip, tmp_lport, FALSE, FALSE));
        }

        if (SYS_DMPS_INACTIVE_NETWORK_PORT != port_attr_tmp->port_type)
        {
            /* clear unidir cfg */
            CTC_ERROR_RETURN(_sys_tmm_mac_set_unidir_en(lchip, tmp_lport, FALSE, TRUE));

            if(!SYS_TMM_IS_CPUMAC_PORT(port_attr_tmp->port_type))
            {
                /* recover ipg to default value */
                CTC_ERROR_RETURN(_sys_tmm_mac_set_ipg(lchip, tmp_lport, 12));
                /* recover preamble cfg to default value */
                CTC_ERROR_RETURN(_sys_tmm_mac_set_internal_property(lchip, tmp_lport, CTC_PORT_PROP_PREAMBLE, 8));
                /* recover padding cfg to default value */
                CTC_ERROR_RETURN(_sys_tmm_mac_set_internal_property(lchip, tmp_lport, CTC_PORT_PROP_PADING_EN, 1));

                CTC_ERROR_RETURN(_sys_tmm_mac_set_internal_property(lchip, tmp_lport, CTC_PORT_PROP_CHK_CRC_EN, 1));
                CTC_ERROR_RETURN(_sys_tmm_mac_set_internal_property(lchip, tmp_lport, CTC_PORT_PROP_STRIP_CRC_EN, 1));
                CTC_ERROR_RETURN(_sys_tmm_mac_set_internal_property(lchip, tmp_lport, CTC_PORT_PROP_APPEND_CRC_EN, 1));
            }
            else
            {
                /* recover ipg to default value */
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_ipg(lchip, tmp_lport, 12));
                if((CTC_CHIP_SERDES_SGMII_MODE == port_attr_tmp->pcs_mode) || 
                     (CTC_CHIP_SERDES_XFI_MODE == port_attr_tmp->pcs_mode) ||
                        (CTC_CHIP_SERDES_XXVG_MODE == port_attr_tmp->pcs_mode))
                {
                    /* recover preamble cfg to default value */
                    CTC_ERROR_RETURN(_sys_tmm_cpumac_set_internal_property(lchip, tmp_lport, CTC_PORT_PROP_PREAMBLE, 8));
                }
                /* recover padding cfg to default value */
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_internal_property(lchip, tmp_lport, CTC_PORT_PROP_PADING_EN, 1));
                
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_internal_property(lchip, tmp_lport, CTC_PORT_PROP_CHK_CRC_EN, 1));
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_internal_property(lchip, tmp_lport, CTC_PORT_PROP_STRIP_CRC_EN, 1));
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_internal_property(lchip, tmp_lport, CTC_PORT_PROP_APPEND_CRC_EN, 1));
            }

            /* clear parallel detect configure, when cl37 auto-nego is enable */
            if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr_tmp->pcs_mode) || 
                    (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr_tmp->pcs_mode) ||
                         (CTC_CHIP_SERDES_QSGMII_MODE == port_attr_tmp->pcs_mode))
            {
                CTC_ERROR_RETURN(_sys_tmm_mac_get_cl37_en(lchip, tmp_lport, &cl37_en));
                if(cl37_en)
                {
                    switch(port_attr_tmp->pcs_mode)
                    {
                        case CTC_CHIP_SERDES_QSGMII_MODE:
                            CTC_ERROR_RETURN(_sys_tmm_mac_qsgmii_set_parallel_detect_en(lchip, tmp_lport, FALSE));
                            break;
                        default:
                            CTC_ERROR_RETURN(_sys_tmm_mac_sgmii_set_parallel_detect_en(lchip, tmp_lport, FALSE));
                            break;
                    }
                }
            }
        }
        
        /* clear FEC if enable */
        if(SYS_TMM_MODE_IS_PAM4(port_attr_tmp->pcs_mode))
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_fec_en(lchip, tmp_lport, port_attr_tmp->pcs_mode, CTC_PORT_FEC_TYPE_RS544));
            _sys_tmm_mac_low_corepll_fec_free(lchip, port_attr_tmp);
        }
        else
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_fec_en(lchip, tmp_lport, port_attr_tmp->pcs_mode, CTC_PORT_FEC_TYPE_NONE));
        }

        /* CL37 AN status set to enable (default) */
        CTC_ERROR_RETURN(_sys_tmm_mac_set_cl37_auto_neg_en(lchip, tmp_lport, TRUE));
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_queue_get_port_depth(uint8 lchip, uint32 gport, uint32* p_depth)
{
#ifdef EMULATION_ENV
    uint32 cmd = 0;
    uint32 entry_id = 0;
#endif
    uint32 field_val = 0;
    uint32 chan_id = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    CTC_PTR_VALID_CHECK(p_depth);

    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
#ifdef EMULATION_ENV
    entry_id = DRV_INS(0, chan_id);
#endif
    
    if (SYS_COMMON_USELESS_CHANNEL == chan_id)
    {
        return CTC_E_INVALID_PORT;
    }
#ifdef EMULATION_ENV
    cmd = DRV_IOR(QMgrShellDestPortInfo_t, QMgrShellDestPortInfo_msgCnt_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, entry_id, cmd, &field_val));
#endif
    *p_depth = field_val;

    return CTC_E_NONE;
}

int32
_sys_tmm_datapath_check_queue_flush_clear(uint8 lchip, uint32 tmp_gport, sys_qos_shape_profile_t* shp_profile)
{
    uint8  cnt   = 0;
    uint32 depth = 0;

#ifdef PCS_IMG
    /*EMULATION pcs img version*/
    CTC_ERROR_RETURN(_sys_tmm_queue_get_port_depth(lchip, tmp_gport, &depth));
    while(depth)
    {
        sal_task_sleep(1000);
        if((cnt++) > 50)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%% Cannot flush queue depth(%d) to Zero, port %d \n", depth, tmp_gport);
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [DATAPATH] dynamic switch fail \n");
            return CTC_E_HW_FAIL;
        }
        CTC_ERROR_RETURN(_sys_tmm_queue_get_port_depth(lchip, tmp_gport, &depth));
    }
#else
    /*Board or UML or EMULATION datapath img version*/
    CTC_ERROR_RETURN(sys_usw_queue_get_port_depth(lchip, tmp_gport, &depth));
    while(depth)
    {
#ifdef EMULATION_ENV
        sal_task_sleep(1000);
#else
        sal_task_sleep(20);
#endif
        if((cnt++) > 50)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%% Cannot flush queue depth(%d) to Zero, port %d \n", depth, tmp_gport);
            CTC_ERROR_RETURN(sys_usw_queue_set_port_drop_en(lchip, tmp_gport, FALSE, shp_profile));
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [DATAPATH] dynamic switch fail \n");
            return CTC_E_HW_FAIL;
        }
        CTC_ERROR_RETURN(sys_usw_queue_get_port_depth(lchip, tmp_gport, &depth));
    }
#endif
    return CTC_E_NONE;
}

int32
_sys_tmm_check_datapath_credit_clear(uint8 lchip, uint32 mac_id, uint32 chan_id)
{
    uint32 cmd    = 0;
    uint32 index  = 0;
    uint32 credit = 0;
    uint32 cnt    = 0;
    uint32 tbl_id = 0;
    uint32 step   = NetTxCreditUsed1_t - NetTxCreditUsed0_t;
    uint8  dp_id       = 0;
    uint8  dp_chan_id  = 0;
    uint8  dp_txqm_id  = 0;
    uint8  txqm_mac_id =  0;

    dp_id       = SYS_TMM_GET_DP_ID_FROM_CHANID(chan_id);
    dp_chan_id  = SYS_TMM_GET_CHANN_PER_DP(chan_id);
    dp_txqm_id  = SYS_TMM_GET_TXQM_PER_DP(SYS_TMM_GET_TXQM_BY_MACID(mac_id));
    txqm_mac_id = TXQM_INNER_MAC_ID(mac_id);

    /* 1. check BufRetrvDPSopCreditMem.credit*/
    credit = 0;
    cnt    = 0;
    index  = DRV_INS(dp_id, dp_chan_id);
    cmd    = DRV_IOR(BufRetrvDPSopCreditMem_t, BufRetrvDPSopCreditMem_credit_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &credit));
    while(credit)
    {
#ifdef EMULATION_ENV
        sal_task_sleep(1000);
#else
        sal_task_sleep(20);
#endif
        if((cnt++) > 50)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " BufRetrvDPSopCreditMem_credit (chan: %d) cannot return to Zero \n", 
                chan_id);
            return CTC_E_HW_FAIL;
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &credit));
    }

    /* 2. BufRetrvDPBodyCreditMem.credit*/
    credit = 0;
    cnt    = 0;
    index  = DRV_INS(dp_id, dp_chan_id);
    cmd    = DRV_IOR(BufRetrvDPBodyCreditMem_t, BufRetrvDPBodyCreditMem_credit_f);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &credit));
    while(credit)
    {
#ifdef EMULATION_ENV
        sal_task_sleep(1000);
#else
        sal_task_sleep(20);
#endif
        if((cnt++) > 50)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " BufRetrvDPBodyCreditMem_credit (chan: %d) cannot return to Zero \n", 
                chan_id);
            return CTC_E_HW_FAIL;
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &credit));
    }

    SYS_CONDITION_RETURN(SYS_TMM_TXQM_NUM_PER_DP <= dp_txqm_id, CTC_E_NONE);

    /* 3. check NetTxCreditUsed0.creditUsed*/
    if(320 > mac_id)
    {
        credit = 0;
        cnt    = 0;
        tbl_id = NetTxCreditUsed0_t + step * dp_txqm_id;
        index = DRV_INS(dp_id, txqm_mac_id);
        cmd = DRV_IOR(tbl_id, NetTxCreditUsed0_creditUsed_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &credit));
        while(credit)
        {
#ifdef EMULATION_ENV
            sal_task_sleep(1000);
#else
            sal_task_sleep(20);
#endif
            if((cnt++) >50)
            {
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "NetTxCreditUsed%d_creditUsed cannot return to Zero, dp %u, txqm mac id %u \n", 
                    dp_txqm_id, dp_id, txqm_mac_id);
                return CTC_E_HW_FAIL;
            }
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &credit));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_datapath_check_credit_flush_clear(uint8 lchip, uint16 lport)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));

    CTC_ERROR_RETURN(_sys_tmm_check_datapath_credit_clear(lchip, port_attr->mac_id, port_attr->chan_id));

    return CTC_E_NONE;
}

int32
_sys_tmm_dynamic_switch_q_flush(uint8 lchip, sys_tmm_ds_target_attr_t *p_ds_attr)
{
    uint32 i = 0;
    uint16 tmp_lport = 0;
    uint32 tmp_gport = 0;
    uint8  gchip = 0;
    sys_qos_shape_profile_t shp_profile[SYS_DATAPATH_DS_MAX_PORT_NUM] = {{0}};
#ifdef PCS_IMG
    uint32 cmd = 0;
    uint32 data[8] = {0};  // 256 bit
    sys_datapath_lport_attr_t* port_attr = NULL;
#endif
    
    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));    

    /* clear port-based property */
    for (i = 0; i < p_ds_attr->lport_num; i++)
    {
        if(SYS_DS_LPORT_ADD == p_ds_attr->lport_list[i].upt_flag)
        {
            /* if pbs is 0, set default value */
            shp_profile[i].chan_shp_tokenThrd      = 0xbf;
            shp_profile[i].chan_shp_tokenThrdShift = 0xa;
        }
        else
        {
            tmp_lport = p_ds_attr->lport_list[i].lport;
            tmp_gport = CTC_MAP_LPORT_TO_GPORT((uint32)gchip, (uint32)tmp_lport);

#ifdef PCS_IMG
            CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, tmp_lport, &port_attr));
            cmd = DRV_IOR(QMgrShellChanWrEnCtl_t, QMgrShellChanWrEnCtl_chanWrEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, data));
            CTC_BMP_UNSET(data, port_attr->chan_id);
            cmd = DRV_IOW(QMgrShellChanWrEnCtl_t, QMgrShellChanWrEnCtl_chanWrEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, data));
#else
            /*for restore shape profile*/
            CTC_ERROR_RETURN(sys_usw_queue_get_profile_from_hw(lchip, tmp_gport, &shp_profile[i]));
            /*enqdrop*/
            CTC_ERROR_RETURN(sys_usw_queue_set_port_drop_en(lchip, tmp_gport, TRUE, &shp_profile[i]));
#endif
            /*check queue flush clear*/
            CTC_ERROR_RETURN(_sys_tmm_datapath_check_queue_flush_clear(lchip, tmp_gport, &shp_profile[i]));
            /*check other credit clear*/
            CTC_ERROR_RETURN(_sys_tmm_datapath_check_credit_flush_clear(lchip, tmp_lport));
        }

        sal_memcpy(&(p_ds_attr->shp_profile[i]), &shp_profile[i], sizeof(sys_qos_shape_profile_t));
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_dynamic_switch_serdes_cfg(uint8 lchip, uint8 phy_serdes_id, uint8 logic_serdes_id, uint8 src_mode, uint8 dst_mode, uint8 ovclk_flag)
{
    uint8                       ovclk_speed_new = ovclk_flag;
    ctc_chip_serdes_ffe_t            serdes_ffe = {0};
    sys_tmm_serdes_fw_config_param_t fw_cfg     = {0};
    sys_datapath_serdes_info_t*      p_serdes   = NULL;

    CTC_ERROR_RETURN(sys_usw_datapath_get_serdes_info(lchip, logic_serdes_id, &p_serdes));

    serdes_ffe.serdes_id = phy_serdes_id;
    serdes_ffe.mode = CTC_CHIP_SERDES_FFE_MODE_DEFINE;

    //parameter check    
    if ((SYS_TMM_MAX_SERDES_NUM + SYS_TMM_CPUMAC_SERDES_NUM) < phy_serdes_id)
    {
        return CTC_E_INVALID_PARAM;
    }

    if(SYS_TMM_IS_SERDES_ABANDON(p_serdes->mode, p_serdes->is_dyn))
    {
        return CTC_E_INVALID_CONFIG;
    }

    /*!NONE --> NONE*/
    if((CTC_CHIP_SERDES_NONE_MODE != src_mode) && (CTC_CHIP_SERDES_NONE_MODE == dst_mode))
    {
        CTC_ERROR_RETURN(_sys_tmm_serdes_fw_deconfig(lchip, phy_serdes_id));
        CTC_ERROR_RETURN(sys_tmm_serdes_set_power_en(lchip, phy_serdes_id, FALSE));
        return CTC_E_NONE;
    }
    /*NONE --> !NONE*/
    else if((CTC_CHIP_SERDES_NONE_MODE == src_mode) && (CTC_CHIP_SERDES_NONE_MODE != dst_mode))
    {
        CTC_ERROR_RETURN(sys_tmm_serdes_set_power_en(lchip, phy_serdes_id, TRUE));
    }

    /*save 28G FFE manual value before reconfig*/
    CTC_ERROR_RETURN(sys_tmm_datapath_get_serdes_ffe(lchip, &serdes_ffe));

    /*firmware configure*/
    fw_cfg.serdes_id    = phy_serdes_id;
    fw_cfg.data_rate    = dst_mode;
    fw_cfg.ovclk_speed  = ovclk_speed_new; 
    fw_cfg.tx_idx       = 4;
    fw_cfg.optical_mode = p_serdes->optical_mode;

    CTC_ERROR_RETURN(_sys_tmm_serdes_fw_deconfig(lchip, fw_cfg.serdes_id));
    CTC_ERROR_RETURN(_sys_tmm_serdes_fw_config(lchip, &fw_cfg));
    
    /*recover 28G FFE manual value after reconfig */
    CTC_ERROR_RETURN(sys_tmm_datapath_set_serdes_ffe(lchip, &serdes_ffe));

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_dynamic_switch_serdes(uint8 lchip,           sys_tmm_ds_target_attr_t *p_ds_attr)
{
#ifndef EMULATION_ENV
    uint8 index = 0;
    uint8 physic_serdes_id = 0;
    uint8 src_mode = 0;
    uint8 dst_mode = 0;
    uint8 ovclk_flag = 0;
    uint16 tmp_lport  = 0;
    uint32 i = 0;
    sys_datapath_lport_attr_t* port_attr_tmp = NULL;

    for (i = 0; i < p_ds_attr->lport_num; i++)
    {
        SYS_CONDITION_CONTINUE(SYS_DS_LPORT_ADD == p_ds_attr->lport_list[i].upt_flag);

        tmp_lport = p_ds_attr->lport_list[i].lport;
        CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, tmp_lport, &port_attr_tmp));

        if(TRUE == port_attr_tmp->an_done_opr)
        {
            return CTC_E_NONE;
        }
    }

    for(index = 0; index < p_ds_attr->serdes_num; index ++)
    {
        _sys_usw_datapath_get_physical_serdes_id_by_logical(lchip, p_ds_attr->serdes_list[index].logic_serdes_id, 
            &physic_serdes_id);
        SYS_CONDITION_CONTINUE(SYS_TMM_USELESS_ID8 == physic_serdes_id);
        src_mode = p_ds_attr->serdes_list[index].src_mode;
        dst_mode = p_ds_attr->serdes_list[index].dst_mode;

        if (SYS_TMM_MODE_IS_PAM4(dst_mode))
        {
             ovclk_flag = (p_ds_attr->serdes_list[index].ovclk_flag) ? p_ds_attr->serdes_list[index].ovclk_flag : CTC_CHIP_SERDES_OCS_MODE_51_56G;
        }
        else
        {
            ovclk_flag = p_ds_attr->serdes_list[index].ovclk_flag;
        }
        
        CTC_ERROR_RETURN(_sys_tmm_dynamic_switch_serdes_cfg(lchip, physic_serdes_id, p_ds_attr->serdes_list[index].logic_serdes_id, src_mode, dst_mode, ovclk_flag));
    }
#endif
    
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_mac_none_config(uint8 lchip, sys_tmm_ds_target_attr_t *p_ds_attr)
{
    uint8  serdes_idx          = 0;
    uint8  logic_serdes_id     = 0;
    uint8  physic_serdes_id     = 0;
    uint16 mac_id              = 0;
    uint8  txqm_id             = 0;
    uint8  is_x16              = 0;
    uint8  x8_x16_idx          = 0;
    uint8  inner_lane          = 0;
    uint8  inner_lane_logic    = 0;
    uint8  mac_lane            = 0;
    uint8  hss_id              = 0;
    uint32 tbl_id              = 0;
    uint32 fld_id              = 0;
    uint32 value               = 0;
    uint32 index               = 0;
    uint32 cmd                 = 0;
    McPcsX8LanesRxPhyLaneCfg_m pcs_rx_cfg;
    McMacTxChanIdLaneCfg_m     mac_tx_cfg;
    uint32 pcs_tx_map[16]      = {0};
    McPcsX8LanesRxLaneCfg_m    pcs_rx_lane;

    SYS_CONDITION_RETURN((NULL == p_ds_attr), CTC_E_INVALID_PTR);

    for(serdes_idx = 0; serdes_idx < p_ds_attr->serdes_num; serdes_idx++)
    {
        SYS_CONDITION_CONTINUE(!SYS_TMM_IS_MODE_NONE(p_ds_attr->serdes_list[serdes_idx].dst_mode));

        logic_serdes_id  = p_ds_attr->serdes_list[serdes_idx].logic_serdes_id;
        SYS_CONDITION_CONTINUE(SYS_TMM_CPUMAC_SERDES_START_ID <= logic_serdes_id);
        SYS_CONDITION_CONTINUE(CTC_E_NONE != _sys_usw_datapath_get_physical_serdes_id_by_logical(lchip, logic_serdes_id, &physic_serdes_id));
        mac_id           = g_lane_2_pcs_mac_map[logic_serdes_id].mac_id;
        txqm_id          = SYS_TMM_GET_TXQM_BY_MACID(mac_id);
        is_x16           = SYS_TMM_IS_PCS_X16(txqm_id);
        SYS_TMM_GET_PCSXIDX(txqm_id, x8_x16_idx);
        inner_lane       = physic_serdes_id % SYS_TMM_LANE_NUM_PER_HSS;
        inner_lane_logic = logic_serdes_id % SYS_TMM_LANE_NUM_PER_HSS;
        hss_id           = logic_serdes_id / SYS_TMM_LANE_NUM_PER_HSS;
        mac_lane         = physic_serdes_id % (is_x16 ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM);

        /*set McPcsX16LanesRxBPhyLaneCfg.cfgRxPhyLane_5_cfgRxChanId to 0x1f*/
        if(is_x16)
        {
            if(SYS_TMM_JUDGE_PCSX16A(hss_id))
            {
                tbl_id = McPcsX16LanesRxAPhyLaneCfg_t;
                fld_id = McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f + inner_lane * 
                         (McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_1_cfgRxChanId_f - 
                         McPcsX16LanesRxAPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f);
            }
            else
            {
                tbl_id = McPcsX16LanesRxBPhyLaneCfg_t;
                fld_id = McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f + inner_lane * 
                         (McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_1_cfgRxChanId_f - 
                         McPcsX16LanesRxBPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f);
            }
        }
        else
        {
            tbl_id = McPcsX8LanesRxPhyLaneCfg_t;
            fld_id = McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f + inner_lane * 
                     (McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_1_cfgRxChanId_f - 
                     McPcsX8LanesRxPhyLaneCfg_cfgRxPhyLane_0_cfgRxChanId_f);
        }

        index = DRV_INS(x8_x16_idx, 0);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_rx_cfg));
        value = 0x1f;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &pcs_rx_cfg);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_rx_cfg));

        /*set McPcsX16LanesTxLaneMapCfg.cfgTxLaneMapLane_0_cfgTxChanId to 0x1f*/
        if(is_x16)
        {
            tbl_id = McPcsX16LanesTxLaneMapCfg_t;
            fld_id = McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f + mac_lane * 
                     (McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxChanId_f - 
                     McPcsX16LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f);
        }
        else
        {
            tbl_id = McPcsX8LanesTxLaneMapCfg_t;
            fld_id = McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f + mac_lane * 
                     (McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_1_cfgTxChanId_f - 
                     McPcsX8LanesTxLaneMapCfg_cfgTxLaneMapLane_0_cfgTxChanId_f);
        }

        index = DRV_INS(x8_x16_idx, 0);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_tx_map));
        value = 0x1f;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &pcs_tx_map);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_tx_map));

        /*set McMacTxChanIdLaneCfg.cfgTxChanIdLane_n_cfgTxChanIdLane to 0x3f*/
        tbl_id = McMacTxChanIdLaneCfg_t;
        fld_id = McMacTxChanIdLaneCfg_cfgTxChanIdLane_0_cfgTxChanIdLane_f + mac_lane * 
                 (McMacTxChanIdLaneCfg_cfgTxChanIdLane_1_cfgTxChanIdLane_f - 
                 McMacTxChanIdLaneCfg_cfgTxChanIdLane_0_cfgTxChanIdLane_f);
        index = DRV_INS(txqm_id, 0);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));
        value = 0x3f;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mac_tx_cfg);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_tx_cfg));

        /*set McPcsX8LanesRxLaneCfg.cfgRxLane_0_cfgRxSpeed to 0xf*/
        if(is_x16)
        {
            if(SYS_TMM_JUDGE_PCSX16A(hss_id))
            {
                tbl_id = McPcsX16LanesRxALaneCfg_t;
                fld_id = McPcsX16LanesRxALaneCfg_cfgRxLane_0_cfgRxSpeed_f + inner_lane_logic * 
                         (McPcsX16LanesRxALaneCfg_cfgRxLane_1_cfgRxSpeed_f - 
                         McPcsX16LanesRxALaneCfg_cfgRxLane_0_cfgRxSpeed_f);
            }
            else
            {
                tbl_id = McPcsX16LanesRxBLaneCfg_t;
                fld_id = McPcsX16LanesRxBLaneCfg_cfgRxLane_0_cfgRxSpeed_f + inner_lane_logic * 
                         (McPcsX16LanesRxBLaneCfg_cfgRxLane_1_cfgRxSpeed_f - 
                         McPcsX16LanesRxBLaneCfg_cfgRxLane_0_cfgRxSpeed_f);
            }
        }
        else
        {
            tbl_id = McPcsX8LanesRxLaneCfg_t;
            fld_id = McPcsX8LanesRxLaneCfg_cfgRxLane_0_cfgRxSpeed_f + inner_lane_logic * 
                     (McPcsX8LanesRxLaneCfg_cfgRxLane_1_cfgRxSpeed_f - 
                     McPcsX8LanesRxLaneCfg_cfgRxLane_0_cfgRxSpeed_f);
        }

        index = DRV_INS(x8_x16_idx, 0);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_rx_lane));
        value = 0x0f;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &pcs_rx_lane);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_rx_lane));

        /*clear McHataTxChanMap_chanMap_f to 0x3f*/
        tbl_id = physic_serdes_id % (is_x16 ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM);
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tbl_id, McHataTxChanMap_chanMap_f, 0x3f));
        /*clear McHataTxChanMap_rxChanMap_f to 0x3f*/
        tbl_id = logic_serdes_id % (is_x16 ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM);
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tbl_id, McHataTxChanMap_rxChanMap_f, 0x3f));
        tbl_id = physic_serdes_id % (is_x16 ? SYS_TMM_PCS_X16_LANE_NUM : SYS_TMM_PCS_X8_LANE_NUM) + 16;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_map(lchip, txqm_id, tbl_id, McHataTxChanMap_rxChanMap_f, 0x3f));
        /*clear McHataTxPortMap_portMap_f to 0x3f*/
        tbl_id = TXQM_INNER_MAC_ID(mac_id);
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_tx_port_map(lchip, txqm_id, tbl_id, 0x3f));
    }

    return CTC_E_NONE;
}

/*if others<->LG, reset port QuadSgmacCfg.cfgSgmac[0..3]TxBufRst*/
int32
_sys_tmm_dynamic_switch_cpumac_tx_buf_rst(uint8 lchip, sys_tmm_ds_target_attr_t *p_ds_attr)
{
    uint8  idx;
    uint8  lg_idx         = 0;
    uint8  is_cpumac      = FALSE;
    uint8  rst_lg_flag[2] = {FALSE, FALSE};
    uint32 step           = 0;
    uint32 tbl_id         = 0;
    uint32 fld_id         = 0;
    uint32 cmd            = 0;
    uint32 value          = 0;
    uint32 value_bmp      = 0;
    QuadSgmacCfg_m        mac_cfg;
    QuadSgmacReserved_m   mac_rsv;
    sys_datapath_lport_attr_t* port_attr = NULL;

    for(idx = 0; idx < p_ds_attr->lport_num; idx++)
    {
        SYS_CONDITION_CONTINUE(SYS_DS_LPORT_DROP == p_ds_attr->lport_list[idx].upt_flag);
        SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_tmm_datapath_get_port_attr(lchip, p_ds_attr->lport_list[idx].lport, &port_attr));
        if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
        {
            is_cpumac = TRUE;
            break;
        }
    }
    SYS_CONDITION_RETURN((!is_cpumac), CTC_E_NONE);

    for(idx = 0; idx < p_ds_attr->serdes_num; idx++)
    {
        if((CTC_CHIP_SERDES_LG_MODE == p_ds_attr->serdes_list[idx].dst_mode) || 
           (CTC_CHIP_SERDES_LG_MODE == p_ds_attr->serdes_list[idx].src_mode))
        {
            lg_idx = (p_ds_attr->serdes_list[idx].logic_serdes_id - SYS_TMM_CPUMAC_SERDES_START_ID) / 2;
            rst_lg_flag[lg_idx] = TRUE;
        }
    }
    SYS_CONDITION_RETURN(((FALSE == rst_lg_flag[0]) && (FALSE == rst_lg_flag[1])), CTC_E_NONE);

    /*QuadSgmacCfg_cfgSgmac0TxBufRst_f set 1*/
    tbl_id = QuadSgmacCfg_t;
    step = QuadSgmacCfg_cfgSgmac1TxBufRst_f - QuadSgmacCfg_cfgSgmac0TxBufRst_f;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));
    value = 1;
    for(lg_idx = 0; lg_idx < 2; lg_idx++)
    {
        SYS_CONDITION_CONTINUE(FALSE == rst_lg_flag[lg_idx]);
        fld_id = QuadSgmacCfg_cfgSgmac0TxBufRst_f + step*(lg_idx*2);
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mac_cfg);
        fld_id = QuadSgmacCfg_cfgSgmac0TxBufRst_f + step*(lg_idx*2 + 1);
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mac_cfg);
    }
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));

    /*QuadSgmacReserved_reserved_f set 1*/
    cmd = DRV_IOR(QuadSgmacReserved_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rsv));
    for(lg_idx = 0; lg_idx < 2; lg_idx++)
    {
        SYS_CONDITION_CONTINUE(FALSE == rst_lg_flag[lg_idx]);
        value_bmp = (0x00000001 << (lg_idx*2)) | (0x00000001 << (lg_idx*2+1));
        DRV_IOW_FIELD(lchip, QuadSgmacReserved_t, QuadSgmacReserved_reserved_f, &value_bmp, &mac_rsv);
    }
    cmd = DRV_IOW(QuadSgmacReserved_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rsv));

    /*QuadSgmacCfg_cfgSgmac0TxBufRst_f set 0*/
    value = 0;
    for(lg_idx = 0; lg_idx < 2; lg_idx++)
    {
        SYS_CONDITION_CONTINUE(FALSE == rst_lg_flag[lg_idx]);
        fld_id = QuadSgmacCfg_cfgSgmac0TxBufRst_f + step*(lg_idx*2);
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mac_cfg);
        fld_id = QuadSgmacCfg_cfgSgmac0TxBufRst_f + step*(lg_idx*2 + 1);
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mac_cfg);
    }
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));

    /*QuadSgmacReserved_reserved_f set 0*/
    cmd = DRV_IOR(QuadSgmacReserved_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rsv));
    value_bmp = 0;
    DRV_IOW_FIELD(lchip, QuadSgmacReserved_t, QuadSgmacReserved_reserved_f, &value_bmp, &mac_rsv);
    cmd = DRV_IOW(QuadSgmacReserved_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rsv));

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_dynamic_switch_macpcs(uint8 lchip, uint8 dst_mode, sys_tmm_ds_target_attr_t *p_ds_attr)
{
    uint8 index                          = 0;
    uint8 inner_lane_id                  = 0;
    uint32 i                             = 0;
    uint16 tmp_lport                     = 0;
    ctc_port_fec_type_t default_fec_type = CTC_PORT_FEC_TYPE_NONE;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_none_config(lchip, p_ds_attr));

    CTC_ERROR_RETURN(_sys_tmm_dynamic_switch_cpumac_tx_buf_rst(lchip, p_ds_attr));

    for (i = 0; i < p_ds_attr->lport_num; i++)
    {
        SYS_CONDITION_CONTINUE(SYS_DS_LPORT_DROP == p_ds_attr->lport_list[i].upt_flag);
        tmp_lport = p_ds_attr->lport_list[i].lport;

        default_fec_type = SYS_TMM_MODE_IS_PAM4(dst_mode) ? CTC_PORT_FEC_TYPE_RS544 : CTC_PORT_FEC_TYPE_NONE;

        SYS_CONDITION_CONTINUE(SYS_COMMON_USELESS_MAC == tmp_lport);

        CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, tmp_lport, &port_attr));
        SYS_CONDITION_CONTINUE(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num);
        if ((SYS_DMPS_NETWORK_PORT == port_attr->port_type) || (SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type))
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_config(lchip, tmp_lport, dst_mode, default_fec_type, port_attr->port_type, FALSE));
        }
        else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
        {
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_mac_config(lchip, tmp_lport, port_attr));

            for(index = 0; index < port_attr->serdes_num; index ++)
            {
                inner_lane_id = port_attr->multi_serdes_id[index] % 4;
                CTC_ERROR_RETURN(sys_tmm_datapath_serdes_clktree_cpumac_cfg(lchip, inner_lane_id, port_attr->pcs_mode));
            }
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_low_corepll_fec_remap(lchip, tmp_lport, port_attr));

        CTC_ERROR_RETURN(sys_usw_peri_set_dlb_chan_type(lchip, port_attr->chan_id));
    }

    CTC_ERROR_RETURN(_sys_tmm_cpumac_additional_cfg(lchip, FALSE, p_ds_attr));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_dynamic_switch_calendar_check(uint8 lchip, uint8 ds_or_xpipe, sys_tmm_ds_target_attr_t *p_ds_attr)
{
    uint8   hss_id                     = SYS_TMM_MAP_SERDES_TO_HSS_IDX(p_ds_attr->serdes_list[0].logic_serdes_id);
    uint8   txqm_id                    = 0;
    uint8   dp_id                      = SYS_TMM_GET_DP_ID_FROM_SERDES(p_ds_attr->serdes_list[0].logic_serdes_id);
    uint16* cal                        = NULL;
    uint16  walk_end                   = 0;
    int32   ret                        = CTC_E_NONE;
    sys_cal_info_collect_t* cal_info   = NULL;
    sys_datapath_lport_attr_t* port_attr_backup = NULL; /*[SYS_DATAPATH_MAX_LOCAL_SLICE_NUM][256]*/
    sys_datapath_hss_attribute_t* hss_backup = NULL;
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    cal = (uint16*)mem_malloc(MEM_DMPS_MODULE, SYS_TMM_MAX_CAL_LEN * sizeof(uint16));
    CTC_ERROR_GOTO((NULL == cal) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_1);
    sal_memset(cal, 0, SYS_TMM_MAX_CAL_LEN * sizeof(uint16));

    cal_info = (sys_cal_info_collect_t*)mem_malloc(MEM_DMPS_MODULE, 
        (SYS_TMM_MAX_MAC_NUM_PER_DP + (SYS_TMM_CPUMAC_SERDES_NUM / 2)) * sizeof(sys_cal_info_collect_t));
    CTC_ERROR_GOTO((NULL == cal_info) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_2);
    sal_memset(cal_info, 0, (SYS_TMM_MAX_MAC_NUM_PER_DP + (SYS_TMM_CPUMAC_SERDES_NUM / 2)) * sizeof(sys_cal_info_collect_t));

    /*serdes db backup*/
    hss_backup = (sys_datapath_hss_attribute_t*)mem_malloc(MEM_DMPS_MODULE, sizeof(sys_datapath_hss_attribute_t));
    CTC_ERROR_GOTO((NULL == hss_backup) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_3);
    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    SYS_CONDITION_RETURN((NULL == p_hss_vec), CTC_E_INVALID_PTR);
    sal_memcpy(hss_backup, p_hss_vec, sizeof(sys_datapath_hss_attribute_t));

    /*port db backup*/
    port_attr_backup = (sys_datapath_lport_attr_t*)mem_malloc(MEM_DMPS_MODULE, 256 * sizeof(sys_datapath_lport_attr_t));
    CTC_ERROR_GOTO((NULL == port_attr_backup) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_4);
    sal_memcpy(port_attr_backup, p_usw_datapath_master[lchip]->port_attr[0], 256 * sizeof(sys_datapath_lport_attr_t));

    /*soft table temp update*/
    if(SYS_CAL_CHECK_DS == ds_or_xpipe)
    {
        CTC_ERROR_GOTO(_sys_tmm_ds_soft_table_upt(lchip, p_ds_attr), ret, RELEASE_PTR_RETURN_5);
    }

    /*general calendar check*/
    CTC_ERROR_GOTO(sys_tmm_calendar_speed_info_collect(lchip, cal_info, dp_id, SYS_TMM_TXQM_NUM_PER_DP, SYS_TMM_GENERAL_CAL),
        ret, RELEASE_PTR_RETURN_5);
    CTC_ERROR_GOTO(_sys_tmm_datapath_calculate_general_calendar_parser(lchip, dp_id, TRUE, cal, &walk_end, cal_info), 
        ret, RELEASE_PTR_RETURN_5);

    /*mac calendar check*/
    SYS_TMM_GET_TXQM_ID_BY_HSS_ID(hss_id, txqm_id);
    sal_memset(cal, 0, SYS_TMM_MAX_CAL_LEN * sizeof(uint16));
    walk_end = 0;
    ret = _sys_tmm_mac_get_calendar(lchip, dp_id, SYS_TMM_GET_TXQM_PER_DP(txqm_id), cal, &walk_end, NULL, TRUE);
    if((CTC_E_NONE != ret) || (128 <= walk_end))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC calendar TX check error! dp_id %u, txqm_id %u\n", 
            dp_id, txqm_id);
        ret = CTC_E_NOT_SUPPORT;
        goto RELEASE_PTR_RETURN_5;
    }
    sal_memset(cal, 0, SYS_TMM_MAX_CAL_LEN * sizeof(uint16));
    walk_end = 0;
    ret = _sys_tmm_mac_get_calendar(lchip, dp_id, SYS_TMM_GET_TXQM_PER_DP(txqm_id), cal, &walk_end, NULL, FALSE);
    if((CTC_E_NONE != ret) || (128 <= walk_end))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% MAC calendar RX check error! dp_id %u, txqm_id %u\n", 
            dp_id, txqm_id);
        ret = CTC_E_NOT_SUPPORT;
        goto RELEASE_PTR_RETURN_5;
    }

RELEASE_PTR_RETURN_5:
    /*serdes db recovery*/
    sal_memcpy(p_hss_vec, hss_backup, sizeof(sys_datapath_hss_attribute_t));
    /*port db recovery*/
    sal_memcpy(p_usw_datapath_master[lchip]->port_attr[0], port_attr_backup, 256 * sizeof(sys_datapath_lport_attr_t));

    mem_free(port_attr_backup);
RELEASE_PTR_RETURN_4:
    mem_free(hss_backup);
RELEASE_PTR_RETURN_3:
    mem_free(cal_info);
RELEASE_PTR_RETURN_2:
    mem_free(cal);
RELEASE_PTR_RETURN_1:
    return ret;
}

int32
_sys_tmm_mac_set_interface_mode(uint8 lchip, uint8 dst_mode, sys_tmm_ds_target_attr_t *p_ds_attr)
{
    uint8  i         = 0;
    uint8  gchip     = 0;
    uint16 tmp_lport = 0;
    uint32 is_bind   = 0;
    sys_datapath_lport_attr_t* port_attr_tmp = NULL;
    sys_usw_port_mac_config_t port_mac_config = {0};
#ifdef PCS_IMG
    uint32 data[8]   = {0};  // 256 bit
    uint32 cmd       = 0;
    uint32 index     = 0;
#else
    uint32 tmp_gport = 0;
#endif
    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));

    CTC_ERROR_RETURN(_sys_tmm_mac_dynamic_switch_calendar_check(lchip, SYS_CAL_CHECK_DS, p_ds_attr));

    /*#1, param/status check*/
    /*CTC_ERROR_RETURN(_sys_tmm_dynamic_switch_param_check(lchip, lport, if_mode, p_ds_attr));*/

    /* check dst port whether bind in group */
    for (i = 0; i < p_ds_attr->lport_num; i++)
    {
        SYS_CONDITION_CONTINUE(SYS_DS_LPORT_REMAIN == p_ds_attr->lport_list[i].upt_flag);
        
        tmp_lport = p_ds_attr->lport_list[i].lport;
        CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, tmp_lport, &port_attr_tmp));
        
        CTC_ERROR_RETURN(sys_tmm_flexe_check_serdes_bind_group(lchip, port_attr_tmp->multi_serdes_id[0], &is_bind));
        if (is_bind)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% SerDes %d is bind to flexe group, cannot run dynamic switch ! \n", port_attr_tmp->multi_serdes_id[0]);
            return CTC_E_PARAM_CONFLICT;
        }
    }
        
    /*#2, mac/pcs property disable*/
    CTC_ERROR_RETURN(_sys_tmm_dynamic_switch_prop_clear(lchip, p_ds_attr));
    /*#3, flush queue*/
    CTC_ERROR_RETURN(_sys_tmm_dynamic_switch_q_flush(lchip, p_ds_attr));

    /*#4, rebuild soft mapping*/
    CTC_ERROR_RETURN(_sys_tmm_ds_soft_table_upt(lchip, p_ds_attr));

    /*#5, serdes switch*/
    CTC_ERROR_RETURN(_sys_tmm_dynamic_switch_serdes(lchip, p_ds_attr));
    /*#6, datapath switch*/
    CTC_ERROR_RETURN(_sys_tmm_dynamic_switch_datapath(lchip, p_ds_attr));
    /*#7, mac/pcs switch*/
    CTC_ERROR_RETURN(_sys_tmm_dynamic_switch_macpcs(lchip, dst_mode, p_ds_attr));

#ifdef PCS_IMG
    /*disable enqdrop*/
    for (i = 0; i < p_ds_attr->lport_num; i++)
    {
        tmp_lport = p_ds_attr->lport_list[i].lport;
        CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, tmp_lport, &port_attr_tmp));
        index = DRV_INS(0, 0);
        if (1 == p_ds_attr->lport_list[i].upt_flag)
        {
            cmd = DRV_IOR(QMgrShellChanWrEnCtl_t, QMgrShellChanWrEnCtl_chanWrEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, data));
            CTC_BMP_SET(data, port_attr_tmp->chan_id);
            cmd = DRV_IOW(QMgrShellChanWrEnCtl_t, QMgrShellChanWrEnCtl_chanWrEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, data));
        }
        port_mac_config.lport = tmp_lport;
        port_mac_config.speed_mode = port_attr_tmp->speed_mode;
        port_mac_config.speed_value = port_attr_tmp->speed_value;
        port_mac_config.interface_type = port_attr_tmp->interface_type;
        CTC_ERROR_RETURN(sys_usw_port_mac_config_attach(lchip, &port_mac_config));    
    }
#else
    /* disable enqdrop & add queue new-built mac to channel */
    for(i = 0; i < p_ds_attr->lport_num; i++)
    {
        SYS_CONDITION_CONTINUE(SYS_DS_LPORT_DROP == p_ds_attr->lport_list[i].upt_flag);
        tmp_lport = p_ds_attr->lport_list[i].lport;
        tmp_gport = CTC_MAP_LPORT_TO_GPORT((uint32)gchip, (uint32)tmp_lport);

        sys_usw_queue_set_port_drop_en(lchip, tmp_gport, FALSE, &(p_ds_attr->shp_profile[i]));

        CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, tmp_lport, &port_attr_tmp));

        sys_usw_add_port_to_channel(lchip, tmp_lport, port_attr_tmp->chan_id, 0);
        
        port_mac_config.lport = tmp_lport;
        port_mac_config.speed_mode = port_attr_tmp->speed_mode;
        port_mac_config.speed_value = port_attr_tmp->speed_value;
        port_mac_config.interface_type = port_attr_tmp->interface_type;
        CTC_ERROR_RETURN(sys_usw_port_mac_config_attach(lchip, &port_mac_config));
    }
#endif

    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_DATAPATH, SYS_WB_APPID_DATAPATH_SUBID_MASTER,        1);
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_DATAPATH, SYS_WB_APPID_DATAPATH_SUBID_HSS_ATTRIBUTE, 1);
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT,     SYS_WB_APPID_PORT_SUBID_MAC_PROP,          1);

    return CTC_E_NONE;
}

#define  __TMM_SYS_MAC_API__
int32 
_sys_tmm_cpumac_set_hss_tx_reset(uint8 lchip, uint8 pcs_idx, uint8 lane_num, uint32 val_rst, uint8 swap_flag)
{
    uint8    idx         = 0;
    uint32   cmd         = 0;
    uint32   value[4]    = {0};
    fld_id_t field_id[4] = {0};
    CpuMacCtlResetCtl_m rst_ctl;

    if(lane_num > 4)
    {
        return CTC_E_INVALID_PARAM;
    }

    /*reset lane consider swap*/
    if(TRUE == swap_flag)
    {
        if (1 == lane_num)
        {
            switch (pcs_idx)
            {
            case 0:
                field_id[0] = CpuMacCtlResetCtl_resetHssTx2_f;
                break;
            case 1:
                field_id[0] = CpuMacCtlResetCtl_resetHssTx1_f;
                break;
            case 2:
                field_id[0] = CpuMacCtlResetCtl_resetHssTx0_f;
                break;
            case 3:
                field_id[0] = CpuMacCtlResetCtl_resetHssTx3_f;
                break;
            }
            value[0] = val_rst;
        }
        else if(2 == lane_num)
        {
            switch (pcs_idx)
            {
            case 0:
                field_id[0] = CpuMacCtlResetCtl_resetHssTx2_f;
                field_id[1] = CpuMacCtlResetCtl_resetHssTx1_f;
                break;
            case 2:
                field_id[0] = CpuMacCtlResetCtl_resetHssTx0_f;
                field_id[1] = CpuMacCtlResetCtl_resetHssTx3_f;
                break;
            }
            value[0] = val_rst;
            value[1] = val_rst;
        }
        else if(4 == lane_num)
        {
            field_id[0] = CpuMacCtlResetCtl_resetHssTx2_f;
            field_id[1] = CpuMacCtlResetCtl_resetHssTx1_f;
            field_id[2] = CpuMacCtlResetCtl_resetHssTx0_f;
            field_id[3] = CpuMacCtlResetCtl_resetHssTx3_f;
            value[0] = val_rst;
            value[1] = val_rst;
            value[2] = val_rst;
            value[3] = val_rst;
        }
    }
    else
    {
        for(idx = 0; idx < lane_num; idx++)
        {
            field_id[idx] = CpuMacCtlResetCtl_resetHssTx0_f + idx + pcs_idx;
            value[idx] = val_rst;
        }
    }

    cmd = DRV_IOR(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rst_ctl));
    for(idx = 0; idx < lane_num; idx++)
    {
        DRV_IOW_FIELD(lchip, CpuMacCtlResetCtl_t, field_id[idx], &(value[idx]), &rst_ctl);
    }
    cmd = DRV_IOW(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rst_ctl));

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_reset_sgmac_rx_buffer(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 cmd = 0;
    uint32 tbl_id = QuadSgmacReserved_t;
    uint32 value = 0;
    uint8 internal_mac_idx = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    QuadSgmacReserved_m mac_rsv;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    internal_mac_idx = port_attr->internal_mac_idx;

    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rsv));
    DRV_IOR_FIELD(lchip, tbl_id, QuadSgmacReserved_reserved_f, &value, &mac_rsv);
    if(enable)
    {
        value |= (1 << internal_mac_idx);
    }
    else
    {
        value &= (~(1 << internal_mac_idx));
    }
    DRV_IOW_FIELD(lchip, tbl_id, QuadSgmacReserved_reserved_f, &value, &mac_rsv);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rsv));

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_sgmac_sgmii_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 value            = 0;
    uint32 cmd              = 0;
    uint32 tbl_id           = 0;
    uint32 field_id         = 0;
    uint8  mii_idx          = 0;
    uint8  pcs_idx          = 0;
    uint8  internal_mac_idx = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    SharedPcsSoftRst_m  pcs_rst;
    SharedMiiResetCfg_m mii_rst;
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    mii_idx  = port_attr->mii_idx;
    pcs_idx  = port_attr->pcs_idx;
    SYS_TMM_CPUMAC_GET_INTERNAL_MAC_ID(port_attr->mac_id, internal_mac_idx);

    if (enable)  /* release reset */
    {
        value = 0;
        /* Release Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstPcsTx0_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Release Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 1, value, FALSE));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        /* Release Mii Rx Soft Reset */
        /* SGMII & 2.5G do not use monitor RX auto, so RX MII reset will be 0 immediately. */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Release Pcs Rx Soft Reset */
        if((2 != pcs_idx) && (3 != pcs_idx))
        {
            tbl_id = SharedPcsSoftRst_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
            field_id = SharedPcsSoftRst_softRstPcsRx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        }
    }
    else     /* Assert reset */
    {
        value = 1;
        /* Assert Pcs Rx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstPcsRx0_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Assert Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 1));
        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 0));

        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 1, value, FALSE));

        /* Assert Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Assert Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstPcsTx0_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
    }

    return CTC_E_NONE;
}

int32
sys_tmm_cpumac_fec_xfi_xlg_cfg(uint8 lchip, uint32 value, uint8 internal_mac_idx, uint8 shared_fec_idx, 
                                         uint8 pcs_mode, uint8 rx_flag)
{
    uint32 cmd      = 0;
    uint32 tbl_id   = 0;
    uint32 field_id = 0;
    uint32 step     = 0;
    uint8  port_cnt = 0;
    uint32 field_id_base = 0;
    ResetCtlSharedFec_m rst_fec;

    tbl_id = ResetCtlSharedFec_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rst_fec));

    step = ResetCtlSharedFec_cfgSoftRstFecRx1_f - ResetCtlSharedFec_cfgSoftRstFecRx0_f;
    field_id_base = rx_flag ? ResetCtlSharedFec_cfgSoftRstFecRx0_f : ResetCtlSharedFec_cfgSoftRstFecTx0_f;
    if(CTC_CHIP_SERDES_XFI_MODE == pcs_mode)
    {
        field_id = field_id_base + step*internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &rst_fec);
    }
    else if(CTC_CHIP_SERDES_XLG_MODE == pcs_mode)
    {
        for(; port_cnt < 4; port_cnt++)
        {
            field_id = field_id_base + step*port_cnt;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &rst_fec);
        }
    }

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rst_fec));

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_get_fec_en(uint8 lchip, uint32 lport, uint32* p_value)
{
    uint32 cmd       = 0;
    uint32 tbl_id    = 0;
    uint8 internal_mac_idx = 0;
    uint8 mii_idx = 0;
    uint8 step = 0;
    uint32 enable = 0;
    uint32 rs_fec = 0;
    SharedPcsFecCfg_m  pcscfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_PTR_VALID_CHECK(p_value);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        return CTC_E_INVALID_PARAM;
    }

    mii_idx          = port_attr->mii_idx;
    internal_mac_idx = port_attr->internal_mac_idx;

    tbl_id = SharedPcsFecCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcscfg));

    switch(port_attr->pcs_mode)
    {
        case CTC_CHIP_SERDES_XXVG_MODE:
            if (0 == internal_mac_idx % 4)
            enable = GetSharedPcsFecCfg(V, xfiPcsFecEn0_f, &pcscfg);
            else if (1 == internal_mac_idx % 4)
                enable = GetSharedPcsFecCfg(V, xfiPcsFecEn1_f, &pcscfg);
            else if (2 == internal_mac_idx % 4)
                enable = GetSharedPcsFecCfg(V, xfiPcsFecEn2_f, &pcscfg);
            else
                enable = GetSharedPcsFecCfg(V, xfiPcsFecEn3_f, &pcscfg);
            if(enable)
            {
                step = SharedMii1Cfg_t - SharedMii0Cfg_t;
                tbl_id = SharedMii0Cfg_t + mii_idx*step;
                cmd = DRV_IOR(tbl_id, SharedMii0Cfg_cfgMiiTxRsFecEn0_f);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rs_fec));
                if(rs_fec)
                {
                    *p_value = CTC_PORT_FEC_TYPE_RS;
                }
                else
                {
                    *p_value = CTC_PORT_FEC_TYPE_BASER;
                }
            }
            else
            {
                *p_value = CTC_PORT_FEC_TYPE_NONE;
            }
            break;
        case CTC_CHIP_SERDES_LG_MODE:
            if (0 == internal_mac_idx % 4)
            {
                enable = GetSharedPcsFecCfg(V, lgPcsFecEn0_f, &pcscfg);
                rs_fec = GetSharedPcsFecCfg(V, lgPcsFecRsMode0_f, &pcscfg);
            }
            else
            {
                enable = GetSharedPcsFecCfg(V, lgPcsFecEn1_f, &pcscfg);
                rs_fec = GetSharedPcsFecCfg(V, lgPcsFecRsMode1_f, &pcscfg);
            }
            if(enable)
            {
                if(rs_fec)
                {
                    *p_value = CTC_PORT_FEC_TYPE_RS;
                }
                else
                {
                    *p_value = CTC_PORT_FEC_TYPE_BASER;
                }
            }
            else
            {
                *p_value = CTC_PORT_FEC_TYPE_NONE;
            }
            break;
        case CTC_CHIP_SERDES_CG_MODE:
            enable = GetSharedPcsFecCfg(V, cgfecEn_f, &pcscfg);
            if(enable)
            {
                *p_value = CTC_PORT_FEC_TYPE_RS;
            }
            else
            {
                *p_value = CTC_PORT_FEC_TYPE_NONE;
            }
            break;
        case CTC_CHIP_SERDES_XFI_MODE:
            if (0 == internal_mac_idx % 4)
                enable = GetSharedPcsFecCfg(V, xfiPcsFecEn0_f, &pcscfg);
            else if (1 == internal_mac_idx % 4)
                enable = GetSharedPcsFecCfg(V, xfiPcsFecEn1_f, &pcscfg);
            else if (2 == internal_mac_idx % 4)
                enable = GetSharedPcsFecCfg(V, xfiPcsFecEn2_f, &pcscfg);
            else
                enable = GetSharedPcsFecCfg(V, xfiPcsFecEn3_f, &pcscfg);
            if(enable)
            {
                *p_value = CTC_PORT_FEC_TYPE_BASER;
            }
            else
            {
                *p_value = CTC_PORT_FEC_TYPE_NONE;
            }
            break;
        case CTC_CHIP_SERDES_XLG_MODE:
            enable = GetSharedPcsFecCfg(V, xlgPcsFecEn_f, &pcscfg);
            if(enable)
            {
                *p_value = CTC_PORT_FEC_TYPE_BASER;
            }
            else
            {
                *p_value = CTC_PORT_FEC_TYPE_NONE;
            }
            break;
        default:
            return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

/*
SharedPcsSoftRst  sigdet  Opteraion
1                 1       SharedPcsSoftRst set 0
1                 0       NA (mac en but no signal)
0                 1       NA (already link up)
0                 0       SharedPcsSoftRst set 1
*/
int32
_sys_tmm_cpumac_lane3_pcs_rx_reset(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr)
{
    uint32 cmd            = 0;
    uint32 value          = 0;
    uint32 fld_id         = SharedPcsSoftRst_softRstPcsRx0_f + port_attr->pcs_idx;
    uint32 phyready       = 0;
    uint8  loopback_inter = FALSE;
    uint8  serdes_link    = FALSE;
    uint8  serdes_id      = port_attr->multi_serdes_id[0];
    SharedPcsSoftRst_m    pcs_rst;

    SYS_CONDITION_RETURN((CTC_CHIP_SERDES_XFI_MODE != port_attr->pcs_mode) && 
                         (CTC_CHIP_SERDES_2DOT5G_MODE != port_attr->pcs_mode) && 
                         (CTC_CHIP_SERDES_XXVG_MODE != port_attr->pcs_mode) &&
                         (CTC_CHIP_SERDES_SGMII_MODE != port_attr->pcs_mode), CTC_E_NONE);
    SYS_CONDITION_RETURN(((98 != serdes_id) && (99 != serdes_id)), CTC_E_NONE);

    CTC_ERROR_RETURN(sys_tmm_serdes_get_phyready(lchip, serdes_id, &phyready));
    CTC_ERROR_RETURN(sys_tmm_serdes_get_internal_loopback_pcs(lchip, serdes_id, &loopback_inter));
    serdes_link = phyready || loopback_inter;

    cmd = DRV_IOR(SharedPcsSoftRst_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
    DRV_IOR_FIELD(lchip, SharedPcsSoftRst_t, fld_id, &value, &pcs_rst);

    if((1 == value) && (TRUE == serdes_link))
    {
        value = 0;
    }
    else if((0 == value) && (FALSE == serdes_link))
    {
        value = 1;
    }
    else
    {
        return CTC_E_NONE;
    }
    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[CPUMAC lane 2/3] serdes_id %u, serdes_link %u, PCS RX %u\n", serdes_id, 
        serdes_link, value);
    DRV_IOW_FIELD(lchip, SharedPcsSoftRst_t, fld_id, &value, &pcs_rst);
    cmd = DRV_IOW(SharedPcsSoftRst_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_sgmac_xfi_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 value    = 0;
    uint32 cmd      = 0;
    uint32 tbl_id   = 0;
    uint32 field_id = 0;
    uint8 mii_idx = 0;
    uint8 pcs_idx = 0;
    uint8 internal_mac_idx = 0;
    uint32 fec_en = 0;
    uint8 shared_fec_idx = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    SharedPcsSoftRst_m  pcs_rst;
    SharedMiiResetCfg_m mii_rst;
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    mii_idx          = port_attr->mii_idx;
    pcs_idx          = port_attr->pcs_idx;
    SYS_TMM_CPUMAC_GET_INTERNAL_MAC_ID(port_attr->mac_id, internal_mac_idx);

    /* get fec en */
    CTC_ERROR_RETURN(_sys_tmm_cpumac_get_fec_en(lchip, lport, &fec_en));

    shared_fec_idx = SYS_MAC_GET_SHARED_FEC_IDX_BY_MII_ID(mii_idx);

    if (enable)  /* release reset */
    {
        value = 0;
        if (fec_en)
        {
            CTC_ERROR_RETURN(sys_tmm_cpumac_fec_xfi_xlg_cfg(lchip, value, internal_mac_idx, 
                shared_fec_idx, CTC_CHIP_SERDES_XFI_MODE, FALSE));
        }
        /* Release Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstPcsTx0_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Release Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 1, value, FALSE));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        /* Release Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Release Pcs Rx Soft Reset */
        /*if rx rst is on hold, do not set reset 0*/
        /*cpumac lane 3 sikp rcs rx release*/
        if((0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold) && (2 != pcs_idx) && (3 != pcs_idx))
        {
            tbl_id = SharedPcsSoftRst_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
            field_id = SharedPcsSoftRst_softRstPcsRx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        }

        if (fec_en)
        {
            CTC_ERROR_RETURN(sys_tmm_cpumac_fec_xfi_xlg_cfg(lchip, value, internal_mac_idx, 
                shared_fec_idx, CTC_CHIP_SERDES_XFI_MODE, TRUE));
        }
    }
    else     /* Assert reset */
    {
        value = 1;
        if (fec_en)
        {
            CTC_ERROR_RETURN(sys_tmm_cpumac_fec_xfi_xlg_cfg(lchip, value, internal_mac_idx, 
                shared_fec_idx, CTC_CHIP_SERDES_XFI_MODE, TRUE));
        }
        /* Assert Pcs Rx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstPcsRx0_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Assert Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 1));
        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 0));

        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 1, value, FALSE));

        /* Assert Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Assert Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstPcsTx0_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        if (fec_en)
        {
            CTC_ERROR_RETURN(sys_tmm_cpumac_fec_xfi_xlg_cfg(lchip, value, internal_mac_idx, 
                shared_fec_idx, CTC_CHIP_SERDES_XFI_MODE, FALSE));
        }
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_sgmac_xlg_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 value    = 0;
    uint32 cmd      = 0;
    uint32 tbl_id   = 0;
    uint32 field_id = 0;
    uint8 mii_idx = 0;
    uint8 pcs_idx = 0;
    uint8 internal_mac_idx = 0;
    uint32 fec_en = 0;
    uint8 shared_fec_idx = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    SharedPcsSoftRst_m  pcs_rst;
    SharedMiiResetCfg_m mii_rst;
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    mii_idx          = port_attr->mii_idx;
    pcs_idx          = port_attr->pcs_idx;
    SYS_TMM_CPUMAC_GET_INTERNAL_MAC_ID(port_attr->mac_id, internal_mac_idx);

    /* get fec en */
    CTC_ERROR_RETURN(_sys_tmm_cpumac_get_fec_en(lchip, lport, &fec_en));

    shared_fec_idx = SYS_MAC_GET_SHARED_FEC_IDX_BY_MII_ID(mii_idx);
    if (internal_mac_idx != 0)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"mac_id: %d is not xlg mode \n", port_attr->mac_id);
        return CTC_E_INVALID_PARAM;
    }

    if (enable)
    {
        value = 0;
        if (fec_en)
        {
            CTC_ERROR_RETURN(sys_tmm_cpumac_fec_xfi_xlg_cfg(lchip, value, internal_mac_idx, 
                shared_fec_idx, CTC_CHIP_SERDES_XLG_MODE, FALSE));
        }
        /* Release Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstXlgTx_f;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Release Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 4, value, port_attr->flag));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        /* Release Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Release Pcs Rx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_rxDeskewSoftRst_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        /*if rx rst is on hold, do not set reset 0*/
        if(0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold)
        {
            tbl_id = SharedPcsSoftRst_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
            field_id = SharedPcsSoftRst_softRstXlgRx_f;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        }

        if (fec_en)
        {
            CTC_ERROR_RETURN(sys_tmm_cpumac_fec_xfi_xlg_cfg(lchip, value, internal_mac_idx, 
                shared_fec_idx, CTC_CHIP_SERDES_XLG_MODE, TRUE));
        }
    }
    else
    {
        value = 1;
        if (fec_en)
        {
            CTC_ERROR_RETURN(sys_tmm_cpumac_fec_xfi_xlg_cfg(lchip, value, internal_mac_idx, 
                shared_fec_idx, CTC_CHIP_SERDES_XLG_MODE, TRUE));
        }
        /* Assert Pcs Rx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_rxDeskewSoftRst_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        field_id = SharedPcsSoftRst_softRstXlgRx_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Assert Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 1));
        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 0));

        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 4, value, port_attr->flag));

        /* Assert Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Assert Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstXlgTx_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        if (fec_en)
        {
            CTC_ERROR_RETURN(sys_tmm_cpumac_fec_xfi_xlg_cfg(lchip, value, internal_mac_idx, 
                shared_fec_idx, CTC_CHIP_SERDES_XLG_MODE, FALSE));
        }
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_sgmac_xxvg_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 value    = 0;
    uint32 cmd      = 0;
    uint32 tbl_id   = 0;
    uint32 field_id = 0;
    uint8 mii_idx = 0;
    uint8 pcs_idx = 0;
    uint8 internal_mac_idx = 0;
    uint32 fec_en = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    ResetCtlSharedFec_m fec_reset;
    SharedPcsSoftRst_m  pcs_rst;
    SharedMiiResetCfg_m mii_rst;
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    mii_idx          = port_attr->mii_idx;
    pcs_idx          = port_attr->pcs_idx;
    SYS_TMM_CPUMAC_GET_INTERNAL_MAC_ID(port_attr->mac_id, internal_mac_idx);

    /* get fec en */
    CTC_ERROR_RETURN(_sys_tmm_cpumac_get_fec_en(lchip, lport, &fec_en));

    if (enable)
    {
        /* Rlease Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            value = 0;
            field_id = ResetCtlSharedFec_cfgSoftRstFecTx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &fec_reset);
            value = 1;
            field_id = ResetCtlSharedFec_cfgSoftRstFecRx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &fec_reset);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
        }

        value = 0;
        /* Release Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstPcsTx0_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Release Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 1, value, port_attr->flag));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        /* Release Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Release Pcs Rx Soft Reset */
        /*if rx rst is on hold, do not set reset 0*/
        if((0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold) && (2 != pcs_idx) && (3 != pcs_idx))
        {
            tbl_id = SharedPcsSoftRst_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
            field_id = SharedPcsSoftRst_softRstPcsRx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        }

        /* Rlease Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            value = 0;
            field_id = ResetCtlSharedFec_cfgSoftRstFecTx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &fec_reset);
            value = 0;
            field_id = ResetCtlSharedFec_cfgSoftRstFecRx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &fec_reset);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
        }
    }
    else
    {
        /* Assert Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            value = 0;
            field_id = ResetCtlSharedFec_cfgSoftRstFecTx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &fec_reset);
            value = 1;
            field_id = ResetCtlSharedFec_cfgSoftRstFecRx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &fec_reset);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
        }

        value = 1;
        /* Assert Pcs Rx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstPcsRx0_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Assert Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 1));
        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 0));

        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 1, value, port_attr->flag));

        /* Assert Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Assert Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstPcsTx0_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Assert Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            value = 1;
            field_id = ResetCtlSharedFec_cfgSoftRstFecTx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &fec_reset);
            value = 1;
            field_id = ResetCtlSharedFec_cfgSoftRstFecRx0_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &fec_reset);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
        }
    }


    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_sgmac_lg_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 value    = 0;
    uint32 cmd      = 0;
    uint32 tbl_id   = 0;
    uint32 field_id = 0;
    uint8 lg_index = 0;
    uint8 mii_idx = 0;
    uint8 pcs_idx = 0;
    uint8 internal_mac_idx = 0;
    uint32 fec_en = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    ResetCtlSharedFec_m fec_reset;
    SharedPcsSoftRst_m  pcs_rst;
    SharedMiiResetCfg_m mii_rst;
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    mii_idx          = port_attr->mii_idx;
    pcs_idx          = port_attr->pcs_idx;
    SYS_TMM_CPUMAC_GET_INTERNAL_MAC_ID(port_attr->mac_id, internal_mac_idx);

    if ((internal_mac_idx != 0) && (internal_mac_idx != 2))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"mac_id: %d is not lg mode \n", port_attr->mac_id);
        return CTC_E_INVALID_PARAM;
    }

    /* get fec en */
    CTC_ERROR_RETURN(_sys_tmm_cpumac_get_fec_en(lchip, lport, &fec_en));

    if (internal_mac_idx <= 1)
    {
        lg_index = 0;
    }
    else
    {
        lg_index = 1;
    }

    if (enable)
    {
        /* Rlease Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            if (lg_index == 0)
            {
                value = 0;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx0_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx1_f, &value, &fec_reset);
                value = 1;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
            else
            {
                value = 0;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx2_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx3_f, &value, &fec_reset);
                value = 1;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
        }

        value = 0;
        /* Release Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        if (0 == lg_index)
        {
            DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstXlgTx_f, &value, &pcs_rst);
        }
        else
        {
            DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstLgTx_f, &value, &pcs_rst);
        }
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Release Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 2, value, port_attr->flag));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        /* Release Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Release Pcs Rx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        if (0 == lg_index)
        {
            DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_rxDeskewSoftRst_f, &value, &pcs_rst);
        }
        else
        {
            DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_rxDeskewSoftRstLg_f, &value, &pcs_rst);
        }
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        /*if rx rst is on hold, do not set reset 0*/
        if(0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold)
        {
            tbl_id = SharedPcsSoftRst_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
            if (0 == lg_index)
            {
                DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstXlgRx_f, &value, &pcs_rst);
            }
            else
            {
                DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstLgRx_f, &value, &pcs_rst);
            }
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        }

        /* Rlease Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            if (lg_index == 0)
            {
                value = 0;
                 /*DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx0_f, &value, &fec_reset);*/
                 /*DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx1_f, &value, &fec_reset);*/
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
            else
            {
                value = 0;
                 /*DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx2_f, &value, &fec_reset);*/
                 /*DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx3_f, &value, &fec_reset);*/
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
        }
    }
    else
    {
        /* Assert Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            if (lg_index == 0)
            {
                value = 0;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx0_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx1_f, &value, &fec_reset);
                value = 1;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
            else
            {
                value = 0;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx2_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx3_f, &value, &fec_reset);
                value = 1;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
        }

        value = 1;
        /* Assert Pcs Rx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        if (0 == lg_index)
        {
            DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_rxDeskewSoftRst_f, &value, &pcs_rst);
            DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstXlgRx_f, &value, &pcs_rst);
        }
        else
        {
            DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_rxDeskewSoftRstLg_f, &value, &pcs_rst);
            DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstLgRx_f, &value, &pcs_rst);
        }

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Assert Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 1));
        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 0));

        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 2, value, port_attr->flag));

        /* Assert Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Assert Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        if (0 == lg_index)
        {
            DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstXlgTx_f, &value, &pcs_rst);
        }
        else
        {
            DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstLgTx_f, &value, &pcs_rst);
        }
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Assert Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            if (lg_index == 0)
            {
                value = 1;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx0_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx1_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
            else
            {
                value = 1;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx2_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx3_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
        }
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_set_sgmac_cg_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 value    = 0;
    uint32 cmd      = 0;
    uint32 tbl_id   = 0;
    uint32 field_id = 0;
    uint8 mii_idx = 0;
    uint8 pcs_idx = 0;
    uint8 internal_mac_idx = 0;
    uint32 fec_en = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    ResetCtlSharedFec_m fec_reset;
    SharedPcsSoftRst_m  pcs_rst;
    SharedMiiResetCfg_m mii_rst;
    CpuMacCtlResetCtl_m mac_rst;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    mii_idx          = port_attr->mii_idx;
    pcs_idx          = port_attr->pcs_idx;
    SYS_TMM_CPUMAC_GET_INTERNAL_MAC_ID(port_attr->mac_id, internal_mac_idx);

    if (internal_mac_idx != 0)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"mac_id: %d is not cg mode \n", port_attr->mac_id);
        return CTC_E_INVALID_PARAM;
    }

    /* get fec en */
    CTC_ERROR_RETURN(_sys_tmm_cpumac_get_fec_en(lchip, lport, &fec_en));

    if (enable)
    {
        /* Rlease Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            value = 0;
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx0_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx1_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx2_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx3_f, &value, &fec_reset);
            value = 1;
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
        }
        /* Release Pcs Tx Soft Reset */
        value = 0;
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstCgTx_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Release Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 4, value, port_attr->flag));

        /* Release Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        /* Release Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Release Pcs Rx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_rxDeskewSoftRst_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        /*if rx rst is on hold, do not set reset 0*/
        if(0 == p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold)
        {
            tbl_id = SharedPcsSoftRst_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
            field_id = SharedPcsSoftRst_softRstCgRx_f + pcs_idx;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        }
        /* Rlease Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            value = 0;
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx0_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx1_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx2_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx3_f, &value, &fec_reset);
            value = 0;
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
        }
    }
    else
    {
        /* Assert Fec Rx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            value = 0;
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx0_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx1_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx2_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx3_f, &value, &fec_reset);
            value = 1;
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
        }

        value = 1;
        /* Assert Pcs Rx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_rxDeskewSoftRst_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        field_id = SharedPcsSoftRst_softRstCgRx_f + pcs_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Assert Mii Rx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstRx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 1));
        CTC_ERROR_RETURN(_sys_tmm_cpumac_reset_sgmac_rx_buffer(lchip, lport, 0));

        /* Assert Sgmac Reset */
        tbl_id = CpuMacCtlResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));
        field_id = CpuMacCtlResetCtl_resetCoreSgmac0_f + internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mac_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_rst));

        CTC_ERROR_RETURN(_sys_tmm_cpumac_set_hss_tx_reset(lchip, pcs_idx, 4, value, port_attr->flag));

        /* Assert Mii Tx Soft Reset */
        tbl_id = SharedMiiResetCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
        field_id = SharedMiiResetCfg_cfgSoftRstTx0_f + mii_idx;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &mii_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

        /* Assert Pcs Tx Soft Reset */
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        field_id = SharedPcsSoftRst_softRstCgTx_f;
        DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

        /* Assert Fec Tx Soft Reset if Fec enabled */
        if (fec_en)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            value = 1;
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx0_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx1_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx2_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecTx3_f, &value, &fec_reset);
            value = 1;
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_set_mac_en(uint8 lchip, uint32 lport, uint8 enable)
{
#if !defined(EMULATION_ENV) || defined(PCS_IMG)
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    /* PCS/MII/Sgmac/FEC reset or release */
    if (1 != SDK_WORK_PLATFORM)
    {
        switch (port_attr->pcs_mode)
        {
            case CTC_CHIP_SERDES_SGMII_MODE:
            case CTC_CHIP_SERDES_2DOT5G_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_sgmac_sgmii_en(lchip, lport, enable));
                break;
            case CTC_CHIP_SERDES_XFI_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_sgmac_xfi_en(lchip, lport, enable));
                break;
            case CTC_CHIP_SERDES_XLG_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_sgmac_xlg_en(lchip, lport, enable));
                break;
            case CTC_CHIP_SERDES_XXVG_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_sgmac_xxvg_en(lchip, lport, enable));
                break;
            case CTC_CHIP_SERDES_LG_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_sgmac_lg_en(lchip, lport, enable));
                break;
            case CTC_CHIP_SERDES_CG_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_set_sgmac_cg_en(lchip, lport, enable));
                break;
            default:
                break;
        }
    }
    /*p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en = ((enable)?TRUE:FALSE);*/
#endif
    return CTC_E_NONE;
}

int32
sys_tmm_mc_mac_pcs_rx_rst(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr, uint8 reset)
{
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd    = 0;
    uint32 index  = 0;
    uint32 step   = 0;
    uint32 factor = 0;
    uint32 is_pcs_x16 = 0;
    uint32 pcs_x8_x16_index = 0;
    uint32 array32[2] = {0};
    McPcsX16LanesResetCtl_m     pcs_x16_rst;
    McPcsX16LanesSgmiiReset_m   sgmii_x16_rst;
    McPcsX16LanesQsgmiiReset_m  qsgmii_rst;
    McPcsX8LanesResetCtl_m      pcs_x8_rst;

    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
    
    index = DRV_INS(pcs_x8_x16_index, 0);

    if(reset)
    {
        p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold = 1;

        if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            if(is_pcs_x16)
            {
                tbl_id = McPcsX16LanesSgmiiReset_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_x16_rst));

                fld_id = McPcsX16LanesSgmiiReset_cfgSgmiiPcsRxSoftRst_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &sgmii_x16_rst);

                array32[0] |= (1 << (port_attr->pcs_idx % 16)) ;
                DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &sgmii_x16_rst, pcs_x8_x16_index, 0);

                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_x16_rst));
            }
            else
            {
                tbl_id = McPcsX8LanesResetCtl_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));

                fld_id = McPcsX8LanesResetCtl_cfgSgmiiPcsRxSoftRst_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst);

                array32[0] |= (1 << (port_attr->pcs_idx % 8)) ;
                DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst, pcs_x8_x16_index, 0);

                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));
            }
        }
        else if(CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
        {
            tbl_id = McPcsX16LanesQsgmiiReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &qsgmii_rst));

            step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPcsRxSoftRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsRxSoftRst_f;
            factor = port_attr->pcs_idx % 8;

            fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsRxSoftRst_f + step*factor;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &qsgmii_rst);

            array32[0] |= (1 << (port_attr->mac_id % 4)) ;
            DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &qsgmii_rst, pcs_x8_x16_index, 0);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &qsgmii_rst));
        }
        else
        {
            if(is_pcs_x16)
            {
                tbl_id = McPcsX16LanesResetCtl_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_rst));

                fld_id = McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x16_rst);

                array32[0] |= (1 << (port_attr->pcs_idx % 16));
                DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x16_rst, pcs_x8_x16_index, 0);

                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_rst));
            }
            else
            {
                index = DRV_INS(pcs_x8_x16_index, 0);

                tbl_id = McPcsX8LanesResetCtl_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));

                fld_id = McPcsX8LanesResetCtl_cfgRxSoftRstChanBmp_f;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst);

                array32[0] |= (1 << (port_attr->pcs_idx % 8)) ;
                DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst, pcs_x8_x16_index, 0);

                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));
            }
        }

        /*HATA rx*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 1));
    }
    else
    {
        if((TRUE == p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en) || (port_attr->port_type == SYS_DMPS_INACTIVE_NETWORK_PORT))
        {
            /*HATA rx*/
            CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 0));

            if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
                if(is_pcs_x16)
                {
                    tbl_id = McPcsX16LanesSgmiiReset_t;
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_x16_rst));

                    fld_id = McPcsX16LanesSgmiiReset_cfgSgmiiPcsRxSoftRst_f;
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &sgmii_x16_rst);

                    array32[0] &= ~(1 << (port_attr->pcs_idx % 16)) ;
                    DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &sgmii_x16_rst, pcs_x8_x16_index, 0);

                    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_x16_rst));
                }
                else
                {
                    tbl_id = McPcsX8LanesResetCtl_t;
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));

                    fld_id = McPcsX8LanesResetCtl_cfgSgmiiPcsRxSoftRst_f;
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst);
                    array32[0] &= ~(1 << (port_attr->pcs_idx % 8)) ;
                    DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst, pcs_x8_x16_index, 0);

                    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));
                }
            }
            else if(CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
            {
                tbl_id = McPcsX16LanesQsgmiiReset_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &qsgmii_rst));

                step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPcsRxSoftRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsRxSoftRst_f;
                factor = port_attr->pcs_idx % 8;

                fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsRxSoftRst_f + step*factor;
                DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &qsgmii_rst);

                array32[0] &= ~(1 << (port_attr->mac_id % 4)) ;
                DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &qsgmii_rst, pcs_x8_x16_index, 0);

                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &qsgmii_rst));
            }
            else
            {
                if(is_pcs_x16)
                {
                    tbl_id = McPcsX16LanesResetCtl_t;
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_rst));

                    fld_id = McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f;
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x16_rst);

                    array32[0] &= ~(1 << (port_attr->pcs_idx % 16));
                    DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x16_rst, pcs_x8_x16_index, 0);

                    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_rst));
                }
                else
                {
                    tbl_id = McPcsX8LanesResetCtl_t;
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));

                    fld_id = McPcsX8LanesResetCtl_cfgRxSoftRstChanBmp_f;
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst);

                    array32[0] &= ~(1 << (port_attr->pcs_idx % 8)) ;
                    DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst, pcs_x8_x16_index, 0);

                    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));
                }
            }
        }
        p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold = 0;
    }
    return CTC_E_NONE;
}

int32
_sys_tmm_mc_mac_get_pcs_rst(uint8 lchip, uint16 lport, uint8 dir, sys_datapath_lport_attr_t* port_attr, uint8* p_reset)
{
    uint8  reset  = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 cmd    = 0;
    uint32 index  = 0;
    uint32 step   = 0;
    uint32 factor = 0;
    uint32 is_pcs_x16 = 0;
    uint32 pcs_x8_x16_index = 0;
    uint32 array32[2] = {0};
    McPcsX16LanesResetCtl_m     pcs_x16_rst;
    McPcsX16LanesSgmiiReset_m   sgmii_x16_rst;
    McPcsX16LanesQsgmiiReset_m  qsgmii_rst;
    McPcsX8LanesResetCtl_m      pcs_x8_rst;

    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
    
    index = DRV_INS(pcs_x8_x16_index, 0);

    if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
    {
        if(is_pcs_x16)
        {
            tbl_id = McPcsX16LanesSgmiiReset_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_x16_rst));

            fld_id = (DMPS_RX == dir) ? McPcsX16LanesSgmiiReset_cfgSgmiiPcsRxSoftRst_f : 
                                        McPcsX16LanesSgmiiReset_cfgSgmiiPcsTxSoftRst_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &sgmii_x16_rst);

            reset = ((array32[0] >> (port_attr->pcs_idx % 16)) & 0x00000001);
        }
        else
        {
            tbl_id = McPcsX8LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));

            fld_id = (DMPS_RX == dir) ? McPcsX8LanesResetCtl_cfgSgmiiPcsRxSoftRst_f : 
                                        McPcsX8LanesResetCtl_cfgSgmiiPcsTxSoftRst_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst);

            reset = ((array32[0] >> (port_attr->pcs_idx % 8)) & 0x00000001);
        }
    }
    else if(CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
    {
        tbl_id = McPcsX16LanesQsgmiiReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &qsgmii_rst));

        step = McPcsX16LanesQsgmiiReset_resetQsgmii_1_qsgmiiPcsRxSoftRst_f - McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsRxSoftRst_f;
        factor = port_attr->pcs_idx % 8;

        fld_id = McPcsX16LanesQsgmiiReset_resetQsgmii_0_qsgmiiPcsRxSoftRst_f + step*factor;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &qsgmii_rst);
        
        reset = ((array32[0] >> (port_attr->mac_id % 4)) & 0x00000001);
    }
    else
    {
        if(is_pcs_x16)
        {
            tbl_id = McPcsX16LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_rst));

            fld_id = (DMPS_RX == dir) ? McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f : McPcsX16LanesResetCtl_cfgTxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x16_rst);

            reset = ((array32[0] >> (port_attr->pcs_idx % 16)) & 0x00000001);
        }
        else
        {
            index = DRV_INS(pcs_x8_x16_index, 0);

            tbl_id = McPcsX8LanesResetCtl_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));

            fld_id = (DMPS_RX == dir) ? McPcsX8LanesResetCtl_cfgRxSoftRstChanBmp_f : McPcsX8LanesResetCtl_cfgTxSoftRstChanBmp_f;
            DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst);

            reset = ((array32[0] >> (port_attr->pcs_idx % 8)) & 0x00000001);
        }
    }
    SYS_USW_VALID_PTR_WRITE(p_reset, reset);

    return CTC_E_NONE;
}

int32
sys_tmm_cpumac_pcs_rx_rst(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr, uint8 reset)
{
    uint32 value    = 0;
    uint32 cmd      = 0;
    uint32 tbl_id   = 0;
    uint32 field_id = 0;
    uint8  internal_mac_idx = port_attr->internal_mac_idx;
    uint8  lg_index = (internal_mac_idx <= 1) ? 0 : 1;
    SharedPcsSoftRst_m   pcs_rst;
    ResetCtlSharedFec_m  fec_reset;

    if(reset)
    {
        p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold = 1;

        if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            /* Assert Fec Rx Soft Reset */
            if((CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode))
            {
                tbl_id = ResetCtlSharedFec_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
                value = 1;
                field_id = ResetCtlSharedFec_cfgSoftRstFecRx0_f + internal_mac_idx;
                DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }

            tbl_id = SharedPcsSoftRst_t;
            field_id = SharedPcsSoftRst_softRstPcsRx0_f + internal_mac_idx;
            cmd = DRV_IOW(tbl_id, field_id);
            value = 1;
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        }
        else if(CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
        {
            /* Assert Fec Rx Soft Reset */
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            if (lg_index == 0)
            {
                value = 1;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
            else
            {
                value = 1;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }

            /* Assert Pcs Rx Soft Reset */
            tbl_id = SharedPcsSoftRst_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
            value = 1;
            if (0 == lg_index)
            {
                DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstXlgRx_f, &value, &pcs_rst);
            }
            else
            {
                DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstLgRx_f, &value, &pcs_rst);
            }
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        }
        else if(CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
        {
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            value = 1;
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            /* Assert Pcs Rx Soft Reset */
            tbl_id = SharedPcsSoftRst_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
            value = 1;
            field_id = SharedPcsSoftRst_softRstXlgRx_f;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        }
        else if(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode)
        {
            /* Assert Fec Rx Soft Reset */
            tbl_id = ResetCtlSharedFec_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            value = 1;
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
            DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));

            /* Assert Pcs Rx Soft Reset */
            tbl_id = SharedPcsSoftRst_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
            value = 1;
            field_id = SharedPcsSoftRst_softRstCgRx_f;
            DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        }
    }
    else
    {
        if(FALSE != p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en)
        {
            if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
                || (CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode)
                || (CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode)
                || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
            {
                tbl_id = SharedPcsSoftRst_t;
                field_id = SharedPcsSoftRst_softRstPcsRx0_f + internal_mac_idx;
                cmd = DRV_IOW(tbl_id, field_id);
                value = 0;
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

                /* Rlease Fec Rx Soft Reset */
                if((CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode))
                {
                    tbl_id = ResetCtlSharedFec_t;
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
                    value = 0;
                    field_id = ResetCtlSharedFec_cfgSoftRstFecRx0_f + internal_mac_idx;
                    DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &fec_reset);
                    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
                }
            }
            else if(CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
            {
               /* Release Pcs Rx Soft Reset */
                tbl_id = SharedPcsSoftRst_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
                value = 0;
                if (0 == lg_index)
                {
                    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstXlgRx_f, &value, &pcs_rst);
                }
                else
                {
                    DRV_IOW_FIELD(lchip, tbl_id, SharedPcsSoftRst_softRstLgRx_f, &value, &pcs_rst);
                }
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

                /* Rlease Fec Rx Soft Reset */
                tbl_id = ResetCtlSharedFec_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
                if (lg_index == 0)
                {
                    value = 0;
                    DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
                    DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
                    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
                }
                else
                {
                    value = 0;
                    DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
                    DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);
                    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
                }
            }
            else if(CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
            {
                /* Release Pcs Rx Soft Reset */
                tbl_id = SharedPcsSoftRst_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
                value = 0;
                field_id = SharedPcsSoftRst_softRstXlgRx_f;
                DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

                tbl_id = ResetCtlSharedFec_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
                value = 0;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
            else if(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode)
            {
                /* Release Pcs Rx Soft Reset */
                tbl_id = SharedPcsSoftRst_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
                value = 0;
                field_id = SharedPcsSoftRst_softRstCgRx_f;
                DRV_IOW_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));

                /* Rlease Fec Rx Soft Reset */
                tbl_id = ResetCtlSharedFec_t;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
                value = 0;
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx0_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx1_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx2_f, &value, &fec_reset);
                DRV_IOW_FIELD(lchip, tbl_id, ResetCtlSharedFec_cfgSoftRstFecRx3_f, &value, &fec_reset);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fec_reset));
            }
        }
        p_usw_mac_master[lchip]->mac_prop[lport].rx_rst_hold = 0;
    }
    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_get_pcs_rst(uint8 lchip, uint16 lport, uint8 dir, sys_datapath_lport_attr_t* port_attr, uint8* p_reset)
{
    uint32 value    = 0;
    uint32 cmd      = 0;
    uint32 tbl_id   = 0;
    uint32 field_id = 0;
    uint8  internal_mac_idx = port_attr->internal_mac_idx;
    uint8  lg_index = (internal_mac_idx <= 1) ? 0 : 1;
    SharedPcsSoftRst_m   pcs_rst;

    if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
        || (CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode)
        || (CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode)
        || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
    {
        tbl_id = SharedPcsSoftRst_t;
        field_id = ((DMPS_RX == dir) ? SharedPcsSoftRst_softRstPcsRx0_f : SharedPcsSoftRst_softRstPcsTx0_f) + internal_mac_idx;
        cmd = DRV_IOR(tbl_id, field_id);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }
    else if(CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
    {
        tbl_id = SharedPcsSoftRst_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        if (0 == lg_index)
        {
            field_id = (DMPS_RX == dir) ? SharedPcsSoftRst_softRstXlgRx_f : SharedPcsSoftRst_softRstXlgTx_f;
            DRV_IOR_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        }
        else
        {
            field_id = (DMPS_RX == dir) ? SharedPcsSoftRst_softRstLgRx_f : SharedPcsSoftRst_softRstLgTx_f;
            DRV_IOR_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
        }
    }
    else if(CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
    {
        tbl_id = SharedPcsSoftRst_t;
        field_id = (DMPS_RX == dir) ? SharedPcsSoftRst_softRstXlgRx_f : SharedPcsSoftRst_softRstXlgTx_f;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        DRV_IOR_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
    }
    else if(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode)
    {
        tbl_id = SharedPcsSoftRst_t;
        field_id = (DMPS_RX == dir) ? SharedPcsSoftRst_softRstCgRx_f : SharedPcsSoftRst_softRstCgTx_f;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs_rst));
        DRV_IOR_FIELD(lchip, tbl_id, field_id, &value, &pcs_rst);
    }
    SYS_USW_VALID_PTR_WRITE(p_reset, (uint8)value);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_pcs_rx_rst(uint8 lchip, uint16 lport, uint8 reset)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    if (NULL == p_usw_mac_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    if ((port_attr->port_type == SYS_DMPS_NETWORK_PORT) || (port_attr->port_type == SYS_DMPS_INACTIVE_NETWORK_PORT))
    {
        if (CTC_PORT_IF_FLEXE != port_attr->interface_type)
        {
            CTC_ERROR_RETURN(sys_tmm_mc_mac_pcs_rx_rst(lchip, lport, port_attr, reset));
        }
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        CTC_ERROR_RETURN(sys_tmm_cpumac_pcs_rx_rst(lchip, lport, port_attr, reset));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% lport %d is not used \n", lport);
        return CTC_E_INVALID_PARAM;
    }
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_pcs_rst(uint8 lchip, uint16 lport, uint8 dir, uint8* p_reset)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    if (NULL == p_usw_mac_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    if ((port_attr->port_type == SYS_DMPS_NETWORK_PORT) || (port_attr->port_type == SYS_DMPS_INACTIVE_NETWORK_PORT))
    {
        if (CTC_PORT_IF_FLEXE != port_attr->interface_type)
        {
            CTC_ERROR_RETURN(_sys_tmm_mc_mac_get_pcs_rst(lchip, lport, dir, port_attr, p_reset));
        }
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        CTC_ERROR_RETURN(_sys_tmm_cpumac_get_pcs_rst(lchip, lport, dir, port_attr, p_reset));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% lport %d is not used \n", lport);
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mc_mac_mii_rx_rst(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr, uint8 reset)
{
    uint32 tbl_id = 0;
    uint32 cmd    = 0;
    uint32 fld_id = 0;
    uint32 factor = 0;
    uint32 index  = 0;
    uint32 val32[2] = {0};
    McMacRxSoftReset_m mm_rx_rst;

    index = DRV_INS(port_attr->txqm_id, 0);
    tbl_id = McMacRxSoftReset_t;
    fld_id = McMacRxSoftReset_cfgMcMacRxSoftReset_f;
    factor = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mm_rx_rst));
    DRV_IOR_FIELD(lchip, tbl_id, fld_id, val32, &mm_rx_rst);

    if (reset)
    {
        if (32 > factor)
        {
            val32[0] |= (1 << factor);
        }
        else
        {
            val32[1] |= (1 << (factor - 32));
        }
    }
    else
    {
        if (32 > factor)
        {
            val32[0] &= ~(1 << factor);
        }
        else
        {
            val32[1] &= ~(1 << (factor - 32));
        }
    }

    DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, val32, &mm_rx_rst, port_attr->txqm_id, 0);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mm_rx_rst));

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_mii_rx_rst(uint8 lchip, sys_datapath_lport_attr_t* port_attr, uint8 reset)
{
    uint32 tbl_id = 0;
    uint32 cmd    = 0;
    uint32 fld_id = 0;
    uint32 value  = 0;
    SharedMiiResetCfg_m mii_rst;

    tbl_id = SharedMiiResetCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));
    fld_id = SharedMiiResetCfg_cfgSoftRstRx0_f + port_attr->mii_idx;

    if (reset)
    {
        value = 1;
    }
    else
    {
        value = 0;
    }
    DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mii_rst);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mii_rst));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_mii_rx_rst(uint8 lchip, uint16 lport, uint8 reset)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    if (NULL == p_usw_mac_master[lchip])
    {
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN((SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type), CTC_E_NONE);
    if (port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        if (CTC_PORT_IF_FLEXE != port_attr->interface_type)
        {
            CTC_ERROR_RETURN(_sys_tmm_mc_mac_mii_rx_rst(lchip, lport, port_attr, reset));
        }
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        CTC_ERROR_RETURN(_sys_tmm_cpumac_mii_rx_rst(lchip, port_attr, reset));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% lport %d is not used \n", lport);
        return CTC_E_INVALID_PARAM;
    }
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_ignore_fault_cfg(uint8 lchip, uint16 lport, uint32 ignore_en)
{
    uint32 step             = 0;
    uint32 tbl_id           = 0;
    uint32 fld_id           = 0;
    uint32 cmd              = 0;
    uint32 internal_mac_idx = 0;
    uint32 index            = 0;
    uint32 value            = ignore_en ? 1 : 0;
    SharedMii0Cfg_m         mii_cfg;
    McMacMiiTxCfg_m         mii_tx_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));

    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        index = DRV_INS(port_attr->txqm_id, 0);

        internal_mac_idx = port_attr->internal_mac_idx;
        tbl_id = McMacMiiTxCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_tx_cfg));
        step = McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxIgnoreRemoteFault_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreRemoteFault_f;
        
        fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreRemoteFault_f + step*internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mii_tx_cfg);
        fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreLocalFault_f + step*internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mii_tx_cfg);
        fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreLintFault_f + step*internal_mac_idx;
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &mii_tx_cfg);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_tx_cfg));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        step = SharedMii1Cfg_t - SharedMii0Cfg_t;
        tbl_id = SharedMii0Cfg_t + step * (port_attr->mii_idx);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, &mii_cfg);

        DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiIgnoreLocalFault0_f,  &value, &mii_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiIgnoreRemoteFault0_f, &value, &mii_cfg);
        DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiIgnoreLintFault0_f,   &value, &mii_cfg);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, &mii_cfg);
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid lport %u! port_type %u\n", lport, port_attr->port_type);
        return CTC_E_INVALID_PARAM;
    }
    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_ignore_fault_cfg(uint8 lchip, uint16 lport, uint32 value)
{
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_ignore_fault_cfg(lchip, lport, value));
    MAC_UNLOCK;
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_ignore_fault_cfg(uint8 lchip, uint16 lport, uint32* p_ignore_en)
{
    uint32 step             = 0;
    uint32 tbl_id           = 0;
    uint32 fld_id           = 0;
    uint32 cmd              = 0;
    uint32 internal_mac_idx = 0;
    uint32 index            = 0;
    uint32 value            = 0;
    SharedMii0Cfg_m         mii_cfg;
    McMacMiiTxCfg_m         mii_tx_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));

    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        index = DRV_INS(port_attr->txqm_id, 0);

        internal_mac_idx = port_attr->internal_mac_idx;
        tbl_id = McMacMiiTxCfg_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_tx_cfg));
        step = McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxIgnoreLocalFault_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreLocalFault_f;
        fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIgnoreLocalFault_f + step*internal_mac_idx;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &mii_tx_cfg);
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        step = SharedMii1Cfg_t - SharedMii0Cfg_t;
        tbl_id = SharedMii0Cfg_t + step * (port_attr->mii_idx);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, cmd, &mii_cfg);
        DRV_IOR_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiIgnoreLocalFault0_f,  &value, &mii_cfg);
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid lport %u! port_type %u\n", lport, port_attr->port_type);
        return CTC_E_INVALID_PARAM;
    }
    SYS_USW_VALID_PTR_WRITE(p_ignore_en, (uint32)(value == 1 ? TRUE : FALSE));

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_ignore_fault_cfg(uint8 lchip, uint16 lport, uint32* p_value)
{

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_ignore_fault_cfg(lchip, lport, p_value));
    MAC_UNLOCK;
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_wait_mii_rx_up(uint8 lchip, uint16 lport, uint8 is_cpumac)
{
    uint32 is_up = 0;
    uint32 times = 10000;

    while(--times)
    {
        if(is_cpumac)
        {
            (void)_sys_tmm_cpumac_get_link_up(lchip, lport, &is_up, 0);
        }
        else
        {
            (void)_sys_tmm_mac_get_mii_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK, lport, &is_up, 0);
        }
        if(is_up)
        {
            return CTC_E_NONE;
        }
    }
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "%% RX MII is down! lport %u\n", lport);
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_sgmii_hata_reset_toggle(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr)
{
    uint32 tbl_id               = 0;
    uint32 fld_id               = 0;
    uint32 cmd                  = 0;
    uint32 index                = 0;
    uint32 is_pcs_x16           = 0;
    uint32 pcs_x8_x16_index     = 0;
    uint32 array32[2]           = {0};
    uint32 unidir               = 0;
    uint32 pardet               = 0;
    uint32 cl37en               = 0;
    uint32 intr_stat            = 0;
    McPcsX16LanesResetCtl_m     pcs_x16_rst;
    McPcsX16LanesSgmiiReset_m   sgmii_x16_rst;
    McPcsX8LanesResetCtl_m      pcs_x8_rst;

    /*1. check return*/
    SYS_CONDITION_RETURN(FALSE == g_hata_sgmii_en, CTC_E_NONE);
    CTC_ERROR_RETURN(_sys_tmm_mac_get_cl37_en(lchip, lport, &cl37en));

    /*2. enable unidirection & parallel detect*/
    if(cl37en)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_get_unidir_en(lchip, lport, &unidir));
        if(0 == unidir)
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_set_nw_sgmii_unidir_en(lchip, port_attr, 1));
        }
        CTC_ERROR_RETURN(_sys_tmm_mac_sgmii_get_parallel_detect_en(lchip, lport, &pardet));
        if(0 == pardet)
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_nw_sgmii_set_parallel_detect_en(lchip, port_attr, 1));
        }
    }

    /*disable interrupt*/
    CTC_ERROR_RETURN(_sys_tmm_mac_get_link_intr(lchip, lport, &intr_stat));
    if(0 != intr_stat)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_set_link_intr(lchip, lport, FALSE));
    }

    /*3. do reset toggle*/
    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
    index = DRV_INS(pcs_x8_x16_index, 0);

    if(is_pcs_x16)
    {
        /*McPcsX16LanesSgmiiReset_cfgSgmiiPcsRxSoftRst_f set 1*/
        tbl_id = McPcsX16LanesSgmiiReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_x16_rst));
        fld_id = McPcsX16LanesSgmiiReset_cfgSgmiiPcsRxSoftRst_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &sgmii_x16_rst);
        array32[0] |= (1 << (port_attr->pcs_idx % 16)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &sgmii_x16_rst, pcs_x8_x16_index, 0);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_x16_rst));

        /*McHataSoftResetCfg_cfgMcHataRxSoftReset_f set 1*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 1));

        /*McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f set 1*/
        tbl_id = McPcsX16LanesResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_rst));
        fld_id = McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x16_rst);
        array32[0] |= (1 << (port_attr->pcs_idx % 16));
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x16_rst, pcs_x8_x16_index, 0);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_rst));

        /*McPcsX16LanesSgmiiReset_cfgSgmiiPcsRxSoftRst_f set 0*/
        tbl_id = McPcsX16LanesSgmiiReset_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_x16_rst));
        fld_id = McPcsX16LanesSgmiiReset_cfgSgmiiPcsRxSoftRst_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &sgmii_x16_rst);
        array32[0] &= ~(1 << (port_attr->pcs_idx % 16)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &sgmii_x16_rst, pcs_x8_x16_index, 0);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &sgmii_x16_rst));

        /*McHataSoftResetCfg_cfgMcHataRxSoftReset_f set 0*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 0));

        /*McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f set 0*/
        tbl_id = McPcsX16LanesResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_rst));
        fld_id = McPcsX16LanesResetCtl_cfgRxSoftRstChanBmp_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x16_rst);
        array32[0] &= ~(1 << (port_attr->pcs_idx % 16));
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x16_rst, pcs_x8_x16_index, 0);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x16_rst));
    }
    else
    {
        /*McPcsX8LanesResetCtl_cfgSgmiiPcsRxSoftRst_f set 1*/
        tbl_id = McPcsX8LanesResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));
        fld_id = McPcsX8LanesResetCtl_cfgSgmiiPcsRxSoftRst_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst);
        array32[0] |= (1 << (port_attr->pcs_idx % 8)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst, pcs_x8_x16_index, 0);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));

        /*McHataSoftResetCfg_cfgMcHataRxSoftReset_f set 1*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 1));

        /*McPcsX8LanesResetCtl_cfgRxSoftRstChanBmp_f set 1*/
        index = DRV_INS(pcs_x8_x16_index, 0);
        tbl_id = McPcsX8LanesResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));
        fld_id = McPcsX8LanesResetCtl_cfgRxSoftRstChanBmp_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst);
        array32[0] |= (1 << (port_attr->pcs_idx % 8)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst, pcs_x8_x16_index, 0);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));

        /*McPcsX8LanesResetCtl_cfgSgmiiPcsRxSoftRst_f set 0*/
        tbl_id = McPcsX8LanesResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));
        fld_id = McPcsX8LanesResetCtl_cfgSgmiiPcsRxSoftRst_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst);
        array32[0] &= ~(1 << (port_attr->pcs_idx % 8)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst, pcs_x8_x16_index, 0);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));

        /*McHataSoftResetCfg_cfgMcHataRxSoftReset_f set 0*/
        CTC_ERROR_RETURN(_sys_tmm_mac_set_hata_rst(lchip, port_attr, SYS_DATAPATH_SERDES_DIR_RX, 0));

        /*McPcsX8LanesResetCtl_cfgRxSoftRstChanBmp_f set 0*/
        tbl_id = McPcsX8LanesResetCtl_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));
        fld_id = McPcsX8LanesResetCtl_cfgRxSoftRstChanBmp_f;
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst);
        array32[0] &= ~(1 << (port_attr->pcs_idx % 8)) ;
        DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &array32[0], &pcs_x8_rst, pcs_x8_x16_index, 0);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &pcs_x8_rst));
    }

    /*4. wait link up*/
    CTC_ERROR_RETURN(_sys_tmm_mac_wait_mii_rx_up(lchip, lport, FALSE));

    if(0 != intr_stat)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_link_intr(lchip, lport, TRUE));
    }

    /*5. recover parallel detect*/
    /*unidirection recover moved to link down intr*/
    if(cl37en)
    {
        if(0 == pardet)
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_nw_sgmii_set_parallel_detect_en(lchip, port_attr, 0));
        }
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_pcs_link_fault_reset(uint8 lchip, uint16 lport)
{
    uint32 intr_stat    = 0;
    uint32 ignore_fault = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));

    if ((port_attr->port_type != SYS_DMPS_NETWORK_PORT) && (port_attr->port_type != SYS_DMPS_INACTIVE_NETWORK_PORT) && (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type)))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PARAM;
    }

    MAC_LOCK;

    if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
    {
        if((SYS_GET_CHIP_VERSION != SYS_CHIP_SUB_VERSION_A) && (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type)))
        {
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_sgmii_hata_reset_toggle(lchip, lport, port_attr));
        }
    }

    if(!SYS_MAC_IS_MULTI_LANE_MODE(port_attr->pcs_mode))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_rx_en(lchip, port_attr->mac_id, 1));
        if (2 == port_attr->client_bind_num)
        {
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_rx_en(lchip, port_attr->mac_id_aps, 1));
        }
        MAC_UNLOCK;
        return CTC_E_NONE;
    }

    /*1. disable interrupt*/
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_intr(lchip, lport, &intr_stat));
    if(0 != intr_stat)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_link_intr(lchip, lport, FALSE));
    }

    if (port_attr->port_type != SYS_DMPS_INACTIVE_NETWORK_PORT)
    {
        /*2. ignore fault: local fault, remote fault, link fault*/
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_ignore_fault_cfg(lchip, lport, &ignore_fault));
        if(!ignore_fault)
        {
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_ignore_fault_cfg(lchip, lport, TRUE));
        }
    }

    /*3. do pcs rx reset*/
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_pcs_rx_rst(lchip, lport, 1));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_wait_rx_buf_empty(lchip, port_attr->mac_id));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_pcs_rx_rst(lchip, lport, 0));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_wait_mii_rx_up(lchip, lport, SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type)));
    
    /*3.1 set mac rx pkt en*/
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_rx_en(lchip, port_attr->mac_id, 1));
    if (2 == port_attr->client_bind_num)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_rx_en(lchip, port_attr->mac_id_aps, 1));
    }

    if (port_attr->port_type != SYS_DMPS_INACTIVE_NETWORK_PORT)
    {
        /*4. care fault*/
        if(!ignore_fault)
        {
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_ignore_fault_cfg(lchip, lport, FALSE));
        }
    }

    /*5. enable interrupt after operation*/
    if(0 != intr_stat)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_link_intr(lchip, lport, TRUE));
    }

    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_mac_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 is_bind_flexe_group = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        MAC_UNLOCK;
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_flexe_check_serdes_bind_group(lchip, port_attr->multi_serdes_id[0], &is_bind_flexe_group));
    if (is_bind_flexe_group)
    {
        MAC_UNLOCK;
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% SerDes %d is bind to flexe group, cannot set mac en! \n", port_attr->multi_serdes_id[0]);
        return CTC_E_INVALID_CONFIG;
    }

    /* if mac already is enabled, no need to do enable again */
    if ((!sys_usw_chip_get_reset_hw_en(lchip)) && ((p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en && enable)
        || (!(p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en) && !enable)))
    {
        MAC_UNLOCK;
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, enable));

    /*Do ANLT restart after mac enable*/
    if((enable) && (p_usw_mac_master[lchip]->mac_prop[lport].cl73_enable) && (CTC_PORT_IF_FLEXE != port_attr->interface_type))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_cl73_auto_neg_en(lchip, lport, FALSE, TRUE));
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_cl73_auto_neg_en(lchip, lport, TRUE, TRUE));
    }

    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_fec_en(uint8 lchip, uint16 lport, uint32 value)
{
    uint8 pam4_or_nrz = 0;
    uint8 ovclk_speed = 0;
    uint8 physical_serdes_id = 0;
    uint32 curr_fec_en = 0;
    uint32 is_bind_flexe_group           = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "lport:%u, fec type:%d\n", lport, value);

    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "[FEC] %s @ %d, port %d SET FEC type %d (3-Rs528, 4-Rs544) start\n", __FUNCTION__, __LINE__, lport, value);

    if(value >= CTC_PORT_FEC_TYPE_MAX)
    {
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    CTC_ERROR_RETURN(_sys_tmm_mac_get_fec_en(lchip, lport, &curr_fec_en));
    if (curr_fec_en == value)
    {
        /* same config, do nothing */
        return CTC_E_NONE;
    }

    /* get info from gport */
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }
    if(CTC_CHIP_MAX_SERDES_MODE <= port_attr->pcs_mode)
    {
        MAC_UNLOCK;
        return CTC_E_INVALID_PARAM;
    }
    physical_serdes_id = port_attr->multi_serdes_id[0];
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_get_glb_info(lchip, physical_serdes_id, SYS_TMM_SERDES_GLB_MD_MODE, &pam4_or_nrz));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_get_glb_info(lchip, physical_serdes_id, SYS_TMM_SERDES_GLB_OVCLK_SPEED, &ovclk_speed));


    if((CTC_PORT_FEC_TYPE_RS544 == value) && (SYS_TMM_SERDES_NRZ_MODE == pam4_or_nrz) &&
                                (ovclk_speed && (CTC_CHIP_SERDES_OCS_MODE_20_625G != ovclk_speed)))
    {   
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% It's not support NRZ FEC544, while configure overclocking-speed.\n");
        MAC_UNLOCK;
        return CTC_E_PARAM_CONFLICT;
    }
    
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_flexe_check_serdes_bind_group(lchip, port_attr->multi_serdes_id[0], &is_bind_flexe_group));
    if (is_bind_flexe_group)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% SerDes %d is bind to flexe group, cannot run fec config ! \n", port_attr->multi_serdes_id[0]);
        MAC_UNLOCK;
        return CTC_E_PARAM_CONFLICT;
    }

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_fec_en(lchip, lport, port_attr->pcs_mode, value));

    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "[FEC] %s @ %d, port %d SET FEC type %d (3-Rs528, 4-Rs544) end\n", __FUNCTION__, __LINE__, lport, value);

    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_link_up(uint8 lchip, uint16 lport, uint32* p_is_up, uint32 is_port)
{
    uint8  match = 0;
    uint8  active_rx_slot = 0;
    uint32 unidir_en = 0;
    uint32 remote_link = 1;
    uint32 cl37_auto_neg_en = 0;
    uint32 cl37_auto_neg_mode = 0;
    int32 ret = CTC_E_NONE;
    sys_datapath_lport_attr_t* port_attr = NULL;
    sys_flexe_client_t *client_node = NULL;

    CTC_PTR_VALID_CHECK(p_is_up);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        return _sys_tmm_cpumac_get_link_up(lchip, lport, p_is_up, is_port);
    }

    if (SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type)
    {
        return _sys_tmm_mac_get_pcs_link_status(lchip, lport, p_is_up);
    }

    if(SYS_DMPS_NETWORK_PORT != port_attr->port_type)
    {
        *p_is_up = FALSE;
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }

    if (CTC_PORT_IF_FLEXE == port_attr->interface_type)
    {
        _sys_tmm_flexe_client_lookup_by_mac(lchip, port_attr->mac_id, &client_node);
        if (!client_node)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d not belong to any client \n", port_attr->mac_id);
            return CTC_E_INVALID_PORT;
        }
        ret = _sys_tmm_flexe_get_client_slot_cnt(lchip, client_node, SYS_FLEXE_DIR_RX, SYS_FLEXE_ACTIVE_FLAG, &active_rx_slot);
        if ((0 != ret) || !active_rx_slot)
        {
            *p_is_up = FALSE;
            return CTC_E_NONE;
        }
    }

    CTC_ERROR_RETURN(_sys_tmm_mac_get_cl37_en(lchip, lport, &cl37_auto_neg_en));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_cl37_mode(lchip, lport, &cl37_auto_neg_mode));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_unidir_en(lchip, lport, &unidir_en));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_mii_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK, lport, p_is_up, unidir_en));
    if (is_port && cl37_auto_neg_en)
    {
        CTC_ERROR_RETURN(_sys_usw_mac_get_cl37_an_remote_status(lchip, lport, cl37_auto_neg_mode, NULL, &remote_link));
        if (FALSE == remote_link)
        {
            *p_is_up = FALSE;
        }
    }

    if (CTC_PORT_IF_FLEXE == port_attr->interface_type)
    {
        ret = sys_tmm_flexe_check_client_match(lchip, client_node, &match);
        if ((0 != ret) || !match)
        {
            *p_is_up = FALSE;
            return CTC_E_NONE;
        }        
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_link_up(uint8 lchip, uint16 lport, uint32* p_is_up, uint32 is_port)
{
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    if (is_port && (CTC_E_NONE == sys_usw_phy_get_phy_register_exist(lchip, lport)))
    {
        CTC_ERROR_RETURN(sys_usw_phy_get_phy_property(lchip, lport, CTC_PORT_PROP_LINK_UP, (void*)p_is_up));
        return CTC_E_NONE;
    }

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_up(lchip, lport, p_is_up, is_port));
    p_usw_mac_master[lchip]->mac_prop[lport].link_status = (*p_is_up)?1:0;
    MAC_UNLOCK;

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_get_sgmii_link_status(uint8 lchip, uint8 type, uint16 lport, uint32* p_value, uint32 unidir_en)
{
    uint8  step    = 0;
    uint8  mii_idx = 0;
    uint8  pcs_idx = 0;
    uint32 cmd     = 0;
    uint32 tb_id   = 0;
    uint32 value   = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }

    mii_idx = port_attr->mii_idx;
    pcs_idx = port_attr->pcs_idx;

    /*need not read dbgMiiRxFaultType0 when port less than 10G*/
    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
    {
        step  = SharedMii1Status_t - SharedMii0Status_t;
        tb_id = SharedMii0Status_t + mii_idx*step;

        cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxLinkStatus0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        *p_value = (value)?TRUE:FALSE;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
    {
        step  = SharedPcsSgmii1Status_t - SharedPcsSgmii0Status_t;
        tb_id = SharedPcsSgmii0Status_t + pcs_idx*step;
        /* read 3 times */
        cmd = DRV_IOR(tb_id, SharedPcsSgmii0Status_codeErrCnt0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        *p_value = value;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK_RAW)
    {
        step  = SharedMii1Status_t - SharedMii0Status_t;
        tb_id = SharedMii0Status_t + mii_idx*step;

        cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxLinkStatusRaw0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

        *p_value = (value)?TRUE:FALSE;
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_get_xfi_xxvg_link_status(uint8 lchip, uint8 type, uint16 lport, uint32* p_value, uint32 unidir_en)
{
    uint8  step     = 0;
    uint8  mii_idx  = 0;
    uint8  pcs_idx  = 0;
    uint32 cmd      = 0;
    uint32 tb_id    = 0;
    uint32 value[2] = {0};
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }

    mii_idx = port_attr->mii_idx;
    pcs_idx = port_attr->pcs_idx;

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
    {
        step  = SharedMii1Status_t - SharedMii0Status_t;
        tb_id = SharedMii0Status_t + mii_idx*step;

        cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxLinkStatus0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));

        if (unidir_en)
        {
            *p_value = value[0]?TRUE:FALSE;
        }
        else
        {
            /*check link fault state*/
            cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxFaultType0_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[1]));
            *p_value = (value[0])?(value[1]?FALSE:TRUE):FALSE;
        }
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
    {
        step  = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
        tb_id = SharedPcsXfi0Status_t + pcs_idx*step;
        cmd = DRV_IOR(tb_id, SharedPcsXfi0Status_badBerCnt0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));
        cmd = DRV_IOR(tb_id, SharedPcsXfi0Status_hiBer0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));

        *p_value = value[0];
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK_RAW)
    {
        step  = SharedMii1Status_t - SharedMii0Status_t;
        tb_id = SharedMii0Status_t + mii_idx*step;

        cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxLinkStatusRaw0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));

        *p_value = (value[0])?TRUE:FALSE;
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_get_xlg_link_status(uint8 lchip, uint8 type, uint16 lport, uint32* p_value, uint32 unidir_en)
{
    uint32 cmd          = 0;
    uint32 tb_id        = 0;
    uint32 value[4]     = {0};
    uint32 value_sub[4] = {0};
    sys_datapath_lport_attr_t* port_attr = NULL;
    SharedPcsXlgStatus0_m xlg_status;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
    {
        tb_id = SharedMii0Status_t;

        cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxLinkStatus0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));

        if (unidir_en)
        {
            *p_value = value[0]?TRUE:FALSE;
        }
        else
        {
            /*check link fault state*/
            cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxFaultType0_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[1]));
            *p_value = (value[0])?(value[1]?FALSE:TRUE):FALSE;
        }
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
    {
        sal_memset(&xlg_status, 0, sizeof(SharedPcsXlgStatus0_m));

        tb_id = SharedPcsXlgStatus_t;
         /*tb_id_sub = SharedPcsXfi0Status0_t + pcs_idx;*/

        cmd = DRV_IOR(tb_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &xlg_status));

        DRV_IOR_FIELD(lchip, tb_id, SharedPcsXlgStatus_bipErrCnt0_f, &value[0], &xlg_status);
        DRV_IOR_FIELD(lchip, tb_id, SharedPcsXlgStatus_bipErrCnt1_f, &value[1], &xlg_status);
        DRV_IOR_FIELD(lchip, tb_id, SharedPcsXlgStatus_bipErrCnt2_f, &value[2], &xlg_status);
        DRV_IOR_FIELD(lchip, tb_id, SharedPcsXlgStatus_bipErrCnt3_f, &value[3], &xlg_status);

         /*cmd = DRV_IOR(tb_id_sub, SharedPcsXfi0Status_errBlockCnt0_f);*/
         /*CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value_sub[0]));*/
         /*cmd = DRV_IOR(tb_id_sub+step, SharedPcsXfi0Status_errBlockCnt0_f);*/
         /*CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value_sub[1]));*/
         /*cmd = DRV_IOR(tb_id_sub+step*2, SharedPcsXfi0Status_errBlockCnt0_f);*/
         /*CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value_sub[2]));*/
         /*cmd = DRV_IOR(tb_id_sub+step*3, SharedPcsXfi0Status_errBlockCnt0_f);*/
         /*CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value_sub[3]));*/

        *p_value = (value[0]+value[1]+value[2]+value[3]+value_sub[0]+value_sub[1]+ value_sub[2]+value_sub[3]);
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK_RAW)
    {
        tb_id = SharedMii0Status_t;

        cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxLinkStatusRaw0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));

        *p_value = (value[0])?TRUE:FALSE;
    }

    return CTC_E_NONE;
}


STATIC int32
_sys_tmm_cpumac_get_lg_link_status(uint8 lchip, uint8 type, uint16 lport, uint32* p_value, uint32 unidir_en)
{
    uint8  step         = 0;
    uint8  mii_idx      = 0;
    uint8  pcs_idx      = 0;
    uint32 cmd          = 0;
    uint32 tb_id        = 0;
    uint32 tb_id_sub    = 0;
    uint32 field_id     = 0;
    uint32 value[4]     = {0};
    uint32 value_sub[4] = {0};
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;

    }
    mii_idx = port_attr->mii_idx;
    pcs_idx = port_attr->pcs_idx;

    if((pcs_idx != 0) && (pcs_idx != 2))
    {
        return CTC_E_INVALID_PARAM;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
    {
        step  = SharedMii1Status_t - SharedMii0Status_t;
        tb_id = SharedMii0Status_t + mii_idx*step;

        cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxLinkStatus0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));

        if (unidir_en)
        {
            *p_value = value[0]?TRUE:FALSE;
        }
        else
        {
            /*check link fault state*/
            cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxFaultType0_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[1]));
            *p_value = (value[0])?(value[1]?FALSE:TRUE):FALSE;
        }
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
    {
        /*First Lg use xlg status, second Lg use lg status*/
        if (pcs_idx == 0)
        {
            tb_id    = SharedPcsXlgStatus_t;
            field_id = SharedPcsXlgStatus_bipErrCnt0_f;
        }
        else
        {
            tb_id    = SharedPcsLgStatus_t;
            field_id = SharedPcsLgStatus_lgPcs1BipErrCnt0_f;
        }
        step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
        tb_id_sub = SharedPcsXfi0Status_t + pcs_idx;
        cmd = DRV_IOR(tb_id, field_id);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));
        cmd = DRV_IOR(tb_id_sub, SharedPcsXfi0Status_errBlockCnt0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value_sub[0]));

        cmd = DRV_IOR(tb_id, field_id+1);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[1]));
        cmd = DRV_IOR(tb_id_sub+step, SharedPcsXfi0Status_errBlockCnt0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value_sub[1]));

        cmd = DRV_IOR(tb_id, field_id+2);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[2]));
        cmd = DRV_IOR(tb_id_sub+step*2, SharedPcsXfi0Status_errBlockCnt0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value_sub[2]));

        cmd = DRV_IOR(tb_id, field_id+3);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[3]));
        cmd = DRV_IOR(tb_id_sub+step*3, SharedPcsXfi0Status_errBlockCnt0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value_sub[3]));

        *p_value = (value[0]+value[1]+value[2]+value[3]+value_sub[0]+value_sub[1]+ value_sub[2]+value_sub[3]);
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK_RAW)
    {
        step  = SharedMii1Status_t - SharedMii0Status_t;
        tb_id = SharedMii0Status_t + mii_idx*step;

        cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxLinkStatusRaw0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));

        *p_value = (value[0])?TRUE:FALSE;
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_cpumac_get_cg_link_status(uint8 lchip, uint8 type, uint16 lport, uint32* p_value, uint32 unidir_en)
{
    uint8  step     = 0;
    uint32 cmd      = 0;
    uint32 tb_id    = 0;
    uint32 value[4] = {0};
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK)
    {
        tb_id = SharedMii0Status_t;
        cmd   = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxLinkStatus0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));

        if (unidir_en)
        {
            *p_value = value[0]?TRUE:FALSE;
        }
        else
        {
            /*check link fault state*/
            cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxFaultType0_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[1]));
            *p_value = (value[0])?(value[1]?FALSE:TRUE):FALSE;
        }
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_CODE_ERR)
    {
        step  = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
        tb_id = SharedPcsXfi0Status_t;

        cmd = DRV_IOR(tb_id, SharedPcsXfi0Status_errBlockCnt0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));

        cmd = DRV_IOR(tb_id+step, SharedPcsXfi0Status_errBlockCnt0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[1]));

        cmd = DRV_IOR(tb_id+step*2, SharedPcsXfi0Status_errBlockCnt0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[2]));

        cmd = DRV_IOR(tb_id+step*3, SharedPcsXfi0Status_errBlockCnt0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[3]));

        *p_value += (value[0]+value[1]+ value[2]+value[3]);
    }

    if (type == SYS_PORT_MAC_STATUS_TYPE_LINK_RAW)
    {
        tb_id = SharedMii0Status_t;

        cmd = DRV_IOR(tb_id, SharedMii0Status_dbgMiiRxLinkStatusRaw0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value[0]));

        *p_value = (value[0])?TRUE:FALSE;
    }

    return CTC_E_NONE;
}

int32
sys_tmm_cpumac_get_lport_info_by_inner_idx(uint8 lchip, uint8 inner_idx, uint16* lport, uint8 *is_network)
{
    if(NULL != lport)
    {
        *lport = p_usw_datapath_master[lchip]->cpumac_map[inner_idx].lport;
    }

    if(NULL != is_network)
    {
        *is_network = p_usw_datapath_master[lchip]->cpumac_map[inner_idx].is_network;
    }
    
    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_get_link_up(uint8 lchip, uint16 lport, uint32* p_is_up, uint32 is_port)
{
    uint32 unidir_en     = 0;
    uint32 auto_neg_en   = 0;
    uint32 auto_neg_mode = 0;
    uint32 remote_link   = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    CTC_PTR_VALID_CHECK(p_is_up);
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }

    if(SYS_TMM_IS_MODE_NONE(port_attr->pcs_mode))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is none mode \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }

    /*CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_cpumac_get_cl37_auto_neg(lchip, lport, CTC_PORT_PROP_AUTO_NEG_EN, &auto_neg_en));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_cpumac_get_cl37_auto_neg(lchip, lport, CTC_PORT_PROP_AUTO_NEG_MODE, &auto_neg_mode));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_cpumac_get_unidir_en(lchip, lport, &unidir_en));*/

    switch (port_attr->pcs_mode)
    {
        case CTC_CHIP_SERDES_SGMII_MODE:
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_get_sgmii_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK, 
                                             lport, p_is_up, unidir_en));
            CTC_ERROR_RETURN(_sys_tmm_mac_get_cl37_en(lchip, lport, &auto_neg_en));
            if (is_port && auto_neg_en)
            {
                CTC_ERROR_RETURN(_sys_tmm_mac_get_cl37_mode(lchip, lport, &auto_neg_mode));
                CTC_ERROR_RETURN(_sys_usw_mac_get_cl37_an_remote_status(lchip, lport, auto_neg_mode, 
                                            NULL, &remote_link));
                if (FALSE == remote_link)
                {
                    *p_is_up = FALSE;
                }
            }
            break;
        case CTC_CHIP_SERDES_XXVG_MODE:
        case CTC_CHIP_SERDES_XFI_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_get_xfi_xxvg_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK, 
                                             lport, p_is_up, unidir_en));
            break;
        case CTC_CHIP_SERDES_XLG_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_get_xlg_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK, 
                                             lport, p_is_up, unidir_en));
            break;
        case CTC_CHIP_SERDES_LG_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_get_lg_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK, 
                                             lport, p_is_up, unidir_en));
            break;
        case CTC_CHIP_SERDES_CG_MODE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_get_cg_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK, 
                                             lport, p_is_up, unidir_en));
            break;
        default:
            break;
    }
    p_usw_mac_master[lchip]->mac_prop[lport].link_status = (*p_is_up)?1:0;

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_get_pcs_link_status(uint8 lchip, uint16 lport, uint32* p_is_up)
{
    uint32 cmd         = 0;
    uint32 tbl_id      = 0;
    uint32 fld_id      = 0;
    uint32 pcs_id      = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    if(!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        return CTC_E_NOT_SUPPORT;
    }

    pcs_id = port_attr->pcs_idx;
    switch(port_attr->pcs_mode)
    {
        case CTC_CHIP_SERDES_CG_MODE:
            tbl_id = SharedPcsCgStatus_t;
            fld_id = SharedPcsCgStatus_cgPcsAlignStatus_f;
            break;
        case CTC_CHIP_SERDES_LG_MODE:
            if(2 <= pcs_id)
            {
                if(CTC_PORT_FEC_TYPE_RS528 == p_usw_mac_master[lchip]->mac_prop[lport].port_fec_val)
                {
                    tbl_id = GlobalStatusSharedFec_t;
                    fld_id = GlobalStatusSharedFec_dbgSharedFecAlignStatus2_f;
                }
                else
                {
                    tbl_id = SharedPcsLgStatus_t;
                    fld_id = SharedPcsLgStatus_lgPcs1AlignStatus_f;
                }
            }
            else
            {
                if(CTC_PORT_FEC_TYPE_RS528 == p_usw_mac_master[lchip]->mac_prop[lport].port_fec_val)
                {
                    tbl_id = GlobalStatusSharedFec_t;
                    fld_id = GlobalStatusSharedFec_dbgSharedFecAlignStatus0_f;
                }
                else
                {
                    tbl_id = SharedPcsXlgStatus_t;
                    fld_id = SharedPcsXlgStatus_alignStatus0_f;
                }
            }
            break;
        case CTC_CHIP_SERDES_XLG_MODE:
            tbl_id = SharedPcsXlgStatus_t;
            fld_id = SharedPcsXlgStatus_alignStatus0_f;
            break;
        case CTC_CHIP_SERDES_XFI_MODE:
        case CTC_CHIP_SERDES_XXVG_MODE:
            tbl_id = SharedPcsXfi0Status_t + (SharedPcsXfi1Status_t - SharedPcsXfi0Status_t)*pcs_id;    
            fld_id = SharedPcsXfi0Status_xfiSyncStatus0_f;
            break;
        case CTC_CHIP_SERDES_SGMII_MODE:
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            tbl_id = SharedPcsSgmii0Status_t + (SharedPcsSgmii1Status_t - SharedPcsSgmii0Status_t)*pcs_id;    
            fld_id = SharedPcsSgmii0Status_sgmiiSyncStatus0_f;
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }

    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, p_is_up));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_pcs_link_status(uint8 lchip, uint16 lport, uint32* p_is_up)
{
    uint8 status            = 0;
    uint32 is_pcs_x16       = 0;
    uint32 pcs_x8_x16_index = 0;
    uint32 index            = 0;
    uint32 tbl_id           = 0;
    uint32 fld_id           = 0;
    uint32 cmd              = 0;
    uint32 step             = 0;
    uint32 factor           = 0;
    uint32 val32            = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    
#ifdef EMULATION_ENV
    char  speed_str[10] = {0};
    char  fec_str[20] = {0};
    char  iftype_str[20] = {0};
    uint32 fec_type = 0;    
#endif
    SYS_CONDITION_RETURN(SYS_USW_MAX_PORT_NUM_PER_CHIP <= lport, CTC_E_INVALID_PARAM);
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        CTC_ERROR_RETURN(_sys_tmm_cpumac_get_pcs_link_status(lchip, lport, p_is_up));
        return CTC_E_NONE;
    }

    if ((port_attr->port_type != SYS_DMPS_NETWORK_PORT) && (port_attr->port_type != SYS_DMPS_INACTIVE_NETWORK_PORT))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }

    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);

    index = DRV_INS(pcs_x8_x16_index, 0);
    factor = port_attr->pcs_idx % (is_pcs_x16?16:8);  /* 0..16(X16) or 0..8(X8) per txqm */
    if (is_pcs_x16)
    {
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            tbl_id = McPcsX16LanesSgmiiMon_t;
            step   = McPcsX16LanesSgmiiMon_monSgmii_1_anLinkStatus_f - McPcsX16LanesSgmiiMon_monSgmii_0_anLinkStatus_f;
            fld_id = McPcsX16LanesSgmiiMon_monSgmii_0_anLinkStatus_f + step * factor;
        }
        else if (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode)
        {
            factor = (port_attr->mac_id % SYS_TMM_MAX_MAC_NUM_PER_TXQM);
            tbl_id = McPcsX16LanesQsgmiiMon_t;
            step   = McPcsX16LanesQsgmiiMon_monQsgmiiSgmii_1_anLinkStatus_f - McPcsX16LanesQsgmiiMon_monQsgmiiSgmii_0_anLinkStatus_f;
            fld_id = McPcsX16LanesQsgmiiMon_monQsgmiiSgmii_0_anLinkStatus_f + step * factor;
        }
        else
        {
            tbl_id = McPcsX16LanesRxChanMon_t;
            step   = McPcsX16LanesRxChanMon_monRxStatusChan_1_monRxSyncStatus_f - McPcsX16LanesRxChanMon_monRxStatusChan_0_monRxSyncStatus_f;
            fld_id = McPcsX16LanesRxChanMon_monRxStatusChan_0_monRxSyncStatus_f + step * factor;
        }
    }
    else
    {
        if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
            || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            tbl_id = McPcsX8LanesSgmiiMon_t;
            step   = McPcsX8LanesSgmiiMon_monSgmii_1_anLinkStatus_f - McPcsX8LanesSgmiiMon_monSgmii_0_anLinkStatus_f;
            fld_id = McPcsX8LanesSgmiiMon_monSgmii_0_anLinkStatus_f + step * factor;
        }
        else
        {
            tbl_id = McPcsX8LanesRxChanMon_t;
            step   = McPcsX8LanesRxChanMon_monRxStatusChan_1_monRxSyncStatus_f - McPcsX8LanesRxChanMon_monRxStatusChan_0_monRxSyncStatus_f;
            fld_id = McPcsX8LanesRxChanMon_monRxStatusChan_0_monRxSyncStatus_f + step * factor;
        }
    }
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &val32));
    
#ifdef EMULATION_ENV
    GET_SPEED_STR_BY_ENUM(port_attr->speed_mode, speed_str);
    GET_IFTYPE_STR_BY_ENUM(port_attr->interface_type, iftype_str);
    _sys_tmm_mac_get_fec_en(lchip, lport, &fec_type);
    GET_FEC_STR_BY_ENUM(fec_type, fec_str);
    
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-25s:  %d\n", "DP ID", port_attr->txqm_id / 4);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-25s:  %s%s\n", "PCS mode", speed_str, fec_str);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-25s:  %s\n", "PCS type", (is_pcs_x16?"X16":"X8"));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-25s:  %d\n", "PCS lane ID", (port_attr->pcs_idx % (is_pcs_x16?16:8)));
#endif

    if ((port_attr->port_type == SYS_DMPS_INACTIVE_NETWORK_PORT) && val32)
    { 
        CTC_ERROR_RETURN(_sys_tmm_flexe_get_phy_status_by_lport(lchip, lport, port_attr, SYS_FLEXE_OH_LOCK, &status));
        if (!status)
        {
            val32 = 0;
        }
        CTC_ERROR_RETURN(_sys_tmm_flexe_get_phy_status_by_lport(lchip, lport, port_attr, SYS_FLEXE_OHMF_LOCK, &status));
        if (!status)
        {
            val32 = 0;
        }
        CTC_ERROR_RETURN(_sys_tmm_flexe_get_phy_status_by_lport(lchip, lport, port_attr, SYS_FLEXE_PAD_LOCK, &status));
        if (!status)
        {
            val32 = 0;
        }
        CTC_ERROR_RETURN(_sys_tmm_flexe_get_phy_status_by_lport(lchip, lport, port_attr, SYS_FLEXE_RPF_CLEAR, &status));
        if (!status)
        {
            val32 = 0;
        }
    }

    SYS_USW_VALID_PTR_WRITE(p_is_up, val32);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_link_up_raw(uint8 lchip, uint16 lport, uint32* p_value)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_get_mii_link_status_raw(lchip, lport, p_value));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        switch (port_attr->pcs_mode)
        {
            case CTC_CHIP_SERDES_SGMII_MODE:
            case CTC_CHIP_SERDES_2DOT5G_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_get_sgmii_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK_RAW, lport, p_value, 0));
                break;
            case CTC_CHIP_SERDES_XXVG_MODE:
            case CTC_CHIP_SERDES_XFI_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_get_xfi_xxvg_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK_RAW, lport, p_value, 0));
                break;
            case CTC_CHIP_SERDES_XLG_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_get_xlg_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK_RAW, lport, p_value, 0));
                break;
            case CTC_CHIP_SERDES_LG_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_get_lg_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK_RAW, lport, p_value, 0));
                break;
            case CTC_CHIP_SERDES_CG_MODE:
                CTC_ERROR_RETURN(_sys_tmm_cpumac_get_cg_link_status(lchip, SYS_PORT_MAC_STATUS_TYPE_LINK_RAW, lport, p_value, 0));
                break;
            default:
                SYS_USW_VALID_PTR_WRITE(p_value, FALSE);
                break;
        }
    }

    return CTC_E_NONE;
}

int32
sys_tmm_dynamic_switch_port_id_normalize(uint8 lchip, uint16 lport, uint8 mode, uint16* p_lport_nml)
{
    uint8  logical_serdes_id;
    uint8  logical_serdes_id_nml;
    uint8  lane_num;
    uint8  hss_type = SYS_DATAPATH_HSS_TYPE_15G;
    sys_datapath_lport_attr_t* port_attr = NULL;
    sys_datapath_serdes_info_t* p_serdes = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        return CTC_E_NOT_SUPPORT;
    }
    
    CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, port_attr->multi_serdes_id[0], &logical_serdes_id));
    SYS_CONDITION_RETURN((SYS_TMM_USELESS_ID8 == logical_serdes_id), CTC_E_INVALID_PARAM);

    SYS_TMM_GET_HSS_TYPE(SYS_TMM_MAP_SERDES_TO_HSS_IDX(logical_serdes_id), hss_type);
    if((CTC_CHIP_SERDES_CG_R2_MODE == mode) && (SYS_DATAPATH_HSS_TYPE_15G == hss_type))
    {
        lane_num = 4;
    }
    else
    {
        SYS_TMM_GET_LANE_NUM_BY_MODE(mode, lane_num);
    }

    logical_serdes_id_nml = logical_serdes_id / lane_num * lane_num;

    CTC_ERROR_RETURN(sys_usw_datapath_get_serdes_info(lchip, logical_serdes_id_nml, &p_serdes));

    *p_lport_nml = p_serdes->lport;

    return CTC_E_NONE;
}

/*get influenced serdes & port in all quad lane, from any mode to none*/
int32
sys_tmm_mac_dynamic_switch_get_info_quad_none(uint8 lchip, uint8 logic_serdes_id, 
                                                             sys_tmm_ds_target_attr_t *target)
{
    uint8  hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logic_serdes_id);
    uint8  lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logic_serdes_id);
    uint8  quad_lane_base = lane_id / 4 * 4;
    uint8  quad_lane_idx;
    uint8  idx_s       = 0;
    uint8  idx_l       = 0;
    uint8  idx_t       = 0;
    uint8  lane_id_tmp = 0;
    uint8  mode_tmp;
    uint8  qsgmii_idx;
    uint16 lport_tmp;
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;

    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    SYS_CONDITION_RETURN(p_hss_vec == NULL, CTC_E_NONE);
    for(quad_lane_idx = 0; quad_lane_idx < 4; quad_lane_idx++)
    {
        lane_id_tmp = quad_lane_base+quad_lane_idx;
        mode_tmp = p_hss_vec->serdes_info[lane_id_tmp].mode;
        SYS_CONDITION_CONTINUE(CTC_CHIP_SERDES_NONE_MODE == mode_tmp);

        /*add serdes change info*/
        idx_s = target->serdes_num;
        target->serdes_list[idx_s].logic_serdes_id = SYS_TMM_GET_SERDES_ID_BY_LANE(hss_id, lane_id_tmp);
        target->serdes_list[idx_s].src_mode = mode_tmp;
        target->serdes_list[idx_s].dst_mode = CTC_CHIP_SERDES_NONE_MODE;
        (target->serdes_num)++;

        /*add lport change info*/
        for(qsgmii_idx = 0; qsgmii_idx < 4; qsgmii_idx++)
        {
            if(0 == p_hss_vec->serdes_info[lane_id_tmp].pcs_l_id)
            {
                idx_l = target->lport_num;
                lport_tmp = p_hss_vec->serdes_info[lane_id_tmp].lport + qsgmii_idx;
                target->lport_list[idx_l].lport = lport_tmp;
                target->lport_list[idx_l].chan_id = p_hss_vec->serdes_info[lane_id_tmp].chan_id + qsgmii_idx;
                target->lport_list[idx_l].upt_flag = SYS_DS_LPORT_DROP;
                (target->lport_num)++;
            }
            idx_t = target->lport_list[idx_l].serdes_relate_num;
            target->lport_list[idx_l].serdes_relate[idx_t].serdes_list_idx = idx_s;
            target->lport_list[idx_l].serdes_relate[idx_t].relate_flag = SYS_DS_LPORT_SERDES_OLD;
            (target->lport_list[idx_l].serdes_relate_num)++;

            SYS_CONDITION_BREAK(CTC_CHIP_SERDES_QSGMII_MODE != mode_tmp);
        }
        
        /*add dst_lport_idx*/
        target->serdes_list[idx_s].dst_lport_idx = (CTC_CHIP_SERDES_QSGMII_MODE == mode_tmp) ? (idx_l-3) : idx_l;
    }

    return CTC_E_NONE;
}

/*get influenced serdes & port in all quad lane, from none to destination mode*/
int32
sys_tmm_mac_dynamic_switch_get_info_quad_dst(uint8 lchip, uint8 logic_serdes_id, uint8 dst_mode,
                                                             sys_tmm_ds_target_attr_t *target, uint16 overclocking_speed)
{
    uint8  quad_lane_base = logic_serdes_id / 4 * 4;
    uint8  quad_lane_idx;
    uint8  idx_s       = 0;
    uint8  idx_l       = 0;
    uint8  idx_t       = 0;
    uint8  lane_num;
    uint16 lport_tmp;
    uint8  chan_tmp;
    uint8  logic_serdes_tmp;
    uint8  qsgmii_idx;
    uint8  ratio;
    uint8  physic_serdes = SYS_TMM_USELESS_ID8;

    SYS_TMM_GET_LANE_NUM_BY_MODE(dst_mode, lane_num);

    SYS_TMM_GET_PORT_SERDES_RATIO_BY_MODE(dst_mode, ratio);

    for(quad_lane_idx = 0; quad_lane_idx < 4; quad_lane_idx++)
    {
        /*for modes not port 1 serdes 4, only index 0 & 2 are influenced, and 1 & 3 are skipped*/
        if((PORT_1_SERDES_1 == ratio) || (PORT_4_SERDES_1 == ratio))
        {
            SYS_CONDITION_CONTINUE((1 == quad_lane_idx) || (3 == quad_lane_idx));
        }

        logic_serdes_tmp = quad_lane_base+quad_lane_idx;

        /*for 4*none -> 50GR2, if current lane is 0/2 (physic serdes always exist), check 1/3 valid, then add to target*/
        /*none mode has 2 probability, physic serdes exist (none/none -> 1*50GR2) or no physic serdes (none/invalid -> nothing).*/
        if(PORT_1_SERDES_2 == ratio)
        {
            if(0 == quad_lane_idx % 2)
            {
                (void)_sys_usw_datapath_get_physical_serdes_id_by_logical(lchip, logic_serdes_tmp+1, &physic_serdes);
                if(SYS_TMM_USELESS_ID8 == physic_serdes)
                {
                    quad_lane_idx++;
                    continue;
                }
            }
        }

        /*add serdes change info (excluding dst_lport_idx)*/
        idx_s = target->serdes_num;
        target->serdes_list[idx_s].logic_serdes_id = logic_serdes_tmp;
        target->serdes_list[idx_s].src_mode = CTC_CHIP_SERDES_NONE_MODE;
        target->serdes_list[idx_s].dst_mode = dst_mode;
        (target->serdes_num)++;

        /*add lport change info*/
        for(qsgmii_idx = 0; qsgmii_idx < 4; qsgmii_idx++)
        {
            if(0 == quad_lane_idx % lane_num)
            {
                idx_l = target->lport_num;
                SYS_CONDITION_CONTINUE(sys_tmm_get_lport_chan_map(lchip, logic_serdes_tmp, &chan_tmp, &lport_tmp));
                target->lport_list[idx_l].lport = lport_tmp + qsgmii_idx;
                target->lport_list[idx_l].chan_id = chan_tmp + qsgmii_idx;
                target->lport_list[idx_l].upt_flag = SYS_DS_LPORT_ADD;
                (target->lport_num)++;
            }
            idx_t = target->lport_list[idx_l].serdes_relate_num;
            target->lport_list[idx_l].serdes_relate[idx_t].serdes_list_idx = idx_s;
            target->lport_list[idx_l].serdes_relate[idx_t].relate_flag = SYS_DS_LPORT_SERDES_NEW;
            (target->lport_list[idx_l].serdes_relate_num)++;
            
            SYS_CONDITION_BREAK(CTC_CHIP_SERDES_QSGMII_MODE != dst_mode);
        }

        /*add dst_lport_idx*/
        target->serdes_list[idx_s].dst_lport_idx = (CTC_CHIP_SERDES_QSGMII_MODE == dst_mode) ? (idx_l-3) : idx_l;
    }

    /*add ovclk*/
    for(idx_s = 0; idx_s < target->serdes_num; idx_s++)
    {
        target->serdes_list[idx_s].ovclk_flag = 
            ((CTC_CHIP_SERDES_OCS_MODE_NONE == overclocking_speed) && 
            SYS_TMM_MODE_IS_PAM4(target->serdes_list[idx_s].dst_mode)) ? 
            CTC_CHIP_SERDES_OCS_MODE_51_56G : overclocking_speed;
    }

    return CTC_E_NONE;
}

/*HS PAM4 switch 1 & 2 swap support, only do 100GR2 <-> other switch*/
int32
sys_tmm_mac_dynamic_switch_remap_proc(  uint8 lchip, uint8 dst_mode,
                                                  uint8 logic_serdes_id, uint16 overclocking_speed)
{
    uint8 logic_serdes_id_tmp = logic_serdes_id;
    uint8 logic_id_base       = logic_serdes_id / 4 * 4;
    sys_tmm_ds_target_attr_t   target    = {0};

    /*1. switch all 4 lane to none*/
    CTC_ERROR_RETURN(sys_tmm_mac_dynamic_switch_get_info_quad_none(lchip, logic_serdes_id, &target));
    CTC_ERROR_RETURN(_sys_tmm_mac_set_interface_mode(lchip, dst_mode, &target));
    
    /*2. do logic 1 & 2 swap*/
    sys_tmm_dynamic_switch_logic_1_2_swap(lchip, logic_serdes_id_tmp);

    SYS_CONDITION_RETURN((CTC_CHIP_SERDES_NONE_MODE == dst_mode), CTC_E_NONE);

    sal_memset(&target, 0, sizeof(sys_tmm_ds_target_attr_t));
    
    /*3. switch none -> 100GR2 or none -> dst_mode*/
    if(CTC_CHIP_SERDES_CG_R2_MODE == dst_mode)
    {
        CTC_ERROR_RETURN(_sys_tmm_datapath_dynamic_switch_get_info(lchip, logic_id_base, CTC_CHIP_SERDES_NONE_MODE, 
            dst_mode, &target, overclocking_speed));
    }
    else
    {
        CTC_ERROR_RETURN(sys_tmm_mac_dynamic_switch_get_info_quad_dst(lchip, logic_serdes_id, dst_mode, &target, 
            overclocking_speed));
    }
    
    CTC_ERROR_RETURN(_sys_tmm_mac_set_interface_mode(lchip, dst_mode, &target));

    return CTC_E_NONE;
}

int32
sys_tmm_mac_dynamic_switch_proc(uint8 lchip, uint16 lport, ctc_port_if_mode_t* if_mode)
{
    uint8  index                         = 0;
    uint8  dst_mode                      = 0;
    uint8  logic_serdes_id               = 0;
    uint8  remap_flag                    = FALSE;
    uint32 is_bind_flexe_group           = 0;
    uint8  dup_flag                      = FALSE;
    uint8  src_ovclk                     = 0;
    uint8  dst_ovclk                     = CTC_CHIP_SERDES_OCS_MODE_NONE;

    sys_tmm_ds_target_attr_t   target    = {0};
    sys_datapath_lport_attr_t* port_attr = NULL;
    
    SYS_TMM_GET_SERDES_MODE_BY_IFMODE(if_mode->speed, if_mode->interface_type, dst_mode);

    if(CTC_CHIP_SERDES_XLG_R2_MODE == dst_mode)
    {
        dst_mode = CTC_CHIP_SERDES_LG_MODE;
        dst_ovclk = CTC_CHIP_SERDES_OCS_MODE_20_625G;
    }
    
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    CTC_ERROR_RETURN(sys_tmm_serdes_get_glb_info(lchip, port_attr->multi_serdes_id[0], SYS_TMM_SERDES_GLB_OVCLK_SPEED, &src_ovclk));
    if((dst_mode == port_attr->pcs_mode) && (dst_ovclk == src_ovclk))
    {
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(sys_tmm_flexe_check_serdes_bind_group(lchip, port_attr->multi_serdes_id[0], &is_bind_flexe_group));
    if (is_bind_flexe_group)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% SerDes %d is bind to flexe group, cannot run dynamic switch ! \n", port_attr->multi_serdes_id[0]);
        return CTC_E_PARAM_CONFLICT;
    }

    CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, port_attr->multi_serdes_id[0], 
        &logic_serdes_id));
    SYS_CONDITION_RETURN((SYS_TMM_USELESS_ID8 == logic_serdes_id), CTC_E_INVALID_PARAM);

    /*HS PAM4 remap switch proc*/
    remap_flag = sys_tmm_dynamic_switch_judge_remap(lchip, logic_serdes_id, dst_mode);
    if(remap_flag)
    {
        CTC_ERROR_RETURN(sys_tmm_dynamic_switch_para_check(lchip, logic_serdes_id, dst_mode, 
            CTC_CHIP_SERDES_OCS_MODE_NONE, &dup_flag, remap_flag));
        SYS_CONDITION_RETURN(dup_flag, CTC_E_NONE);
        CTC_ERROR_RETURN(sys_tmm_mac_dynamic_switch_remap_proc(lchip, dst_mode, logic_serdes_id, CTC_CHIP_SERDES_OCS_MODE_NONE));
        return CTC_E_NONE;
    }

    if (FALSE == port_attr->an_done_opr)
    {
        CTC_ERROR_RETURN(sys_tmm_dynamic_switch_para_check(lchip, logic_serdes_id, dst_mode, 
            dst_ovclk, &dup_flag, remap_flag));
        SYS_CONDITION_RETURN(dup_flag, CTC_E_NONE);
    }

    CTC_ERROR_RETURN(_sys_tmm_datapath_dynamic_switch_get_info(lchip, logic_serdes_id, port_attr->pcs_mode, 
        dst_mode, &target, CTC_CHIP_SERDES_OCS_MODE_NONE));

    if((CTC_CHIP_SERDES_LG_MODE == dst_mode) && (CTC_CHIP_SERDES_OCS_MODE_20_625G == dst_ovclk))
    {
        for (index = 0; index < target.serdes_num; index++)
        {
            target.serdes_list[index].ovclk_flag = CTC_CHIP_SERDES_OCS_MODE_20_625G;
        }
    }
    CTC_ERROR_RETURN(_sys_tmm_mac_set_interface_mode(lchip, dst_mode, &target));
    
    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_interface_mode(uint8 lchip, uint16 lport, ctc_port_if_mode_t* if_mode)
{
    uint16 lport_nml = 0;
    uint8  mode      = 0;
    CTC_PTR_VALID_CHECK(if_mode);

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d, lport: %u, dst_mode: %d/%d\n", 
        __FUNCTION__, __LINE__, lport, if_mode->speed, if_mode->interface_type);

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    SYS_TMM_GET_SERDES_MODE_BY_IFMODE(if_mode->speed, if_mode->interface_type, mode);
    if (CTC_CHIP_MAX_SERDES_MODE == mode)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Interface speed and type not match \n");
        return CTC_E_PARAM_CONFLICT;
    }
    
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_dynamic_switch_port_id_normalize(lchip, lport, mode, &lport_nml));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport_nml, if_mode));
    MAC_UNLOCK;
    
    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_xpipe_mac_chan_id(uint8 lchip, uint16 lport, uint16* emac_id, uint8* echan_id, 
                                             uint16* pmac_id, uint8* pchan_id)
{
    sys_datapath_lport_attr_t* port_attr = NULL;
    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN(((SYS_DMPS_NETWORK_PORT != port_attr->port_type) || (CTC_PORT_XPIPE_TYPE_0 == port_attr->xpipe_en)), 
        CTC_E_NONE);

    SYS_USW_VALID_PTR_WRITE(emac_id,  port_attr->mac_id);
    SYS_USW_VALID_PTR_WRITE(echan_id, port_attr->chan_id);
    SYS_USW_VALID_PTR_WRITE(pmac_id,  port_attr->pmac_id);
    SYS_USW_VALID_PTR_WRITE(pchan_id, port_attr->pmac_chanid);
    
    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_xpipe_en(uint8 lchip, uint16 lport, uint32* p_value)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    if(SYS_DMPS_NETWORK_PORT != port_attr->port_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% lport %u is not a network port! \n", lport);
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }
    if(CTC_PORT_IF_FLEXE == port_attr->interface_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% FlexE client mac DONOT support xpipe \n");
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }
    SYS_USW_VALID_PTR_WRITE(p_value, port_attr->xpipe_en);
    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_dp_id_by_lport(uint8 lchip, uint16 lport, uint8* dp_id)
{
    uint8  dp;
    uint16 dp_chan;
    for(dp = 0; dp < SYS_TMM_DP_NUM; dp++)
    {
        for(dp_chan = 0; dp_chan < 128; dp_chan++)
        {
            if(lport == p_usw_datapath_master[lchip]->chan_2_logic_serdes[dp][dp_chan].lport)
            {
                SYS_USW_VALID_PTR_WRITE(dp_id, dp);
                return CTC_E_NONE;
            }
        }
    }
    return CTC_E_INVALID_PARAM;
}

int32
sys_tmm_mac_xpipe_soft_table_upt(uint8 lchip, uint8 xpipe_en, uint16 lport, sys_datapath_lport_attr_t* port_attr)
{
    int32   ret          = CTC_E_NONE;
    int32   ret2         = CTC_E_NONE;
    uint8   pmac_chanid  = SYS_TMM_USELESS_ID8;
    uint16  pmac_id      = SYS_TMM_USELESS_ID16;
    uint8   chan_id_tmp;
    uint8   dp_id        = 0;
    uint16  tmp_lport    = 0;
    uint8   glb_xpipe_en = FALSE;
    sys_datapath_lport_attr_t* port_attr_tmp = NULL;
    sys_datapath_lport_attr_t  port_backup = {0};
    sys_resource_manage_item_info_t *p_channel_arrange = p_usw_datapath_master[lchip]->resource_manage.channel_arrange;
    sys_resource_manage_item_info_t *p_macid_arrange   = p_usw_datapath_master[lchip]->resource_manage.macid_arrange;
    sys_tmm_ds_target_attr_t ds_attr = {0};

    SYS_CONDITION_RETURN((320 <= port_attr->mac_id), CTC_E_INVALID_PARAM);
    SYS_CONDITION_RETURN(SYS_TMM_TXQM_NUM_PER_DP*2 <= port_attr->txqm_id, CTC_E_INVALID_PARAM);

    /*1. port db backup*/
    sal_memcpy(&port_backup, port_attr, sizeof(sys_datapath_lport_attr_t));

    /*2. update port db*/
    if(xpipe_en)
    {
        /*2.1 Get new mac_id & chan_id Preamble Mac*/
        CTC_ERROR_RETURN(_sys_tmm_mac_get_dp_id_by_lport(lchip, lport, &dp_id));
        ret = sys_tmm_datapath_get_idle_chanid(lchip, SYS_ARRANGE_XPIPE_PMAC_BMP, dp_id, &pmac_chanid);
        if(CTC_E_NONE != ret)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Cannot get idle channel id for PMac! lport %u\n", lport);
            return CTC_E_NO_RESOURCE;
        }
        ret = sys_tmm_datapath_get_idle_macid(lchip, SYS_ARRANGE_XPIPE_PMAC_BMP, port_attr->txqm_id, &pmac_id);
        if(CTC_E_NONE != ret)
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Cannot get idle mac id for PMac! lport %u, txqm_id %u\n", 
                lport, port_attr->txqm_id);
            return CTC_E_NO_RESOURCE;
        }

        /*2.2 Update port_attr info of Express Mac*/
        if(320 > pmac_id)
        {
            p_channel_arrange[pmac_chanid].using_stat = SYS_RESOURCE_IN_USE;
            p_macid_arrange[pmac_id].using_stat       = SYS_RESOURCE_IN_USE;
        }

        port_attr->pmac_id     = pmac_id;
        port_attr->pmac_chanid = pmac_chanid;

        /*chan id e/p exchange*/
        chan_id_tmp = port_attr->chan_id;
        port_attr->chan_id = port_attr->pmac_chanid;
        port_attr->pmac_chanid = chan_id_tmp;
    }
    else
    {
        /*chan id e/p exchange*/
        chan_id_tmp = port_attr->chan_id;
        port_attr->chan_id = port_attr->pmac_chanid;
        port_attr->pmac_chanid = chan_id_tmp;

        /*2.1 Update port_attr info of Express Mac*/
        pmac_chanid = port_attr->pmac_chanid;
        pmac_id     = port_attr->pmac_id;
        if(320 > pmac_id)
        {
            p_channel_arrange[pmac_chanid].using_stat = SYS_RESOURCE_FREE;
            p_macid_arrange[pmac_id].using_stat       = SYS_RESOURCE_FREE;
        }

        port_attr->pmac_id     = SYS_TMM_USELESS_ID16;
        port_attr->pmac_chanid = SYS_TMM_USELESS_ID8;
    }
    port_attr->xpipe_en = xpipe_en;

    /*3. datpath resource check*/
    /*check credit: qmgr, bufretrv, epe, nettx*/
    ret = _sys_tmm_datapath_check_credit_sum(lchip, dp_id);
    CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, port_attr->multi_serdes_id[0], 
        &(ds_attr.serdes_list[0].logic_serdes_id)));
    ret2 = _sys_tmm_mac_dynamic_switch_calendar_check(lchip, SYS_CAL_CHECK_XPIPE, &ds_attr);
    if((CTC_E_NONE != ret) || (CTC_E_NONE != ret2))
    {
        /*exception handle: rollback chan & mac arrange*/
        if(320 > pmac_id)
        {
            if(xpipe_en)
            {
                p_channel_arrange[pmac_chanid].using_stat = SYS_RESOURCE_FREE;
                p_macid_arrange[pmac_id].using_stat       = SYS_RESOURCE_FREE;
            }
            else
            {
                p_channel_arrange[pmac_chanid].using_stat = SYS_RESOURCE_IN_USE;
                p_macid_arrange[pmac_id].using_stat       = SYS_RESOURCE_IN_USE;
            }
        }
        /*exception handle: rollback port db*/
        sal_memcpy(port_attr, &port_backup, sizeof(sys_datapath_lport_attr_t));
        return CTC_E_NO_RESOURCE;
    }

    /*4. Global xpipe status update*/
    for(tmp_lport = 0; tmp_lport < SYS_PHY_PORT_NUM_PER_SLICE; tmp_lport++)
    {
        port_attr_tmp = sys_usw_datapath_get_port_capability(lchip, tmp_lport);
        SYS_CONDITION_CONTINUE(NULL == port_attr_tmp);
        if(CTC_PORT_XPIPE_TYPE_0 != port_attr_tmp->xpipe_en)
        {
            glb_xpipe_en = TRUE;
            break;
        }
    }
    p_usw_datapath_master[lchip]->glb_xpipe_en = glb_xpipe_en;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_xpipe_en(uint8 lchip, uint16 lport, uint32 value)
{
    uint8   xpipe_en     = (uint8)value;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    TSINGMA_DUMP_PRINT(g_tm_dump_fp, "\n ### %s @ %d\n", __FUNCTION__, __LINE__);

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    SYS_CONDITION_RETURN(SYS_USW_MAX_PORT_NUM_PER_CHIP <= lport, CTC_E_INVALID_PARAM);

    /*1. Config validation*/
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    if(SYS_DMPS_NETWORK_PORT != port_attr->port_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% lport %u is not a network port! \n", lport);
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }
    if(CTC_PORT_IF_FLEXE == port_attr->interface_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% FlexE client mac DONOT support xpipe \n");
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }
    if(port_attr->xpipe_en == xpipe_en)
    {
        MAC_UNLOCK;
        return CTC_E_NONE;
    }

    /*2. Soft table update*/
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_xpipe_soft_table_upt(lchip, xpipe_en, lport, port_attr));

    /*3. Set datapath config*/
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_datapath_xpipe_resource_alloc(lchip, port_attr));

    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_rx_pmac_sfd_en(uint8 lchip, uint16 lport, uint32 value)
{
    uint8  txqm_id      = 0;
    uint16 txqm_emac_id = 0;
    uint32 fld_id       = 0;
    uint32 tbl_id       = 0;
    uint32 index        = 0;
    uint32 cmd          = 0;
    uint32 step         = 0;    
    sys_datapath_lport_attr_t* port_attr = NULL;
    uint32 write_st[SYS_MAC_MAX_STRUCT_WORD] = {0};

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    if(SYS_DMPS_NETWORK_PORT != port_attr->port_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% lport %u is not a network port! \n", lport);
        return CTC_E_INVALID_PORT;
    }
    if(CTC_PORT_IF_FLEXE == port_attr->interface_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% FlexE client mac DONOT support xpipe \n");
        return CTC_E_INVALID_PORT;
    }

    txqm_id      = SYS_TMM_GET_TXQM_BY_MACID(port_attr->mac_id);
    txqm_emac_id = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);
    index  = DRV_INS(txqm_id, 0);

    /*McMacMiiRxCfg   cfgMcMacMiiRx_[0-39]_cfgMiiRxPmacSfdEn*/
    tbl_id = McMacMiiRxCfg_t;
    step   = McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMiiRxPmacSfdEn_f - McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMiiRxPmacSfdEn_f;
    fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMiiRxPmacSfdEn_f + step*txqm_emac_id;

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, write_st));
    DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &value, write_st, txqm_id, 0);
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, write_st));

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_tx_pmac_sfd_en(uint8 lchip, uint16 lport, uint32 value)
{
    uint8  txqm_id      = 0;
    uint16 txqm_emac_id = 0;
    uint32 fld_id       = 0;
    uint32 tbl_id       = 0;
    uint32 index        = 0;
    uint32 cmd          = 0;
    uint32 step         = 0;    
    sys_datapath_lport_attr_t* port_attr = NULL;
    uint32 write_st[SYS_MAC_MAX_STRUCT_WORD] = {0};

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    if(SYS_DMPS_NETWORK_PORT != port_attr->port_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% lport %u is not a network port! \n", lport);
        return CTC_E_INVALID_PORT;
    }
    if(CTC_PORT_IF_FLEXE == port_attr->interface_type)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% FlexE client mac DONOT support xpipe \n");
        return CTC_E_INVALID_PORT;
    }

    txqm_id      = SYS_TMM_GET_TXQM_BY_MACID(port_attr->mac_id);
    txqm_emac_id = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);
    index  = DRV_INS(txqm_id, 0);

    /*McMacMiiTxCfg   cfgMcMacMiiTx_[0-39]_cfgMiiTxPmacSfdEn*/
    tbl_id = McMacMiiTxCfg_t;
    step   = McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxPmacSfdEn_f - McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxPmacSfdEn_f;
    fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxPmacSfdEn_f + step*txqm_emac_id;

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, write_st));
    DRV_IOW_FIELD_NZ(lchip, tbl_id, fld_id, &value, write_st, txqm_id, 0);
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, write_st));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_tailts_en(uint8 lchip, uint16 lport, uint32 value)
{
    uint32 step     =   0;
    uint32 tbl_id   =   0;
    uint32 fld_id   =   0;
    uint32 index    =   0;
    uint32 cmd      =   0;
    uint32 factor   =   0;
    uint32 bit1     =   0;
    uint32 bit0     =   0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (port_attr->port_type != SYS_DMPS_NETWORK_PORT)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }
    /*valid config : 0b00 0b10 0b11    bit 1 ~ en  bit 0 ~ mode*/
    if((0 != value) && (2 != value) && (3 != value))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid config %u!\n", value);
        return CTC_E_INVALID_PARAM;
    }
    bit1 = (value >> 1) & 0x1; //bit 1 en
    bit0 = value & 0x1;        //bit 0 mode

    tbl_id=McMacMacRxCfg_t;
    step= McMacMacRxCfg_cfgMcMacMacRx_1_cfgMcMacRxTailTsEn_f-McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxTailTsEn_f;
    factor = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);
    fld_id=McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxTailTsEn_f+step*factor;
    index = DRV_INS(port_attr->txqm_id, 0);
    cmd = DRV_IOW(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &bit1));

    fld_id=McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxTailTsMode_f+step*factor;
    cmd = DRV_IOW(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &bit0));

    tbl_id=McMacMacTxCfg_t;
    step= McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxKeepTsEn_f-McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxKeepTsEn_f;
    factor = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);
    fld_id=McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxKeepTsEn_f+step*factor;
    index = DRV_INS(port_attr->txqm_id, 0);
    cmd = DRV_IOW(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &bit1));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_tailts_en(uint8 lchip, uint16 lport, uint32* p_value)
{
    uint32 step     =   0;
    uint32 tbl_id   =   0;
    uint32 fld_id   =   0;
    uint32 index    =   0;
    uint32 cmd      =   0;
    uint32 factor   =   0;
    uint32 bit1     =   0;
    uint32 bit0     =   0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (port_attr->port_type != SYS_DMPS_NETWORK_PORT)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }

    tbl_id = McMacMacRxCfg_t;
    step   = McMacMacRxCfg_cfgMcMacMacRx_1_cfgMcMacRxTailTsEn_f-McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxTailTsEn_f;
    factor = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);
    fld_id = McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxTailTsEn_f+step*factor;
    index  = DRV_INS(port_attr->txqm_id, 0);
    cmd    = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &bit1));

    fld_id = McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxTailTsMode_f+step*factor;
    cmd    = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &bit0));

    SYS_USW_VALID_PTR_WRITE(p_value, ((bit1 << 1) | bit0));

    return CTC_E_NONE;
}


int32
sys_tmm_mac_set_tailts_en(uint8 lchip, uint16 lport, uint32 value)
{
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%u, enable:0x%X\n", lport, value);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_tailts_en(lchip, lport, value));
    MAC_UNLOCK;
    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_tailts_en(uint8 lchip, uint16 lport, uint32* p_value)
{

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_tailts_en(lchip, lport, p_value));
    MAC_UNLOCK;
    return CTC_E_NONE;
}


int32
_sys_tmm_mac_set_ipg(uint8 lchip, uint16 lport, uint32 value_raw)
{
    uint32 step      =       0;
    uint32 tbl_id    =       0;
    uint32 fld_id    =       0;
    uint32 index     =       0;
    uint32 cmd       =       0;
    uint32 factor    =       0;
    uint32 value     =       value_raw & 0x000000ff;
    uint32 cfg_en    =       (value_raw >> 8) & 0x000000ff;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (port_attr->port_type != SYS_DMPS_NETWORK_PORT)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }

    if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode) || 
       (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode))
    {
        if((4 != value) && (8 != value) && (12 != value))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Value %d is invalid, only 4, 8 or 12 is permitted.  \n", value);
            return CTC_E_INVALID_PARAM;
        }
    }
    else
    {
        if((8 !=value) && (12 != value))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Value %d is invalid, only 8 or 12 is permitted.  \n", value);
            return CTC_E_INVALID_PARAM;
        }
    }

    factor = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);/* 0..39 per txqm */
    index = DRV_INS(port_attr->txqm_id, 0);

    step=McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxIpgLen_f-McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIpgLen_f;
    tbl_id=McMacMiiTxCfg_t;

    fld_id=McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIpgLen_f+step*factor;
    cmd = DRV_IOW(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));

    fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxMod_f+step*factor;
    cmd = DRV_IOW(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &cfg_en));

    step=McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacRxMod_f-McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacRxMod_f;
    tbl_id=McMacMiiRxCfg_t;

    fld_id=McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacRxMod_f+step*factor;
    cmd = DRV_IOW(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &cfg_en));

    return CTC_E_NONE; 
}

int32
_sys_tmm_cpumac_set_ipg(uint8 lchip, uint16 lport, uint32 value)
{
    uint8 mii_idx = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 index = 0;
    uint32 cmd = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d, value:%d\n", lport, value);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    
    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }

    if((port_attr->pcs_mode == CTC_CHIP_SERDES_SGMII_MODE) && (4 !=value) && (8 != value) && (12 != value))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% value %d is invalid,only 4 or 8 or 12 is permitted.  \n", value);
        return CTC_E_INVALID_PARAM;
    }
    else if((port_attr->pcs_mode != CTC_CHIP_SERDES_SGMII_MODE) && (8 != value) && (12 != value))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% value %d is invalid,only 8 or 12 is permitted.  \n", value);
        return CTC_E_INVALID_PARAM;
    }
    
    mii_idx = port_attr->mii_idx;
    tbl_id=SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t);
    fld_id = SharedMii0Cfg_cfgMiiTxIpgLen0_f;
    
    cmd = DRV_IOW(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
    
    return CTC_E_NONE; 
}

int32
_sys_tmm_mac_get_ipg(uint8 lchip, uint16 lport, uint32* p_value)
{
    uint32 step      =       0;
    uint32 tbl_id    =       0;
    uint32 fld_id    =       0;
    uint32 index     =       0;
    uint32 cmd       =       0;
    uint32 factor    =       0;
    uint32 value     =       0;
    uint32 cfg_en    =       0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (port_attr->port_type != SYS_DMPS_NETWORK_PORT)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }

    factor = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);/* 0..39 per txqm */
    index = DRV_INS(port_attr->txqm_id, 0);

    step = McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxIpgLen_f-McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIpgLen_f;
    tbl_id = McMacMiiTxCfg_t;

    fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxIpgLen_f+step*factor;
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));

    fld_id=McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxMod_f+step*factor;
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &cfg_en));

    SYS_USW_VALID_PTR_WRITE(p_value, ((cfg_en << 8) | value));

    return CTC_E_NONE; 
}

int32
_sys_tmm_cpumac_get_ipg(uint8 lchip, uint16 lport, uint32 *value)
{
    uint8 mii_idx = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 index = 0;
    uint32 cmd = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d\n", lport);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    
    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }
    
    mii_idx = port_attr->mii_idx;
    tbl_id=SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t);
    fld_id = SharedMii0Cfg_cfgMiiTxIpgLen0_f;
    
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, value));

    return CTC_E_NONE; 
}

int32
_sys_tmm_cpumac_set_preamble(uint8 lchip, uint16 lport, uint32 value)
{
    uint8 mii_idx = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 index = 0;
    uint32 cmd = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d, value:%d\n", lport, value);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }

    /*check*/
    if(CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
    {
        if((2 != value) && (8 != value))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% value %d is invalid,only 2 to 8 is permitted.  \n", value);
            return CTC_E_INVALID_PARAM;
        }
    }
    else if((CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode))
    {
        if((4 != value) && (8 != value))
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% value %d is invalid,only 4 or 8 is permitted.  \n", value);
            return CTC_E_INVALID_PARAM;
        }
    }
    else
    {
        return CTC_E_NOT_SUPPORT;
    }

    mii_idx = port_attr->mii_idx;
    tbl_id=SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t);
    fld_id = SharedMii0Cfg_cfgMiiTxPreambleLen0_f;
    
    cmd = DRV_IOW(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));

    return CTC_E_NONE; 
}

int32
_sys_tmm_cpumac_get_preamble(uint8 lchip, uint16 lport, uint32 *value)
{
    uint8 mii_idx = 0;
    uint32 tbl_id = 0;
    uint32 fld_id = 0;
    uint32 index = 0;
    uint32 cmd = 0;
    uint32 val_u32 = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%d\n", lport);

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    
    if (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }
    
    mii_idx = port_attr->mii_idx;
    tbl_id=SharedMii0Cfg_t + mii_idx * (SharedMii1Cfg_t - SharedMii0Cfg_t);
    fld_id = SharedMii0Cfg_cfgMiiTxPreambleLen0_f;
    
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &val_u32));

    SYS_USW_VALID_PTR_WRITE(value, val_u32);

    return CTC_E_NONE; 
}

int32
sys_tmm_mac_set_ipg(uint8 lchip, uint16 lport, uint32 value)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%u, enable:0x%X\n", lport, value);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    
    MAC_LOCK;
    
    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_ipg(lchip, lport, value));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_cpumac_set_ipg(lchip, lport, value));
    }

    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_ipg(uint8 lchip, uint16 lport, uint32 *value)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lport:%u\n", lport);

    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    
    MAC_LOCK;
    
    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_ipg(lchip, lport, value));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_cpumac_get_ipg(lchip, lport, value));
    }
    else
    {
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }

    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_set_internal_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 value)
{
    uint32 sgmac_idx            = 0;
    uint8 cfg_index            = 0;
    uint32 step                = 0;
    uint32 write_val           = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 index               = 0;
    void *p_cfg_val = NULL;
    sys_datapath_lport_attr_t* port_attr = NULL;
    Sgmac0TxCfg_m              mac_tx_cfg;
    Sgmac0RxCfg_m              mac_rx_cfg;
    
    uint32 sgmac_prop_en_cfg_mapping[][2] = {
        /*Tbl                         Field              */
        {Sgmac0RxCfg_t,  Sgmac0RxCfg_cfgSgmac0RxCrcChkEn_f},     /*0 : CTC_PORT_PROP_CHK_CRC_EN*/
        {Sgmac0RxCfg_t,  Sgmac0RxCfg_cfgSgmac0RxTodAppendEn_f},  /*1 : CTC_PORT_PROP_APPEND_TOD_EN*/
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxPadEn_f},        /*2 : CTC_PORT_PROP_PADING_EN*/   
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxStripCrcEn_f},   /*3 : CTC_PORT_PROP_STRIP_CRC_EN*/
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxAppendCrcEn_f},  /*4 : CTC_PORT_PROP_APPEND_CRC_EN*/
    };

    switch (port_prop)
    {
        case CTC_PORT_PROP_PREAMBLE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_preamble(lchip, lport, value));
            return CTC_E_NONE;
        case CTC_PORT_PROP_CHK_CRC_EN:
            cfg_index = 0;
            break;
        case CTC_PORT_PROP_APPEND_TOD_EN:
            cfg_index = 1;
            break;  
        case CTC_PORT_PROP_PADING_EN:
            cfg_index = 2;
            break;
        case CTC_PORT_PROP_STRIP_CRC_EN:
            cfg_index = 3;
            break;
        case CTC_PORT_PROP_APPEND_CRC_EN:
            cfg_index = 4;
            break;
        default:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
            return CTC_E_NOT_SUPPORT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    
    sgmac_idx  = SYS_TMM_CPUMAC_GET_MAC_HW_IDX(port_attr->mac_id);

    step = ((cfg_index >= 2) ? (Sgmac1TxCfg_t - Sgmac0TxCfg_t) : (Sgmac1RxCfg_t - Sgmac0RxCfg_t));
    tbl_id = sgmac_prop_en_cfg_mapping[cfg_index][0] + sgmac_idx*step;

    p_cfg_val = ((cfg_index >= 2) ? ((void *)&mac_tx_cfg) : ((void *)&mac_rx_cfg));
    write_val = value ? 1 : 0;

    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, p_cfg_val));
    DRV_IOW_FIELD(lchip, tbl_id, sgmac_prop_en_cfg_mapping[cfg_index][1], &write_val, p_cfg_val);

    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, p_cfg_val));

    return CTC_E_NONE;
}

int32
_sys_tmm_cpumac_get_internal_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 *p_value)
{
    uint8 sgmac_idx            = 0;
    uint8 cfg_index            = 0;
    uint16 step                = 0;
    uint32 cmd                 = 0;
    uint32 tbl_id              = 0;
    uint32 value               = 0;
    uint32 index               = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    uint32 sgmac_prop_en_cfg_mapping[][2] = {
        /*Tbl                         Field              */
        {Sgmac0RxCfg_t,  Sgmac0RxCfg_cfgSgmac0RxCrcChkEn_f},     /*0 : CTC_PORT_PROP_CHK_CRC_EN*/
        {Sgmac0RxCfg_t,  Sgmac0RxCfg_cfgSgmac0RxTodAppendEn_f},  /*1 : CTC_PORT_PROP_APPEND_TOD_EN*/
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxPadEn_f},        /*2 : CTC_PORT_PROP_PADING_EN*/   
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxStripCrcEn_f},   /*3 : CTC_PORT_PROP_STRIP_CRC_EN*/
        {Sgmac0TxCfg_t,  Sgmac0TxCfg_cfgSgmac0TxAppendCrcEn_f},  /*4 : CTC_PORT_PROP_APPEND_CRC_EN*/
    };

    switch (port_prop)
    {
        case CTC_PORT_PROP_PREAMBLE:
            CTC_ERROR_RETURN(_sys_tmm_cpumac_get_preamble(lchip, lport, p_value));
            return CTC_E_NONE;
        case CTC_PORT_PROP_CHK_CRC_EN:
            cfg_index = 0;
            break;
        case CTC_PORT_PROP_APPEND_TOD_EN:
            cfg_index = 1;
            break;  
        case CTC_PORT_PROP_PADING_EN:
            cfg_index = 2;
            break;
        case CTC_PORT_PROP_STRIP_CRC_EN:
            cfg_index = 3;
            break;
        case CTC_PORT_PROP_APPEND_CRC_EN:
            cfg_index = 4;
            break;
         default:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
            return CTC_E_NOT_SUPPORT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    
    sgmac_idx  = SYS_TMM_CPUMAC_GET_MAC_HW_IDX(port_attr->mac_id);

    step = ((cfg_index >= 2) ? (Sgmac1TxCfg_t - Sgmac0TxCfg_t) : (Sgmac1RxCfg_t - Sgmac0RxCfg_t));
    tbl_id = sgmac_prop_en_cfg_mapping[cfg_index][0] + sgmac_idx*step;

    cmd = DRV_IOR(tbl_id, sgmac_prop_en_cfg_mapping[cfg_index][1]);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));

    SYS_USW_VALID_PTR_WRITE(p_value, value);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_internal_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 value)
{
    uint32  cmd         =       0;
    uint32  step        =       0;
    uint32 tbl_id       =       0;
    uint32 fld_id       =       0;
    uint32 factor       =       0;
    uint32 index        =       0;
    sys_datapath_lport_attr_t* port_attr = NULL;
 
    
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"mac_id:%d\n", port_attr->mac_id);
    if (port_attr->port_type != SYS_DMPS_NETWORK_PORT)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }
    factor = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);/* 0..39 per txqm */
    switch (port_prop)
    {
        case CTC_PORT_PROP_PADING_EN:
                    /*  calc pading step */
            step =McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxPadEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPadEn_f;
                        /* HW table ID */
            tbl_id = McMacMacTxCfg_t;                                                                                                                           
                        /* calc field ID */
            fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPadEn_f+step*factor;
            break;                          
        case CTC_PORT_PROP_PREAMBLE:
            if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode) ||                                                                                                                                                               
               (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode) ||
               (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode))
            {
                if(3 > value)
                {
                    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Preamble len cannot less than 2!\n");
                    return CTC_E_INVALID_PARAM;
                }
            }
            else
            {
                if(8 != value)
                {
                    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Preamble len only support 8!\n");
                    return CTC_E_INVALID_PARAM;
                }
            }
            /*  calc premble step */
            step =McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxPreambleLen_f-McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxPreambleLen_f;
            /* HW table ID */
            tbl_id = McMacMiiTxCfg_t;
            /* calc field ID */
            fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxPreambleLen_f+step*factor;
            break;
        case CTC_PORT_PROP_CHK_CRC_EN:
                /*  calc check CRC step */
            step =McMacMacRxCfg_cfgMcMacMacRx_1_cfgMcMacRxCrcCheckEn_f-McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxCrcCheckEn_f;
             /* HW table ID */
            tbl_id = McMacMacRxCfg_t;
             /* calc field ID */
            fld_id = McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxCrcCheckEn_f+step*factor;
            break;
        case CTC_PORT_PROP_STRIP_CRC_EN:
                /*  calc strip_CRC step */
            step =McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxStripCrcEn_f-McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxStripCrcEn_f;
             /* HW table ID */
            tbl_id = McMacMacTxCfg_t;
             /* calc field ID */
            fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxStripCrcEn_f+step*factor;
             break;
        case CTC_PORT_PROP_APPEND_CRC_EN:
                /*  calc append_CRC step */
            step =McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxAppendCrcEn_f-McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxAppendCrcEn_f;
             /* HW table ID */
            tbl_id = McMacMacTxCfg_t;
             /* calc field ID */
            fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxAppendCrcEn_f +step*factor;
            break;
        case CTC_PORT_PROP_APPEND_TOD_EN:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
            return CTC_E_NOT_SUPPORT;
        default:
            return CTC_E_INVALID_PARAM;
    } 
    /* #1, calc index */
    index = DRV_INS(port_attr->txqm_id, 0);
    cmd = DRV_IOW(tbl_id, fld_id);
    if((CTC_PORT_PROP_PREAMBLE != port_prop) && (1 < value))
    {
        return CTC_E_INVALID_PARAM;
    }
    else
    {
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
    }

    return CTC_E_NONE;  
}

int32
_sys_tmm_mac_get_internal_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32* p_value)
{
    uint32  cmd         =       0;
    uint32  step        =       0;
    uint32 tbl_id       =       0;
    uint32 fld_id       =       0;
    uint32 factor       =       0;
    uint32 index        =       0;
    uint32 value        =       0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"mac_id:%d\n", port_attr->mac_id);
    if (port_attr->port_type != SYS_DMPS_NETWORK_PORT)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }
    factor = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);/* 0..39 per txqm */
    switch(port_prop)
    {
        case CTC_PORT_PROP_PADING_EN:
                    /*  calc pading step */
            step =McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxPadEn_f - McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPadEn_f;
                        /* HW table ID */
            tbl_id = McMacMacTxCfg_t;                                                                                                                           
                        /* calc field ID */
            fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxPadEn_f+step*factor;
            break;                          
        case CTC_PORT_PROP_PREAMBLE:
            /*  calc premble step */
            step =McMacMiiTxCfg_cfgMcMacMiiTx_1_cfgMcMacTxPreambleLen_f-McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxPreambleLen_f;
            /* HW table ID */
            tbl_id = McMacMiiTxCfg_t;
            /* calc field ID */
            fld_id = McMacMiiTxCfg_cfgMcMacMiiTx_0_cfgMcMacTxPreambleLen_f+step*factor;
            break;
        case CTC_PORT_PROP_CHK_CRC_EN:
                /*  calc check CRC step */
            step =McMacMacRxCfg_cfgMcMacMacRx_1_cfgMcMacRxCrcCheckEn_f-McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxCrcCheckEn_f;
             /* HW table ID */
            tbl_id = McMacMacRxCfg_t;
             /* calc field ID */
            fld_id = McMacMacRxCfg_cfgMcMacMacRx_0_cfgMcMacRxCrcCheckEn_f+step*factor;
            break;
        case CTC_PORT_PROP_STRIP_CRC_EN:
                /*  calc strip_CRC step */
            step =McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxStripCrcEn_f-McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxStripCrcEn_f;
             /* HW table ID */
            tbl_id = McMacMacTxCfg_t;
             /* calc field ID */
            fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxStripCrcEn_f+step*factor;
             break;
        case CTC_PORT_PROP_APPEND_CRC_EN:
                /*  calc append_CRC step */
            step =McMacMacTxCfg_cfgMcMacMacTx_1_cfgMcMacTxAppendCrcEn_f-McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxAppendCrcEn_f;
             /* HW table ID */
            tbl_id = McMacMacTxCfg_t;
             /* calc field ID */
            fld_id = McMacMacTxCfg_cfgMcMacMacTx_0_cfgMcMacTxAppendCrcEn_f +step*factor;
            break;
        case CTC_PORT_PROP_APPEND_TOD_EN:
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
            return CTC_E_NOT_SUPPORT;
        default:
            return CTC_E_INVALID_PARAM;
    } 
    /* #1, calc index */
    index = DRV_INS(port_attr->txqm_id, 0);
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));

    SYS_USW_VALID_PTR_WRITE(p_value, value);

    return CTC_E_NONE;  
}

int32
sys_tmm_mac_set_internal_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 value)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set mac internal property, lport:%u, property:%d, value:%d\n", \
                     lport, port_prop, value);
    /*Sanity check*/
    SYS_MAC_INIT_CHECK();
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    
    MAC_LOCK;

    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_internal_property(lchip, lport, port_prop, value));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_cpumac_set_internal_property(lchip, lport, port_prop, value));
    }
    else
    {
        MAC_UNLOCK;
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
        return CTC_E_INVALID_PORT;
    }
    
    MAC_UNLOCK;
    
    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_internal_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 *p_value)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "lport:%u, property:%d\n", lport, port_prop);
    /*Sanity check*/
    SYS_MAC_INIT_CHECK();
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    
    MAC_LOCK;

    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_internal_property(lchip, lport, port_prop, p_value));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_cpumac_get_internal_property(lchip, lport, port_prop, p_value));
    }
    else
    {
        MAC_UNLOCK;
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
        return CTC_E_INVALID_PORT;
    }
    
    MAC_UNLOCK;
    
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_nw_sgmii_set_parallel_detect_en(uint8 lchip, sys_datapath_lport_attr_t* port_attr, uint32 enable)
{
    uint8  is_pcs_x16       = 0;
    uint8  pcs_x8_x16_index = 0;
    uint32 tbl_id           = 0;
    uint32 step             = 0;
    uint32 field_id         = 0;
    uint32 cmd              = 0;
    uint32 index            = 0;
    uint8  pcs_idx          = port_attr->pcs_idx;

    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
    index = DRV_INS(pcs_x8_x16_index, 0);

    if(is_pcs_x16)
    {
        tbl_id = McPcsX16LanesSgmiiCfg_t;
        step = McPcsX16LanesSgmiiCfg_cfgSgmii_1_anParallelDetectEn_f -McPcsX16LanesSgmiiCfg_cfgSgmii_0_anParallelDetectEn_f;
        field_id = McPcsX16LanesSgmiiCfg_cfgSgmii_0_anParallelDetectEn_f + step*pcs_idx;
    }
    else
    {
        tbl_id = McPcsX8LanesSgmiiCfg_t;
        step = McPcsX8LanesSgmiiCfg_cfgSgmii_1_anParallelDetectEn_f -McPcsX8LanesSgmiiCfg_cfgSgmii_0_anParallelDetectEn_f;
        field_id = McPcsX8LanesSgmiiCfg_cfgSgmii_0_anParallelDetectEn_f + step*pcs_idx;
    }
    cmd = DRV_IOW(tbl_id, field_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &enable));
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_sgmii_set_parallel_detect_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint32 cl37_en                  = 0;
    uint32 index                    = 0;
    uint32 tbl_id                   = 0;
    uint32 step                     = 0;
    uint32 field_id                 = 0;
    uint32 value                    = enable ? 1 : 0;
    uint32 cmd                      = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    /*parameter check*/
    CTC_ERROR_RETURN(_sys_tmm_mac_get_cl37_en(lchip, lport, &cl37_en));

    if (!cl37_en)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Lport %d in force mode, cannot set parallel detect. \n", lport);
        return CTC_E_INVALID_CONFIG;
    }

    /*Normal Ethernet Network Port*/
    if(SYS_DMPS_NETWORK_PORT == port_attr->port_type)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_nw_sgmii_set_parallel_detect_en(lchip, port_attr, value));
    }
    /*CPUMAC Port*/
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
        tbl_id = SharedPcsSgmii0Cfg_t + port_attr->pcs_idx*step;
        field_id = SharedPcsSgmii0Cfg_anParallelDetectEn0_f;
        cmd = DRV_IOW(tbl_id, field_id);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_qsgmii_set_parallel_detect_en(uint8 lchip, uint16 lport, uint8 enable)
{
    uint8 pcs_x8_x16_index          = 0;
    uint32 index                    = 0;
    uint32 tbl_id                   = 0;
    uint32 step                     = 0;
    uint32 field_id                 = 0;
    uint32 cmd                      = 0;
    uint32 factor                   = 0;
    uint32 value                    = enable ? 1 : 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if (port_attr->port_type != SYS_DMPS_NETWORK_PORT)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }

    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, factor, pcs_x8_x16_index);
    index = DRV_INS(pcs_x8_x16_index, 0);

    tbl_id = McPcsX16LanesQsgmiiCfg_t;
    step = McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_anParallelDetectEn_f -McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anParallelDetectEn_f;
    factor = port_attr->mac_id-(SYS_TMM_MAX_MAC_NUM_PER_TXQM*port_attr->txqm_id);
    field_id = McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anParallelDetectEn_f + step*factor;

    cmd = DRV_IOW(tbl_id, field_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));

    return CTC_E_NONE;
}


int32
sys_tmm_mac_set_parallel_detect_en(uint8 lchip, uint16 lport, uint32 value)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "lport:%u, value:%d\n", lport, value);

    /*Sanity check*/
    SYS_MAC_INIT_CHECK();
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    MAC_LOCK;
    
    if ((port_attr->port_type != SYS_DMPS_NETWORK_PORT) && ((!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))))
    {
        MAC_UNLOCK;
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }

    switch(port_attr->pcs_mode)
    {
        case CTC_CHIP_SERDES_SGMII_MODE:
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_sgmii_set_parallel_detect_en(lchip, lport, value ? TRUE : FALSE));
            break;
        case CTC_CHIP_SERDES_QSGMII_MODE:
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_qsgmii_set_parallel_detect_en(lchip, lport, value ? TRUE : FALSE));
            break;  
        default:
            MAC_UNLOCK;
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " API or some feature is not supported \n");
            return CTC_E_NOT_SUPPORT;
    }
    MAC_UNLOCK;
    
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_sgmii_get_parallel_detect_en(uint8 lchip, uint16 lport, uint32 *value)
{
    uint8 is_pcs_x16                = 0;
    uint8 pcs_x8_x16_index          = 0;
    uint8 pcs_idx                   = 0;
    uint32 index                    = 0;
    uint32 tbl_id                   = 0;
    uint32 step                     = 0;
    uint32 field_id                 = 0;
    uint32 cmd                      = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if ((port_attr->port_type != SYS_DMPS_NETWORK_PORT) && (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type)))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }

    pcs_idx = port_attr->pcs_idx;

    /*Normal Ethernet Network Port*/
    if(SYS_DMPS_NETWORK_PORT == port_attr->port_type)
    {
        SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, is_pcs_x16, pcs_x8_x16_index);
        index = DRV_INS(pcs_x8_x16_index, 0);

        if(is_pcs_x16)
        {
            tbl_id = McPcsX16LanesSgmiiCfg_t;
            step = McPcsX16LanesSgmiiCfg_cfgSgmii_1_anParallelDetectEn_f -McPcsX16LanesSgmiiCfg_cfgSgmii_0_anParallelDetectEn_f;
            field_id = McPcsX16LanesSgmiiCfg_cfgSgmii_0_anParallelDetectEn_f + step*pcs_idx;
        }
        else
        {
            tbl_id = McPcsX8LanesSgmiiCfg_t;
            step = McPcsX8LanesSgmiiCfg_cfgSgmii_1_anParallelDetectEn_f -McPcsX8LanesSgmiiCfg_cfgSgmii_0_anParallelDetectEn_f;
            field_id = McPcsX8LanesSgmiiCfg_cfgSgmii_0_anParallelDetectEn_f + step*pcs_idx;
        }
    }
    /*CPUMAC Port*/
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        step = SharedPcsSgmii1Cfg_t - SharedPcsSgmii0Cfg_t;
        tbl_id = SharedPcsSgmii0Cfg_t + pcs_idx*step;
        field_id = SharedPcsSgmii0Cfg_anParallelDetectEn0_f;
    }

    cmd = DRV_IOR(tbl_id, field_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, value));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_qsgmii_get_parallel_detect_en(uint8 lchip, uint16 lport, uint32 *value)
{
    uint8 pcs_x8_x16_index          = 0;
    uint32 index                    = 0;
    uint32 tbl_id                   = 0;
    uint32 step                     = 0;
    uint32 field_id                 = 0;
    uint32 cmd                      = 0;
    uint32 factor                   = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if (port_attr->port_type != SYS_DMPS_NETWORK_PORT)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_CONFIG;
    }

    SYS_TMM_GET_PCS_X8_X16_BY_TXQM(port_attr->txqm_id, factor, pcs_x8_x16_index);
    index = DRV_INS(pcs_x8_x16_index, 0);

    tbl_id = McPcsX16LanesQsgmiiCfg_t;
    step = McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_1_anParallelDetectEn_f -McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anParallelDetectEn_f;
    factor = port_attr->mac_id-(SYS_TMM_MAX_MAC_NUM_PER_TXQM*port_attr->txqm_id);
    field_id = McPcsX16LanesQsgmiiCfg_cfgQsgmiiSgmii_0_anParallelDetectEn_f + step*factor;

    cmd = DRV_IOR(tbl_id, field_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, value));

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_parallel_detect_en(uint8 lchip, uint16 lport, uint32 *p_value)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    /*Sanity check*/
    SYS_MAC_INIT_CHECK();
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    MAC_LOCK;
    if((port_attr->port_type != SYS_DMPS_NETWORK_PORT) && ((!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))))
    {
        MAC_UNLOCK;
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }

    switch(port_attr->pcs_mode)
    {
        case CTC_CHIP_SERDES_SGMII_MODE:
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_sgmii_get_parallel_detect_en(lchip, lport, p_value));
            break;
        case CTC_CHIP_SERDES_QSGMII_MODE:
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_qsgmii_get_parallel_detect_en(lchip, lport, p_value));
            break;
        default:
            break;
    }
    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_check_property_is_supoort(uint8 lchip, uint16 lport, ctc_port_property_t port_prop)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    SYS_MAC_INIT_CHECK();
    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if(CTC_PORT_IF_FLEXE == port_attr->interface_type)
    {
        switch(port_prop)
        {
            case CTC_PORT_PROP_SPEED:
            case CTC_PORT_PROP_AUTO_NEG_EN:        
            case CTC_PORT_PROP_AUTO_NEG_MODE:             
            case CTC_PORT_PROP_CL73_ABILITY:              
            case CTC_PORT_PROP_FEC_EN:              
            case CTC_PORT_PROP_LINK_INTRRUPT_EN:             
            case CTC_PORT_PROP_SIGNAL_DETECT:         
            case CTC_PORT_PROP_XPIPE_EN:                  
            case CTC_PORT_PROP_XPIPE_MODE:                
            case CTC_PORT_PROP_AUTO_NEG_FEC:
            case CTC_PORT_PROP_FEC_CNT:
            case CTC_PORT_PROP_PAR_DET_EN:   
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
                return CTC_E_NOT_SUPPORT;
            default:
                break;
        }
    }
    else if(SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type)
    {
        switch(port_prop)
        {
            case CTC_PORT_PROP_SPEED:                     
            case CTC_PORT_PROP_MAX_FRAME_SIZE:            
            case CTC_PORT_PROP_MIN_FRAME_SIZE:            
            case CTC_PORT_PROP_PREAMBLE:                  
            case CTC_PORT_PROP_PADING_EN:                 
            case CTC_PORT_PROP_MAC_TX_IPG:         
            case CTC_PORT_PROP_AUTO_NEG_MODE:
            case CTC_PORT_PROP_UNIDIR_EN:
            case CTC_PORT_PROP_XPIPE_EN:                  
            case CTC_PORT_PROP_XPIPE_MODE:                
            case CTC_PORT_PROP_FAULT:                     
            case CTC_PORT_PROP_PAR_DET_EN:
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% API or some feature is not supported \n");
                return CTC_E_NOT_SUPPORT;
            default:
                break;
        }
    }

    return CTC_E_NONE;
}

/**
@brief   Config port's properties
*/
int32
sys_tmm_mac_set_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 value)
{
    int32   ret    = CTC_E_NONE;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port property, lport:%u, property:%d, value:%d\n", \
                     lport, port_prop, value);

    /*Sanity check*/
    SYS_MAC_INIT_CHECK();

    CTC_ERROR_RETURN(_sys_tmm_mac_check_property_is_supoort(lchip,   lport, port_prop));

    switch (port_prop)
    {
    case CTC_PORT_PROP_MAC_EN:
        value = (value) ? TRUE : FALSE;
        ret = sys_tmm_mac_set_mac_en(lchip, lport, value);
        break;

    case CTC_PORT_PROP_FEC_EN:
        ret = sys_tmm_mac_set_fec_en(lchip, lport, value);
        break;

    case CTC_PORT_PROP_CL73_ABILITY:
        ret = sys_tmm_mac_set_cl73_ability(lchip, lport, value);
        break;

    case CTC_PORT_PROP_AUTO_NEG_EN:
        value = (value) ? TRUE : FALSE;
        ret = sys_tmm_mac_set_auto_neg(lchip, lport, CTC_PORT_PROP_AUTO_NEG_EN, value);
        break;

    case CTC_PORT_PROP_AUTO_NEG_MODE:
        ret = sys_tmm_mac_set_auto_neg(lchip, lport, CTC_PORT_PROP_AUTO_NEG_MODE, value);
        break;

    case CTC_PORT_PROP_AUTO_NEG_FEC:
        ret = sys_tmm_mac_set_auto_neg(lchip, lport, CTC_PORT_PROP_AUTO_NEG_FEC, value);
        break;

    case CTC_PORT_PROP_SPEED:
        ret = sys_tmm_mac_set_speed(lchip, lport, value);
        break;

    case CTC_PORT_PROP_LINK_INTRRUPT_EN:
        value = (value) ? TRUE : FALSE;
        ret = sys_tmm_mac_set_link_intr(lchip, lport, value);
        break;

    case CTC_PORT_PROP_UNIDIR_EN:
        value = (value) ? 1 : 0;
        ret = sys_tmm_mac_set_unidir_en(lchip, lport, value);
        break;

    case CTC_PORT_PROP_MAC_TX_IPG:
        ret = sys_tmm_mac_set_ipg(lchip, lport, value);
        break;

    case CTC_PORT_PROP_PREAMBLE:
    case CTC_PORT_PROP_PADING_EN:
    case CTC_PORT_PROP_CHK_CRC_EN:
    case CTC_PORT_PROP_STRIP_CRC_EN:
    case CTC_PORT_PROP_APPEND_CRC_EN:
    case CTC_PORT_PROP_APPEND_TOD_EN:
        ret = sys_tmm_mac_set_internal_property(lchip, lport, port_prop, value);
        break;
    case CTC_PORT_PROP_XPIPE_EN:
        ret = sys_tmm_mac_set_xpipe_en(lchip, lport, value);
        break;
    case CTC_PORT_PROP_MAC_TS_EN:
        ret = sys_tmm_mac_set_tailts_en(lchip, lport, value);
        break;
    case CTC_PORT_PROP_PAR_DET_EN:
        ret = sys_tmm_mac_set_parallel_detect_en(lchip, lport, value);
        break;

    case CTC_PORT_PROP_ERROR_CHECK:
    case CTC_PORT_PROP_RX_PAUSE_TYPE:
    case CTC_PORT_PROP_LINKSCAN_EN:
    default:
        return CTC_E_NOT_SUPPORT;
    }

    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_DATAPATH, SYS_WB_APPID_DATAPATH_SUBID_MASTER, 1);
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT,     SYS_WB_APPID_PORT_SUBID_MAC_PROP,   1);

    if (ret != CTC_E_NONE)
    {
        return ret;
    }

    return CTC_E_NONE;
}

/*This function is changed from _sys_tmm_mac_set_fec_en, and delete some redundant steps.
If current FEC mode is the same as new FEC mode, do pcs & mac reset; else do pcs & mac disable -> fec cfg -> enable*/
int32
_sys_tmm_mac_an_done_fec_cfg(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr, uint32 fec_type)
{
    uint8 mac_toggle_flag = 0;

    if (p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en)
    {
        mac_toggle_flag = 1;
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_en(lchip, lport, FALSE));
    }

    if(p_usw_mac_master[lchip]->mac_prop[lport].port_fec_val != fec_type)
    {
        if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
        {
            CTC_ERROR_RETURN(_sys_tmm_cpumac_set_fec_config(lchip, lport, port_attr->pcs_mode, fec_type));
        }
        else
        {
            /*low corepll fec map clear before config*/
            _sys_tmm_mac_low_corepll_fec_free(lchip, port_attr);
            /*set fec config*/
            CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_config(lchip, lport, port_attr->pcs_mode, fec_type, port_attr->port_type, FALSE));
            /*low corepll fec map remap after config*/
            _sys_tmm_mac_low_corepll_fec_remap(lchip, lport, port_attr);
        }
    }

    if (mac_toggle_flag)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_isr_cl73_complete_isr(uint8 lchip, void* p_data, void* p_data1)
{
    uint16 lport                     = 0;
    uint8  cl73_ok                   = 0;
    uint8  serdes_id                 = 0;
    uint8  enable                    = 0;
    uint8  cnt                       = 0;
    uint8  hss_idx                   = 0;
    uint8  logical_serdes_id         = 0;
    uint8  logic_lane_id             = 0;
    uint16 anlt_status               = 0;
    uint32 fec_type                  = 0;
    sys_datapath_an_ability_t        remote_ability;
    sys_datapath_an_ability_t        local_ability;
    uint32 ability[2]                = {0};
    uint32 cstm_ability[2]           = {0};
    sys_datapath_hss_attribute_t*    p_hss_vec = NULL;
    sys_datapath_lport_attr_t*       port_attr = NULL;
    ctc_port_if_mode_t               if_mode   = {0};
    sys_tmm_serdes_fw_config_param_t fw_data   = {0};
    sys_datapath_an_ability_t        an_ability = {0};

    cl73_ok   = *((uint8*)p_data1);
    serdes_id = *((uint8*)p_data);

    SYS_CL73_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "Enter %s\n", __FUNCTION__);
    SYS_CL73_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"serdes_id:%d, cl73_ok:%d\n", serdes_id, cl73_ok);

    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    fw_data.link_train = SYS_TMM_SERDES_LINK_TRAIN_TYPE_ENABLE;

    CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, serdes_id, &logical_serdes_id));
    SYS_CONDITION_RETURN((SYS_TMM_USELESS_ID8 == logical_serdes_id), CTC_E_INVALID_PARAM);
    CTC_ERROR_RETURN(sys_usw_datapath_get_lport_with_serdes(lchip, logical_serdes_id, &lport));

    hss_idx = SYS_TMM_MAP_SERDES_TO_HSS_IDX(serdes_id);
    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_idx);
    logic_lane_id = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);

    SYS_CONDITION_RETURN(SYS_USW_MAX_PORT_NUM_PER_CHIP <= lport, CTC_E_INVALID_PARAM);
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if ((port_attr->port_type != SYS_DMPS_NETWORK_PORT)
        && (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
        && (port_attr->port_type != SYS_DMPS_INACTIVE_NETWORK_PORT))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC is not used \n");
        return CTC_E_INVALID_CONFIG;
    }

    if ((CTC_CHIP_SERDES_XAUI_MODE == port_attr->pcs_mode) || (CTC_CHIP_SERDES_DXAUI_MODE == port_attr->pcs_mode))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not support \n");
        return CTC_E_NOT_SUPPORT;
    }

    if (SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num)
    {
        return CTC_E_INVALID_PARAM;
    }

    MAC_LOCK;

    if(!cl73_ok)
    {
        MAC_UNLOCK;
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% CL73 is not done! lport %u \n", lport);
        return CTC_E_INVALID_CONFIG;
    }

    port_attr->an_done_opr = TRUE;
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_OK, 1);
    if (0 == port_attr->is_first)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_read_reg(lchip, serdes_id, AUTO_NEG_LINK_TRAINING_STATUS_ADDR, 0, &anlt_status));
        if (!(anlt_status & 0x0001))
        {
            port_attr->an_done_opr = FALSE;

            MAC_UNLOCK;

            SYS_CL73_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "Exit %s\n", __FUNCTION__);

            return CTC_E_NONE;
        }

        /* 1. recover bypass, get ability */
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_get_serdes_auto_neg_local_ability(lchip, serdes_id, &local_ability));
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_get_serdes_auto_neg_remote_ability(lchip, serdes_id, &remote_ability));
        ability[0] = local_ability.base_ability0 & remote_ability.base_ability0;
        ability[1] = local_ability.base_ability1 & remote_ability.base_ability1;
        cstm_ability[0] = local_ability.np1_ability0 & remote_ability.np1_ability0;
        cstm_ability[1] = local_ability.np1_ability1 & remote_ability.np1_ability1;

        if (CTC_FLAG_ISSET(cstm_ability[1], SYS_PORT_CSTM_400GBASE_CR8))
        {
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD, 0);
            /* enable Link training */
            fw_data.data_rate = CTC_CHIP_SERDES_CDG_R8_MODE;
            fw_data.ovclk_speed = (uint8) p_hss_vec->serdes_info[logic_lane_id].overclocking_speed;

            for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
            {
                /* program different polynomials for different lanes */
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_write_reg(lchip, port_attr->multi_serdes_id[cnt],
                    POLYNOMIAL_CONFIG_ADDR, 0xE7FF, (uint16) (cnt % 4)));

                fw_data.serdes_id = port_attr->multi_serdes_id[cnt];
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_deconfig(lchip, fw_data.serdes_id));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_config(lchip, &fw_data));
            }

            if_mode.speed = CTC_PORT_SPEED_400G;
            if_mode.interface_type = CTC_PORT_IF_CR8;

            if (CTC_CHIP_SERDES_CDG_R8_MODE != port_attr->pcs_mode)
            {
                /* disable original MAC */
                enable = p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en;
                sal_memcpy(&an_ability, &(port_attr->an_ability), sizeof(sys_datapath_an_ability_t));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport, &if_mode));
                sal_memcpy(&(port_attr->an_ability), &an_ability, sizeof(sys_datapath_an_ability_t));
                /* enable CDG MAC */
                if (enable)
                {
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
                }
            }
            else
            {
                port_attr->interface_type = if_mode.interface_type;
            }
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_RS544));
        }
        else if (CTC_FLAG_ISSET(ability[1], SYS_PORT_CL73_200GBASE_KR4)
            || CTC_FLAG_ISSET(ability[1], SYS_PORT_CL73_200GBASE_CR4))
        {
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD, 1);
            /* enable Link training */
            fw_data.data_rate = CTC_CHIP_SERDES_CCG_R4_MODE;
            fw_data.ovclk_speed = (uint8) p_hss_vec->serdes_info[logic_lane_id].overclocking_speed;

            for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
            {
                /* program different polynomials for different lanes */
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_write_reg(lchip, port_attr->multi_serdes_id[cnt],
                    POLYNOMIAL_CONFIG_ADDR, 0xE7FF, (uint16) (cnt % 4)));

                fw_data.serdes_id = port_attr->multi_serdes_id[cnt];
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_deconfig(lchip, fw_data.serdes_id));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_config(lchip, &fw_data));
            }

            if_mode.speed = CTC_PORT_SPEED_200G;
            if_mode.interface_type = CTC_PORT_IF_CR4;

            if (CTC_CHIP_SERDES_CCG_R4_MODE != port_attr->pcs_mode)
            {
                /* disable original MAC */
                enable = p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en;
                sal_memcpy(&an_ability, &(port_attr->an_ability), sizeof(sys_datapath_an_ability_t));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport, &if_mode));
                sal_memcpy(&(port_attr->an_ability), &an_ability, sizeof(sys_datapath_an_ability_t));
                /* enable CCG MAC */
                if (enable)
                {
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
                }
            }
            else
            {
                port_attr->interface_type = if_mode.interface_type;
            }

            if ((CTC_FLAG_ISSET(cstm_ability[1], SYS_PORT_CSTM_LF3_200GR4)
                    && (CTC_FLAG_ISSET(local_ability.np1_ability1, SYS_PORT_CSTM_LL_RS_FEC_REQ)
                        ||CTC_FLAG_ISSET(remote_ability.np1_ability1, SYS_PORT_CSTM_LL_RS_FEC_REQ))))
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_RS272));
            }
            else
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_RS544));
            }
        }
        else if (CTC_FLAG_ISSET(ability[1], SYS_PORT_CL73_100GBASE_KR2)
            || CTC_FLAG_ISSET(ability[1], SYS_PORT_CL73_100GBASE_CR2))
        {
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD, 2);
            /* enable Link training */
            fw_data.data_rate = CTC_CHIP_SERDES_CG_R2_MODE;

            if(CTC_FLAG_ISSET(cstm_ability[1], SYS_PORT_CSTM_LF2_100GR2) && 
               (CTC_FLAG_ISSET(local_ability.np1_ability1, SYS_PORT_CSTM_LL_RS_FEC_REQ) || 
                CTC_FLAG_ISSET(remote_ability.np1_ability1, SYS_PORT_CSTM_LL_RS_FEC_REQ))) /*for CSTM 100GR2 && CSTM RS272*/
            {
                if(CTC_CHIP_SERDES_OCS_MODE_NONE == p_hss_vec->serdes_info[logic_lane_id].overclocking_speed)
                {
                    p_hss_vec->serdes_info[logic_lane_id].overclocking_speed = CTC_CHIP_SERDES_OCS_MODE_51_56G;
                }
                fw_data.ovclk_speed = (uint8)(p_hss_vec->serdes_info[logic_lane_id].overclocking_speed);
                fec_type = CTC_PORT_FEC_TYPE_RS272;
            }
            else if((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_RS)) && 
                    (CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_25G_RS_FEC_REQ) || 
                     CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_25G_RS_FEC_REQ))) /*for IEEE 100GR2 && CTC RS528*/
            {
                if(CTC_CHIP_SERDES_OCS_MODE_51_56G == p_hss_vec->serdes_info[logic_lane_id].overclocking_speed)
                {
                    p_hss_vec->serdes_info[logic_lane_id].overclocking_speed = CTC_CHIP_SERDES_OCS_MODE_NONE;
                }
                fw_data.ovclk_speed = (uint8)(p_hss_vec->serdes_info[logic_lane_id].overclocking_speed);
                fec_type = CTC_PORT_FEC_TYPE_RS528;
            }
            else /*for IEEE 100GR2*/
            {
                if(CTC_CHIP_SERDES_OCS_MODE_NONE == p_hss_vec->serdes_info[logic_lane_id].overclocking_speed)
                {
                    p_hss_vec->serdes_info[logic_lane_id].overclocking_speed = CTC_CHIP_SERDES_OCS_MODE_51_56G;
                }
                fw_data.ovclk_speed = (uint8)(p_hss_vec->serdes_info[logic_lane_id].overclocking_speed);
                fec_type = CTC_PORT_FEC_TYPE_RS544;
            }  

            for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
            {
                /* program different polynomials for different lanes */
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_write_reg(lchip, port_attr->multi_serdes_id[cnt],
                    POLYNOMIAL_CONFIG_ADDR, 0xE7FF, (uint16) (cnt % 4)));

                fw_data.serdes_id = port_attr->multi_serdes_id[cnt];
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_deconfig(lchip, fw_data.serdes_id));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_config(lchip, &fw_data));
            }

            if_mode.speed = CTC_PORT_SPEED_100G;
            if_mode.interface_type = CTC_PORT_IF_CR2;

            if (CTC_CHIP_SERDES_CG_R2_MODE != port_attr->pcs_mode)
            {
                /* disable original MAC */
                enable = p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en;
                sal_memcpy(&an_ability, &(port_attr->an_ability), sizeof(sys_datapath_an_ability_t));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport, &if_mode));
                sal_memcpy(&(port_attr->an_ability), &an_ability, sizeof(sys_datapath_an_ability_t));
                /* enable CG MAC */
                if (enable)
                {
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
                }
            }
            else
            {
                port_attr->interface_type = if_mode.interface_type;
            }

            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, fec_type));
        }
        else if (CTC_FLAG_ISSET(ability[0], SYS_PORT_CL73_100GBASE_KR4)
            || CTC_FLAG_ISSET(ability[0], SYS_PORT_CL73_100GBASE_CR4))
        {
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD, 3);
            /* enable Link training */
            fw_data.data_rate = CTC_CHIP_SERDES_CG_MODE;
            fw_data.ovclk_speed = (uint8) p_hss_vec->serdes_info[logic_lane_id].overclocking_speed;

            for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
            {
                /* program different polynomials for different lanes */
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_write_reg(lchip, port_attr->multi_serdes_id[cnt],
                    POLYNOMIAL_CONFIG_ADDR, 0xE7FF, (uint16) (cnt % 4)));

                fw_data.serdes_id = port_attr->multi_serdes_id[cnt];
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_deconfig(lchip, fw_data.serdes_id));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_config(lchip, &fw_data));
            }

            if_mode.speed = CTC_PORT_SPEED_100G;
            if_mode.interface_type = CTC_PORT_IF_CR4;

            if (CTC_CHIP_SERDES_CG_MODE != port_attr->pcs_mode)
            {
                /* disable original MAC */
                enable = p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en;
                sal_memcpy(&an_ability, &(port_attr->an_ability), sizeof(sys_datapath_an_ability_t));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport, &if_mode));
                sal_memcpy(&(port_attr->an_ability), &an_ability, sizeof(sys_datapath_an_ability_t));
                /* enable CG MAC */
                if (enable)
                {
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
                }
            }
            else
            {
                port_attr->interface_type = if_mode.interface_type;
            }

            if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_RS))
                && ((CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_25G_RS_FEC_REQ))
                    ||(CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_25G_RS_FEC_REQ))))
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_RS528));
            }
            else
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_NONE));
            }
        }
        else if (CTC_FLAG_ISSET(ability[1], SYS_PORT_CL73_50GBASE_KR)
            || CTC_FLAG_ISSET(ability[1], SYS_PORT_CL73_50GBASE_CR))
        {
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD, 4);
            /* enable Link training */
            fw_data.data_rate = CTC_CHIP_SERDES_LG_R1_MODE;

            if(CTC_FLAG_ISSET(cstm_ability[1], SYS_PORT_CSTM_LF1_50GR1) && 
               (CTC_FLAG_ISSET(local_ability.np1_ability1, SYS_PORT_CSTM_LL_RS_FEC_REQ) || 
                CTC_FLAG_ISSET(remote_ability.np1_ability1, SYS_PORT_CSTM_LL_RS_FEC_REQ))) /*for CSTM 50GR1 && CSTM RS272*/
            {
                if(CTC_CHIP_SERDES_OCS_MODE_NONE == p_hss_vec->serdes_info[logic_lane_id].overclocking_speed)
                {
                    p_hss_vec->serdes_info[logic_lane_id].overclocking_speed = CTC_CHIP_SERDES_OCS_MODE_51_56G;
                }
                fw_data.ovclk_speed = (uint8)(p_hss_vec->serdes_info[logic_lane_id].overclocking_speed);
                fec_type = CTC_PORT_FEC_TYPE_RS272;
            }
            else if((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_RS)) && 
                    (CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_25G_RS_FEC_REQ) || 
                     CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_25G_RS_FEC_REQ))) /*for IEEE 50GR1 && CTC RS528*/
            {
                if(CTC_CHIP_SERDES_OCS_MODE_51_56G == p_hss_vec->serdes_info[logic_lane_id].overclocking_speed)
                {
                    p_hss_vec->serdes_info[logic_lane_id].overclocking_speed = CTC_CHIP_SERDES_OCS_MODE_NONE;
                }
                fw_data.ovclk_speed = (uint8)(p_hss_vec->serdes_info[logic_lane_id].overclocking_speed);
                fec_type = CTC_PORT_FEC_TYPE_RS528;
            }
            else /*for IEEE 50GR1*/
            {
                if(CTC_CHIP_SERDES_OCS_MODE_NONE == p_hss_vec->serdes_info[logic_lane_id].overclocking_speed)
                {
                    p_hss_vec->serdes_info[logic_lane_id].overclocking_speed = CTC_CHIP_SERDES_OCS_MODE_51_56G;
                }
                fw_data.ovclk_speed = (uint8)(p_hss_vec->serdes_info[logic_lane_id].overclocking_speed);
                fec_type = CTC_PORT_FEC_TYPE_RS544;
            }            

            for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
            {
                /* program different polynomials for different lanes */
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_write_reg(lchip, port_attr->multi_serdes_id[cnt],
                    POLYNOMIAL_CONFIG_ADDR, 0xE7FF, (uint16) (cnt % 4)));

                fw_data.serdes_id = port_attr->multi_serdes_id[cnt];
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_deconfig(lchip, fw_data.serdes_id));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_config(lchip, &fw_data));
            }

            if_mode.speed = CTC_PORT_SPEED_50G;
            if_mode.interface_type = CTC_PORT_IF_CR;

            if (CTC_CHIP_SERDES_LG_R1_MODE != port_attr->pcs_mode)
            {
                /* disable original MAC */
                enable = p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en;
                sal_memcpy(&an_ability, &(port_attr->an_ability), sizeof(sys_datapath_an_ability_t));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport, &if_mode));
                sal_memcpy(&(port_attr->an_ability), &an_ability, sizeof(sys_datapath_an_ability_t));
                /* enable LG MAC */
                if (enable)
                {
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
                }
            }
            else
            {
                port_attr->interface_type = if_mode.interface_type;
            }

            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, fec_type));
        }
        else if (CTC_FLAG_ISSET(cstm_ability[0], SYS_PORT_CSTM_50GBASE_KR2)
                || CTC_FLAG_ISSET(cstm_ability[0], SYS_PORT_CSTM_50GBASE_CR2))
        {
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD, 5);
            /* enable Link training */
            fw_data.data_rate = CTC_CHIP_SERDES_LG_MODE;
            fw_data.ovclk_speed = (uint8) p_hss_vec->serdes_info[logic_lane_id].overclocking_speed;

            for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
            {
                /* program different polynomials for different lanes */
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_write_reg(lchip, port_attr->multi_serdes_id[cnt],
                    POLYNOMIAL_CONFIG_ADDR, 0xE7FF, (uint16) (cnt % 4)));

                fw_data.serdes_id = port_attr->multi_serdes_id[cnt];
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_deconfig(lchip, fw_data.serdes_id));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_config(lchip, &fw_data));
            }

            if_mode.speed = CTC_PORT_SPEED_50G;
            if_mode.interface_type = CTC_PORT_IF_CR2;

             /*Switch to 50G*/
            if (CTC_CHIP_SERDES_LG_MODE != port_attr->pcs_mode)
            {
                /* disable original MAC */
                enable = p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en;
                sal_memcpy(&an_ability, &(port_attr->an_ability), sizeof(sys_datapath_an_ability_t));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport, &if_mode));
                sal_memcpy(&(port_attr->an_ability), &an_ability, sizeof(sys_datapath_an_ability_t));
                /* enable LG MAC */
                if (enable)
                {
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
                }
            }
            else
            {
                port_attr->interface_type = if_mode.interface_type;
            }

            /*25/50G Ethernet Consortium Draft 3.2.5.2*/
            if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_RS))
                && (CTC_FLAG_ISSET(cstm_ability[1], SYS_PORT_CSTM_CL91_FEC_SUP)
                    && (CTC_FLAG_ISSET(local_ability.np1_ability1, SYS_PORT_CSTM_CL91_FEC_REQ)
                        ||CTC_FLAG_ISSET(remote_ability.np1_ability1, SYS_PORT_CSTM_CL91_FEC_REQ))))
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_RS528));
            }
            else if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_BASER))
                    && (CTC_FLAG_ISSET(cstm_ability[1], SYS_PORT_CSTM_CL74_FEC_SUP)
                         && (CTC_FLAG_ISSET(local_ability.np1_ability1, SYS_PORT_CSTM_CL74_FEC_REQ)
                              || CTC_FLAG_ISSET(remote_ability.np1_ability1, SYS_PORT_CSTM_CL74_FEC_REQ))))
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_FC2112));
            }
            else if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_BASER))
                    &&(CTC_FLAG_ISSET(ability[1], SYS_PORT_CL73_FEC_SUP)
                        && (CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_FEC_REQ)
                            || CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_FEC_REQ))))
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_FC2112));
            }
            else
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_NONE));
            }
        }
        else if (CTC_FLAG_ISSET(ability[0], SYS_PORT_CL73_40GBASE_CR4)
                || CTC_FLAG_ISSET(ability[0], SYS_PORT_CL73_40GBASE_KR4))
        {
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD, 6);
            /* enable Link training */
            fw_data.data_rate = CTC_CHIP_SERDES_XLG_MODE;
            fw_data.ovclk_speed = (uint8) p_hss_vec->serdes_info[logic_lane_id].overclocking_speed;

            for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
            {
                /* program different polynomials for different lanes */
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_write_reg(lchip, port_attr->multi_serdes_id[cnt],
                    POLYNOMIAL_CONFIG_ADDR, 0xE7FF, (uint16) (cnt % 4)));

                fw_data.serdes_id = port_attr->multi_serdes_id[cnt];
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_deconfig(lchip, fw_data.serdes_id));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_config(lchip, &fw_data));
            }

            if_mode.speed = CTC_PORT_SPEED_40G;
            if_mode.interface_type = CTC_PORT_IF_CR4;

            if (CTC_CHIP_SERDES_XLG_MODE != port_attr->pcs_mode)
            {
                /* disable original MAC */
                enable = p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en;
                sal_memcpy(&an_ability, &(port_attr->an_ability), sizeof(sys_datapath_an_ability_t));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport, &if_mode));
                sal_memcpy(&(port_attr->an_ability), &an_ability, sizeof(sys_datapath_an_ability_t));
                /* enable XLG MAC */
                if (enable)
                {
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
                }
            }
            else
            {
                port_attr->interface_type = if_mode.interface_type;
            }

            /*TM2 support 10G/40G BASE-R FEC*/
            if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_BASER))
                &&((CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_FEC_REQ)) || (CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_FEC_REQ)))
                &&(CTC_FLAG_ISSET(ability[1], SYS_PORT_CL73_FEC_SUP)))
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_FC2112));
            }
            else
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_NONE));
            }
        }
        else if (CTC_FLAG_ISSET(ability[0], SYS_PORT_CL73_25GBASE_CR_S)
                || CTC_FLAG_ISSET(ability[0], SYS_PORT_CL73_25GBASE_CR))
        {
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD, 7);
            /* enable Link training */
            fw_data.data_rate = CTC_CHIP_SERDES_XXVG_MODE;
            fw_data.ovclk_speed = (uint8) p_hss_vec->serdes_info[logic_lane_id].overclocking_speed;

            for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
            {
                /* program different polynomials for different lanes */
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_write_reg(lchip, port_attr->multi_serdes_id[cnt],
                    POLYNOMIAL_CONFIG_ADDR, 0xE7FF, (uint16) (cnt % 4)));

                fw_data.serdes_id = port_attr->multi_serdes_id[cnt];
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_deconfig(lchip, fw_data.serdes_id));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_config(lchip, &fw_data));
            }

            if_mode.speed = CTC_PORT_SPEED_25G;
            if_mode.interface_type = CTC_PORT_IF_CR;
             /*Switch to 25G*/
            if (CTC_CHIP_SERDES_XXVG_MODE != port_attr->pcs_mode)
            {
                /* disable original MAC */
                enable = p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en;
                sal_memcpy(&an_ability, &(port_attr->an_ability), sizeof(sys_datapath_an_ability_t));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport, &if_mode));
                sal_memcpy(&(port_attr->an_ability), &an_ability, sizeof(sys_datapath_an_ability_t));
                /* enable XLG MAC */
                if (enable)
                {
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
                }
            }
            else
            {
                port_attr->interface_type = if_mode.interface_type;
            }

            /*CL73.6.5.1*/
            if (port_attr->an_fec)
            {
                if (CTC_FLAG_ISSET(ability[0], SYS_PORT_CL73_25GBASE_CR))
                {
                    if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_RS))
                        && (CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_25G_RS_FEC_REQ)
                            ||CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_25G_RS_FEC_REQ)))
                    {
                        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_RS528));
                    }
                    else if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_BASER))
                        && (CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_25G_BASER_FEC_REQ)
                            ||CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_25G_BASER_FEC_REQ)))
                    {
                        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_FC2112));
                    }
                    else
                    {
                        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_NONE));
                    }
                }
                else if (CTC_FLAG_ISSET(ability[0], SYS_PORT_CL73_25GBASE_CR_S))
                {
                    if (CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_25G_RS_FEC_REQ)
                        ||CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_25G_RS_FEC_REQ)
                        ||CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_25G_BASER_FEC_REQ)
                        ||CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_25G_BASER_FEC_REQ))
                    {
                        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_FC2112));
                    }
                    else
                    {
                        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_NONE));
                    }
                }
            }
        }
        else if (CTC_FLAG_ISSET(cstm_ability[0], SYS_PORT_CSTM_25GBASE_KR1)
                || CTC_FLAG_ISSET(cstm_ability[0], SYS_PORT_CSTM_25GBASE_CR1))
        {
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD, 8);
            /* enable Link training */
            fw_data.data_rate = CTC_CHIP_SERDES_XXVG_MODE;
            fw_data.ovclk_speed = (uint8) p_hss_vec->serdes_info[logic_lane_id].overclocking_speed;

            for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
            {
                /* program different polynomials for different lanes */
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_write_reg(lchip, port_attr->multi_serdes_id[cnt],
                    POLYNOMIAL_CONFIG_ADDR, 0xE7FF, (uint16) (cnt % 4)));

                fw_data.serdes_id = port_attr->multi_serdes_id[cnt];
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_deconfig(lchip, fw_data.serdes_id));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_config(lchip, &fw_data));
            }

            if_mode.speed = CTC_PORT_SPEED_25G;
            if_mode.interface_type = CTC_PORT_IF_CR;
             /*Switch to 25G*/
            if (CTC_CHIP_SERDES_XXVG_MODE != port_attr->pcs_mode)
            {
                /* disable original MAC */
                enable = p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en;
                sal_memcpy(&an_ability, &(port_attr->an_ability), sizeof(sys_datapath_an_ability_t));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport, &if_mode));
                sal_memcpy(&(port_attr->an_ability), &an_ability, sizeof(sys_datapath_an_ability_t));
                /* enable XXVG MAC */
                if (enable)
                {
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
                }
            }
            else
            {
                port_attr->interface_type = if_mode.interface_type;
            }

            /*25/50G Ethernet Consortium Draft 3.2.5.2*/
            if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_RS))
                && (CTC_FLAG_ISSET(cstm_ability[1], SYS_PORT_CSTM_CL91_FEC_SUP)
                    && (CTC_FLAG_ISSET(local_ability.np1_ability1, SYS_PORT_CSTM_CL91_FEC_REQ)
                        || CTC_FLAG_ISSET(remote_ability.np1_ability1, SYS_PORT_CSTM_CL91_FEC_REQ))))
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_RS528)); 
            }
            else if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_BASER))
                && (CTC_FLAG_ISSET(cstm_ability[1], SYS_PORT_CSTM_CL74_FEC_SUP)
                    && (CTC_FLAG_ISSET(local_ability.np1_ability1, SYS_PORT_CSTM_CL74_FEC_REQ)
                        || CTC_FLAG_ISSET(remote_ability.np1_ability1, SYS_PORT_CSTM_CL74_FEC_REQ))))
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_FC2112));
            }
            else if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_BASER))
                    && (CTC_FLAG_ISSET(ability[1], SYS_PORT_CL73_FEC_SUP)
                        && (CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_FEC_REQ)
                            || CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_FEC_REQ))))
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_FC2112));
            }
            else
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_NONE));
            }
        }
        else if (CTC_FLAG_ISSET(ability[0], SYS_PORT_CL73_10GBASE_KR))
        {
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD, 9);
            /* enable Link training */
            fw_data.data_rate = CTC_CHIP_SERDES_XFI_MODE;
            fw_data.ovclk_speed = (uint8) p_hss_vec->serdes_info[logic_lane_id].overclocking_speed;

            for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
            {
                /* program different polynomials for different lanes */
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_serdes_write_reg(lchip, port_attr->multi_serdes_id[cnt],
                    POLYNOMIAL_CONFIG_ADDR, 0xE7FF, (uint16) (cnt % 4)));

                fw_data.serdes_id = port_attr->multi_serdes_id[cnt];
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_deconfig(lchip, fw_data.serdes_id));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_serdes_fw_config(lchip, &fw_data));
            }

            if_mode.speed = CTC_PORT_SPEED_10G;
            if_mode.interface_type = CTC_PORT_IF_XFI;

            if (CTC_CHIP_SERDES_XFI_MODE != port_attr->pcs_mode)
            {
                /* disable original MAC */
                enable = p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en;
                sal_memcpy(&an_ability, &(port_attr->an_ability), sizeof(sys_datapath_an_ability_t));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_tmm_mac_dynamic_switch_proc(lchip, lport, &if_mode));
                sal_memcpy(&(port_attr->an_ability), &an_ability, sizeof(sys_datapath_an_ability_t));
                /* enable XFI MAC */
                if (enable)
                {
                    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_en(lchip, lport, TRUE));
                }
            }
            else
            {
                port_attr->interface_type = if_mode.interface_type;
            }

            /*TM2 support 10G/40G BASE-R FEC*/
            if ((port_attr->an_fec & (1<<CTC_PORT_FEC_TYPE_BASER))
                &&((CTC_FLAG_ISSET(local_ability.base_ability1, SYS_PORT_CL73_FEC_REQ)) || (CTC_FLAG_ISSET(remote_ability.base_ability1, SYS_PORT_CL73_FEC_REQ)))
                &&(CTC_FLAG_ISSET(ability[1], SYS_PORT_CL73_FEC_SUP)))
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_FC2112));
            }
            else
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_an_done_fec_cfg(lchip, lport, port_attr, CTC_PORT_FEC_TYPE_NONE));
            }
        }

        SYS_CL73_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Lp base ability[0]:0x%x,[1]:0x%x, next page0[0]:0x%x,[1]:0x%x\n",
            remote_ability.base_ability0,remote_ability.base_ability1, remote_ability.np0_ability0, remote_ability.np0_ability1);

        port_attr->is_first = 1;
        port_attr->lt_done_num = 0;
    }

    port_attr->an_done_opr = FALSE;

    MAC_UNLOCK;

    SYS_CL73_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "Exit %s\n", __FUNCTION__);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_isr_linkstat_handler(uint8 lchip, uint16 lport, uint32 link_stat)
{
    ctc_port_link_status_t     port_link_status;
    CTC_INTERRUPT_EVENT_FUNC   cb        = NULL;
    uint8  gchip_id  = 0;
    uint32 gport = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    uint32 pcs_stat = 0;

    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip_id));
    gport = SYS_MAP_DRV_LPORT_TO_CTC_GPORT(gchip_id, lport);
    port_link_status.gport = gport;
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "lport %u, link_stat %u\n", lport, link_stat);

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if (NULL == port_attr)
    {
        MAC_UNLOCK;
        return CTC_E_INVALID_PARAM;
    }
    p_usw_mac_master[lchip]->mac_prop[lport].link_status = link_stat;

    if(0 == link_stat)
    {
        /*AN restart: link status up -> down*/
        if((SYS_TMM_IS_NETWORK_PORT(port_attr->port_type)) && 
          (0 != p_usw_mac_master[lchip]->mac_prop[lport].cl73_enable) && 
          (p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en))
        {
            /*ignore fault caused link down*/
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_pcs_link_status(lchip, lport, &pcs_stat));
            sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_RESTART, 2);
            if(0 == pcs_stat)
            {
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_cl73_auto_neg_en(lchip, lport, FALSE, TRUE));
                CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_cl73_auto_neg_en(lchip, lport, TRUE, TRUE));
            }
        }

        /*CPUMAC lane 2&3 reset*/
        if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type) && (TRUE == p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en))
        {
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_cpumac_lane3_pcs_rx_reset(lchip, lport, port_attr));
        }

        /*_sys_tmm_mac_sgmii_hata_reset_toggle recover*/
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_sgmii_hata_reset_recover(lchip, lport, port_attr));
    }

    MAC_UNLOCK;

    CTC_ERROR_RETURN(sys_usw_interrupt_get_event_cb(lchip, CTC_EVENT_PORT_LINK_CHANGE, &cb));
    if (cb)
    {
        cb(gchip_id, &port_link_status);
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_pcs_up_isr_linkstat(uint8 lchip, uint8 hss_index, uint8 pcs_lane, uint8 link_stat)
{
    uint8 asic_inst         = 0;
    uint8 logical_serdes_id = 0;
    uint8 is_phy            = 0;
    uint8 cs_id             = 0;
    uint8 txqm_id           = 0;
    uint8 flexe_en          = 0;
    uint8 pcs_link          = 0;
    uint32 flexe_shim_id    = 0;
    sys_datapath_serdes_info_t* p_serdes  = NULL;
    sys_datapath_lport_attr_t* port_attr = NULL;
    sys_flexe_phy_t* phy_node = NULL;

    /* Only when flexe is init, we will handle with the pcs status interrupt. */
    if (NULL == p_usw_flexe_master[lchip])
    {
        return CTC_E_NONE;
    }

    /* Only when the port is flexe port, we will handle with the pcs status interrupt. */
    logical_serdes_id = hss_index * 8 + pcs_lane;
    SYS_TMM_GET_RLMCS(logical_serdes_id, cs_id);
    SYS_TMM_FLEXE_CS_2_TXQM(cs_id, txqm_id);
    if ((2 == txqm_id) || (3 == txqm_id) || (6 == txqm_id) || (7 == txqm_id))
    {
        CTC_ERROR_RETURN(_sys_tmm_flexe_get_hw_enable(lchip, txqm_id, &flexe_en));
    }
    if (!flexe_en)
    {
        return CTC_E_NONE;
    }

    /* alarm: phy link down */
    if (!link_stat)
    {
        sys_tmm_flexe_alarm_phy_link_down(lchip, logical_serdes_id);
    }

    MAC_LOCK;
    /* get p_serdes */
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_datapath_get_serdes_info(lchip, logical_serdes_id, &p_serdes));
    if (SYS_USW_MAX_PORT_NUM_PER_CHIP <= p_serdes->lport)
    {
        MAC_UNLOCK;
        return CTC_E_NONE;
    }
    /* get port_attr */
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, p_serdes->lport, &port_attr));
    /* get pcs_link */
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_flexe_get_phy_status_by_lport(lchip, p_serdes->lport, port_attr, SYS_FLEXE_PCS_LINK, &pcs_link));
    /* operation: phy link up/down handle */
    if (pcs_link)
    {
        sys_tmm_flexe_phy_link_up_event(lchip, p_serdes->lport, port_attr);
    }
    else
    {
        sys_tmm_flexe_phy_link_down_event(lchip, p_serdes->lport, port_attr);
    }
    /* get phy node */
    phy_node = _sys_tmm_flexe_get_phy_node(lchip, logical_serdes_id);
    if (NULL != phy_node)
    {
        is_phy = 1;
        flexe_shim_id = SYS_TMM_FLEXE_GET_FLEXE_SHIM(logical_serdes_id);
        asic_inst = phy_node->inst_base;
    }    
    MAC_UNLOCK;

    /* ----------------------------------------- start ----------------------------------------- */
    /* alarm: lpf */
    sys_tmm_flexe_alarm_lpf(lchip, logical_serdes_id, pcs_link);    
    /* alarm: lof, lomf, phy link */
    if (!pcs_link && is_phy)
    {
        _sys_tmm_flexe_alarm_ohlock_ohmflock_isr(lchip, flexe_shim_id, asic_inst, 0, CTC_FLEXE_EVENT_LOF);
        _sys_tmm_flexe_alarm_ohlock_ohmflock_isr(lchip, flexe_shim_id, asic_inst, 0, CTC_FLEXE_EVENT_LOMF);
    }
    /* -----------------------------------------  end  ----------------------------------------- */

    return CTC_E_NONE;
}

int32
_sys_tmm_flexe_mac_up_isr_linkstat(uint8 lchip, uint16 mac_id, uint32* p_is_flexe)
{
    uint8  gchip_id  = 0;
    ctc_flexe_link_event_t     client_link_status;
    CTC_INTERRUPT_EVENT_FUNC   cb        = NULL;
    sys_flexe_client_t *client_node = NULL;

    if (NULL == p_usw_flexe_master[lchip])
    {
        return CTC_E_NONE;
    }

    sal_memset(&client_link_status, 0, sizeof(ctc_flexe_link_event_t));

    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip_id));

    MAC_LOCK;
    _sys_tmm_flexe_client_lookup_by_mac(lchip, mac_id, &client_node);
    if (!client_node)
    {
        SYS_USW_VALID_PTR_WRITE(p_is_flexe, FALSE);
        MAC_UNLOCK;
        return CTC_E_NONE;
    }
    SYS_USW_VALID_PTR_WRITE(p_is_flexe, TRUE);
    client_link_status.client_id = client_node->client_id;
    MAC_UNLOCK;

    /* cb */
    CTC_ERROR_RETURN(sys_usw_interrupt_get_event_cb(lchip, CTC_EVENT_FLEXE_LINK, &cb));
    if (cb)
    {
        cb(gchip_id, &client_link_status);
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_up_isr_linkstat(uint8 lchip, uint16 lport, uint16 mac_id, uint8 up_flag, uint8 down_flag)
{
    uint32  link_stat = 0;  /*1-up  0-down*/
    uint32  is_flexe  = 0;

    if((!up_flag) && (!down_flag))
    {
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(_sys_tmm_flexe_mac_up_isr_linkstat(lchip, mac_id, &is_flexe));
    if (is_flexe)
    {
        return CTC_E_NONE;
    }

    if(up_flag && down_flag)
    {
        CTC_ERROR_RETURN(sys_tmm_mac_get_link_up(lchip, lport, &link_stat, 0));
    }
    else
    {
        link_stat = up_flag ? 1 : 0;
    }

    CTC_ERROR_RETURN(_sys_tmm_mac_isr_linkstat_handler(lchip, lport, link_stat));

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_isr_cs_pcs_linkstat(uint8 lchip, uint8 hss_index, uint32 word_2_val, uint32 word_3_val)
{
    uint8   pcs_lane  = 0;
    uint8   up_flag   = 0; /* 1-up, 0-down */
    uint8   down_flag = 0; /* 1-up, 0-down */
    uint8   link_stat = 1; /* 1-up, 0-down */

    if(NULL == p_usw_datapath_master[lchip])
    {
        return CTC_E_INVALID_PTR;
    }

    if ((4 != hss_index)
        && (5 != hss_index)
        && (10 != hss_index)
        && (11 != hss_index))
    {
        return CTC_E_INVALID_PARAM;
    }

    /* pcs lane 0 ~ 6 */
    /*Retrieve lport and link stat to call handler*/
    for(pcs_lane = 0; pcs_lane < 7; pcs_lane++)
    {
        up_flag   = 0;
        down_flag = 0;
        link_stat = 0;
        if ((word_2_val >> ( 2 * pcs_lane + 18)) & 1) //link up status update
        {
            up_flag = 1;
            link_stat = 1;
        }
        if ((word_2_val >> ( 2 * pcs_lane + 17)) & 1) //link down status update
        {
            down_flag = 1;
            link_stat = 0;
        }

        if (up_flag || down_flag)
        {
            CTC_ERROR_RETURN(_sys_tmm_mac_pcs_up_isr_linkstat(lchip, hss_index, pcs_lane, link_stat));
        }
    }

    up_flag   = 0;
    down_flag = 0;
    link_stat = 0;
    
    /* pcs lane 7 */
    if (word_3_val & 1) //link up status update
    {
        up_flag = 1;
        link_stat = 1;
    }
    if ((word_2_val >> 31) & 1) //link down status update
    {
        //CTC_ERROR_RETURN(_sys_tmm_mac_pcs_down_isr_linkstat(lchip, hss_index, 7));
        down_flag = 1;
        link_stat = 0;
    }

    if (up_flag || down_flag)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_pcs_up_isr_linkstat(lchip, hss_index, 7, link_stat));
    }
    
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_isr_cs_linkstat(uint8 lchip, uint8 hss_index, uint32 word_0_val, uint32 word_1_val, uint32 word_2_val, uint32 word_3_val)
{
    uint8   inner_mii;
    uint8   up_flag   = 0;  /*1-up*/
    uint8   down_flag = 0;  /*1-down*/
    uint16  lport     = 0;
    uint16  mac_id    = 0;
    uint16  base_mac_id = 80;

    if(NULL == p_usw_datapath_master[lchip])
    {
        return CTC_E_INVALID_PTR;
    }

    if(11 < hss_index)
    {
        return CTC_E_INVALID_PARAM;
    }

    if (hss_index > 5)
    {
        base_mac_id = 240;
    }

    /*Retrieve lport and link stat to call handler*/
    for(inner_mii = 0; inner_mii < 15; inner_mii++)
    {
        up_flag   = 0;
        down_flag = 0;
        mac_id    = base_mac_id + (hss_index % 6 - 4) * 40 + inner_mii;
        lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);

        if(SYS_DATAPATH_USELESS_MAC == lport)
        {
            continue;
        }

        if ((word_0_val >> ( 2 * inner_mii + 2)) & 1) //link up status update
        {
            up_flag = 1;
        }
        if ((word_0_val >> ( 2 * inner_mii + 1)) & 1) //link down status update
        {
            down_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }

    up_flag   = 0;
    down_flag = 0;
    mac_id    = base_mac_id + (hss_index % 6 - 4) * 40 + 15;
    lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);
    if(SYS_DATAPATH_USELESS_MAC != lport)
    {
        if (word_1_val & 1) //link up status update
        {
            up_flag = 1;
        }
        if ((word_0_val >> 31) & 1) //link down status update
        {
            down_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }  

    for(inner_mii = 16; inner_mii < 31; inner_mii++)
    {
        up_flag   = 0;
        down_flag = 0;
        mac_id    = base_mac_id + (hss_index % 6 - 4) * 40 + inner_mii;
        lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);

        if(SYS_DATAPATH_USELESS_MAC == lport)
        {
            continue;
        }

        if ((word_1_val >> ( 2 * (inner_mii - 16) + 2)) & 1) //link up status update
        {
            up_flag = 1;
        }
        if ((word_1_val >> ( 2 * (inner_mii - 16) + 1)) & 1) //link down status update
        {
            down_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }

    up_flag   = 0;
    down_flag = 0;
    mac_id    = base_mac_id + (hss_index % 6 - 4) * 40 + 31;
    lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);
    if(SYS_DATAPATH_USELESS_MAC != lport)
    {
        if ((word_1_val >> 31) & 1) //link down status update
        {
            down_flag = 1;
        }

        if (word_2_val & 1) //link up status update
        {
            up_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }

    for(inner_mii = 32; inner_mii < 40; inner_mii++)
    {
        up_flag   = 0;
        down_flag = 0;
        mac_id    = base_mac_id + (hss_index % 6 - 4) * 40 + inner_mii;
        lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);

        if(SYS_DATAPATH_USELESS_MAC == lport)
        {
            continue;
        }

        if ((word_2_val >> ( 2 * (inner_mii - 32) + 2)) & 1) //link up status update
        {
            up_flag = 1;
        }
        if ((word_2_val >> ( 2 * (inner_mii - 32) + 1)) & 1) //link down status update
        {
            down_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_isr_hs_linkstat(uint8 lchip, uint8 hss_index, uint32 word_0_val, uint32 word_1_val, uint32 word_2_val)
{
    uint8   inner_mii;
    uint8   up_flag   = 0;  /*1-up*/
    uint8   down_flag = 0;  /*1-down*/
    uint16  lport     = 0;
    uint16  mac_id    = 0;
    uint16  base_mac_id = 0;

    if(NULL == p_usw_datapath_master[lchip])
    {
        return CTC_E_INVALID_PTR;
    }

    if(11 < hss_index)
    {
        return CTC_E_INVALID_PARAM;
    }

    if (hss_index > 5)
    {
        base_mac_id = 160;
    }

    /*Retrieve lport and link stat to call handler*/
    for(inner_mii = 0; inner_mii < 15; inner_mii++)
    {
        up_flag   = 0;
        down_flag = 0;
        mac_id    = base_mac_id + (hss_index % 6) * 20 + inner_mii;
        lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);

        if(SYS_DATAPATH_USELESS_MAC == lport)
        {
            continue;
        }

        if ((word_0_val >> ( 2 * inner_mii + 2)) & 1) //link up status update
        {
            up_flag = 1;
        }
        if ((word_0_val >> ( 2 * inner_mii + 1)) & 1) //link down status update
        {
            down_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }

    up_flag   = 0;
    down_flag = 0;
    mac_id    = base_mac_id + (hss_index % 6) * 20 + 15;
    lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);

    if(SYS_DATAPATH_USELESS_MAC != lport)
    {
        if (word_1_val & 1) //link up status update
        {
            up_flag = 1;
        }
        if ((word_0_val >> 31) & 1) //link down status update
        {
            down_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }  

    for(inner_mii = 16; inner_mii < 31; inner_mii++)
    {
        up_flag   = 0;
        down_flag = 0;
        mac_id    = base_mac_id + (hss_index % 6) * 20 + inner_mii;
        lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);

        if(SYS_DATAPATH_USELESS_MAC == lport)
        {
            continue;
        }

        if ((word_1_val >> ( 2 * (inner_mii - 16) + 2)) & 1) //link up status update
        {
            up_flag = 1;
        }
        if ((word_1_val >> ( 2 * (inner_mii - 16) + 1)) & 1) //link down status update
        {
            down_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }

    up_flag   = 0;
    down_flag = 0;
    mac_id    = base_mac_id + (hss_index % 6) * 20 + 31;
    lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);
    if(SYS_DATAPATH_USELESS_MAC != lport)
    {
        if ((word_1_val >> 31) & 1) //link down status update
        {
            down_flag = 1;
        }

        if (word_2_val & 1) //link up status update
        {
            up_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }

    for(inner_mii = 32; inner_mii < 40; inner_mii++)
    {
        up_flag   = 0;
        down_flag = 0;
        mac_id    = base_mac_id + (hss_index % 6) * 20 + inner_mii;
        lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);

        if(SYS_DATAPATH_USELESS_MAC == lport)
        {
            continue;
        }

        if ((word_2_val >> ( 2 * (inner_mii - 32) + 2)) & 1) //link up status update
        {
            up_flag = 1;
        }
        if ((word_2_val >> ( 2 * (inner_mii - 32) + 1)) & 1) //link down status update
        {
            down_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_isr_cpumac_linkstat(uint8 lchip, uint8 hss_index, uint32 word_0_val)
{
    uint8   inner_mii;
    uint8   up_flag   = 0;  /*1-up*/
    uint8   down_flag = 0;  /*1-down*/
    uint16  lport     = 0;
    uint16  mac_id    = 0;

    if(NULL == p_usw_datapath_master[lchip])
    {
        return CTC_E_INVALID_PTR;
    }

    for(inner_mii = 0; inner_mii < 4; inner_mii++)
    {
        up_flag   = 0;
        down_flag = 0;
        mac_id    = 320 + inner_mii;
        lport     = sys_usw_datapath_get_lport_with_mac(lchip, mac_id);

        if(SYS_DATAPATH_USELESS_MAC == lport)
        {
            continue;
        }

        if ((word_0_val >> (3 - inner_mii)) & 1) //link up status update
        {
            up_flag = 1;
        }
        if ((word_0_val >> (7 - inner_mii)) & 1) //link down status update
        {
            down_flag = 1;
        }

        CTC_ERROR_RETURN(_sys_tmm_mac_up_isr_linkstat(lchip, lport, mac_id, up_flag, down_flag));
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_isr_LT_done_isr(uint8 lchip, uint8 serdes_id)
{
    uint8 logical_serdes_id= 0;
    uint8 cnt = 0;
    uint8 lt_done = 0;
    uint16 lport = 0;
    uint16 anlt_status = 0;
    uint16 an_en_status = 0;
    uint16 lt_en_status = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    
    CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, serdes_id, &logical_serdes_id));
    SYS_CONDITION_RETURN((SYS_TMM_USELESS_ID8 == logical_serdes_id), CTC_E_INVALID_PARAM);
    CTC_ERROR_RETURN(sys_usw_datapath_get_lport_with_serdes(lchip, logical_serdes_id, &lport));
    SYS_CONDITION_RETURN(SYS_USW_MAX_PORT_NUM_PER_CHIP <= lport, CTC_E_INVALID_PARAM);
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num, CTC_E_INVALID_PARAM);
    port_attr->lt_done_num++;
    SYS_CL73_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "LT_done: serdes_id %u, lt_done_num %u, serdes_num %u\n", 
        serdes_id, port_attr->lt_done_num, port_attr->serdes_num);
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LT_DONE, (uint16)serdes_id);
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LT_DONE, (uint16)port_attr->lt_done_num);
    if (port_attr->lt_done_num == port_attr->serdes_num)
    {
        MAC_LOCK;

        lt_done = 1;

        for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
        {
            (void)sys_tmm_serdes_read_reg(lchip, port_attr->multi_serdes_id[cnt], AUTO_NEG_CONTROL_ADDR, 0, &an_en_status);
            (void)sys_tmm_serdes_read_reg(lchip, port_attr->multi_serdes_id[cnt], LINK_TRAINING_CONTROL_ADDR, 0, &lt_en_status);
            (void)sys_tmm_serdes_read_reg(lchip, port_attr->multi_serdes_id[cnt], AUTO_NEG_LINK_TRAINING_STATUS_ADDR, 0, &anlt_status);
            if ((!(an_en_status & 0x1000)) || (!(lt_en_status & 0x0002)) || (!(anlt_status & 0x0004)) || (!(anlt_status & 0x0001)))
            {
                lt_done = 0;
                SYS_CL73_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "LT_done: serdes %u, an_en 0x%x, lt_en 0x%x, status 0x%x\n", 
                    port_attr->multi_serdes_id[cnt], an_en_status, lt_en_status, anlt_status);
                sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LT_DONE_FAIL, (uint16)an_en_status);
                sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LT_DONE_FAIL, (uint16)lt_en_status);
                sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LT_DONE_FAIL, (uint16)anlt_status);
                break;
            }
        }

        if (lt_done)
        {
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_mii_rx_rst(lchip, lport, FALSE));
            CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_pcs_rx_rst(lchip, lport, FALSE));
        }

        MAC_UNLOCK;
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_isr_feature_handler(uint8 lchip, uint8 hss_index, tmm_sys_func_intr_feature_t ft_id, uint8 inner_serdes_id)
{
    uint8  cl73_ok   = TRUE;
    uint8  serdes_id = SYS_TMM_LANE_NUM_PER_HSS * hss_index + inner_serdes_id;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Pcs interrupt happened! serdes_id %u, cl73_ok %u, ft_id %u\n", serdes_id, cl73_ok, ft_id);
    switch(ft_id)
    {
        case TMM_FUNC_INTR_AN_LINK_GOOD:
            CTC_ERROR_RETURN(sys_tmm_mac_isr_cl73_complete_isr(lchip, (void*)(&serdes_id), (void*)(&cl73_ok)));
            break;
        case TMM_FUNC_INTR_TRAIN_OK:
            CTC_ERROR_RETURN(_sys_tmm_mac_isr_LT_done_isr(lchip, serdes_id));
            break;
        default:
            break;
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_isr_cs_feature_dispatch(uint8 lchip, uint8 hss_index, tmm_sys_func_intr_feature_t ft_id, uint32 word_3_val, uint32 word_4_val)
{
    uint32 word_3_mask = 0;
    uint32 temp_val = 0;
    uint8  word_3_fix_bit = 0;
    uint8  cnt;

    switch(ft_id)
    {
        case TMM_FUNC_INTR_AN_LINK_GOOD:
            word_3_mask = 0x88888888;
            word_3_fix_bit = 3;
            break;
        case TMM_FUNC_INTR_TRAIN_OK:
            word_3_mask = 0x22222222;
            word_3_fix_bit = 1;
            break;
        default:
            return CTC_E_NONE;
    }

    //word 3
    if(0 != (word_3_mask & word_3_val))
    {
        for(cnt = 0; cnt < SYS_TMM_PCS_X8_LANE_NUM; cnt++)
        {
            temp_val = word_3_val >> (4*cnt + word_3_fix_bit); // funcIntrHssLaneGpoChg_[]_gpo1Chg
            if(0 == temp_val)
            {
                break;
            }
            if(CTC_FLAG_ISSET(temp_val, 0x1))
            {
                /*
                Call feature process to handle intr.
                cnt - inner serdes id  ft_id - feature process
                */
                _sys_tmm_mac_isr_feature_handler(lchip, hss_index, ft_id, cnt);
            }
        }
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_isr_hs_feature_dispatch(uint8 lchip, uint8 hss_index, tmm_sys_func_intr_feature_t ft_id, uint32 word_2_val, uint32 word_3_val, uint32 word_4_val)
{
    uint32 word_2_mask = 0;
    uint32 word_3_mask = 0;
    uint32 word_4_mask = 0;
    uint32 temp_val = 0;
    uint8  word_2_fix_bit = 0;
    uint8  word_3_fix_bit = 0;
    uint8  word_4_fix_bit = 0;
    uint8  cnt;

    switch(ft_id)
    {
        case TMM_FUNC_INTR_AN_LINK_GOOD:
            word_2_mask = 0x88880000;
            word_3_mask = 0x88888888;
            word_4_mask = 0x00008888;
            word_2_fix_bit = 3;
            word_3_fix_bit = 3;
            word_4_fix_bit = 3;
            break;
        case TMM_FUNC_INTR_TRAIN_OK:
            word_2_mask = 0x22220000;
            word_3_mask = 0x22222222;
            word_4_mask = 0x00002222;
            word_2_fix_bit = 1;
            word_3_fix_bit = 1;
            word_4_fix_bit = 1;
            break;
        default:
            return CTC_E_NONE;
    }

    //word 2
    if(0 != (word_2_mask & word_2_val))
    {
        for(cnt = 0; cnt < 4; cnt++)
        {
            temp_val = word_2_val >> (4*cnt + word_2_fix_bit + 16); // funcIntrHssLaneGpoChg_[]_gpo1Chg
            if(0 == temp_val)
            {
                break;
            }
            if(CTC_FLAG_ISSET(temp_val, 0x1))
            {
                /*
                Call feature process to handle intr.
                cnt - inner serdes id  ft_id - feature process
                */
                _sys_tmm_mac_isr_feature_handler(lchip, hss_index, ft_id, cnt);
            }
        }
    }

    //word 3
    if(0 != (word_3_mask & word_3_val))
    {
        for(cnt = 0; cnt < 8; cnt++)
        {
            temp_val = word_3_val >> (4*cnt + word_3_fix_bit); // funcIntrHssLaneGpoChg_[]_gpo1Chg
            if(0 == temp_val)
            {
                break;
            }
            if(CTC_FLAG_ISSET(temp_val, 0x1))
            {
                /*
                Call feature process to handle intr.
                cnt - inner serdes id  ft_id - feature process
                */
                if (4 > cnt)
                {
                    _sys_tmm_mac_isr_feature_handler(lchip, hss_index, ft_id, cnt + 4);
                }
                else
                {
                    _sys_tmm_mac_isr_feature_handler(lchip, hss_index + 1, ft_id, cnt - 4);
                }
            }
        }
    }

    //word 4
    if(0 != (word_4_mask & word_4_val))
    {
        for(cnt = 0; cnt < 4; cnt++)
        {
            temp_val = word_4_val >> (4*cnt + word_4_fix_bit); // funcIntrHssLaneGpoChg_[]_gpo1Chg
            if(0 == temp_val)
            {
                break;
            }
            if(CTC_FLAG_ISSET(temp_val, 0x1))
            {
                /*
                Call feature process to handle intr.
                cnt - inner serdes id  ft_id - feature process
                */
                _sys_tmm_mac_isr_feature_handler(lchip, hss_index + 1, ft_id, cnt + 4);
            }
        }
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_isr_cpumac_feature_dispatch(uint8 lchip, uint8 hss_index, tmm_sys_func_intr_feature_t ft_id, uint32 word_0_val)
{
    uint32 word_0_mask = 0;
    uint32 temp_val = 0;
    uint8  word_0_fix_bit = 0;
    uint8  cnt;

    switch(ft_id)
    {
        case TMM_FUNC_INTR_AN_LINK_GOOD:
            word_0_mask = 0x04444000;
            word_0_fix_bit = 2;
            break;
        case TMM_FUNC_INTR_TRAIN_OK:
            word_0_mask = 0x01111000;
            word_0_fix_bit = 0;
            break;
        default:
            return CTC_E_NONE;
    }

    //word 0
    if(0 != (word_0_mask & word_0_val))
    {
        for(cnt = 0; cnt < 4; cnt++)
        {
            temp_val = word_0_val >> (4*cnt + word_0_fix_bit + 12); // funcIntrHssLaneGpoChg_[]_gpo1Chg
            if(0 == temp_val)
            {
                break;
            }
            if(CTC_FLAG_ISSET(temp_val, 0x1))
            {
                /*
                Call feature process to handle intr.
                cnt - inner serdes id  ft_id - feature process
                */
                _sys_tmm_mac_isr_feature_handler(lchip, hss_index, ft_id, cnt);
            }
        }
    }

    return CTC_E_NONE;
}

/*
pcs interrupt dispatcher
*/
STATIC int32
sys_tmm_mac_isr_pcs_dispatch(uint8 lchip, uint32 intr, void* p_data)
{
    uint32* p_bmp = (uint32*)p_data;
    uint8 hss_index = 0;
    tmm_sys_func_intr_feature_t  ft_id;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "intr %d, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", intr, p_bmp[0], p_bmp[1], p_bmp[2], p_bmp[3],p_bmp[4]);
    if((0 == p_bmp[0]) && (0 == p_bmp[1]) && (0 == p_bmp[2]) && (0 == p_bmp[3]) && (0 == p_bmp[4]))
    {
        return CTC_E_NONE;
    }

    if (CTC_IS_BIT_SET(p_bmp[0], 0) && p_usw_mac_master[lchip]->cb[SYS_MAC_INTR_TX_TS]
        && intr >= SYS_INTR_FUNC_DP0_MC_MAC0 && intr <= SYS_INTR_FUNC_DP1_MC_MAC3)
    {
        p_usw_mac_master[lchip]->cb[SYS_MAC_INTR_TX_TS](lchip, intr, p_data);
    }
    if (SYS_INTR_FUNC_DP0_MC_MAC0 == intr)
    {
        hss_index = 0;
        for(ft_id = TMM_FUNC_INTR_AN_COMPLETE; ft_id < TMM_FUNC_INTR_BUTT; ft_id++)
        {
            _sys_tmm_mac_isr_hs_feature_dispatch(lchip, hss_index, ft_id, p_bmp[2], p_bmp[3], p_bmp[4]);
        }
        _sys_tmm_mac_isr_hs_linkstat(lchip, hss_index, p_bmp[0], p_bmp[1], p_bmp[2]);
    }
    else if (SYS_INTR_FUNC_DP0_MC_MAC1 == intr)
    {
        hss_index = 2;
        for(ft_id = TMM_FUNC_INTR_AN_COMPLETE; ft_id < TMM_FUNC_INTR_BUTT; ft_id++)
        {
            _sys_tmm_mac_isr_hs_feature_dispatch(lchip, hss_index, ft_id, p_bmp[2], p_bmp[3], p_bmp[4]);
        }
        _sys_tmm_mac_isr_hs_linkstat(lchip, hss_index, p_bmp[0], p_bmp[1], p_bmp[2]);
    }
    else if (SYS_INTR_FUNC_DP0_MC_MAC2 == intr)
    {
        hss_index = 4;
        for(ft_id = TMM_FUNC_INTR_AN_COMPLETE; ft_id < TMM_FUNC_INTR_BUTT; ft_id++)
        {
            _sys_tmm_mac_isr_cs_feature_dispatch(lchip, hss_index, ft_id, p_bmp[3], p_bmp[4]);
        }
        _sys_tmm_mac_isr_cs_pcs_linkstat(lchip, hss_index, p_bmp[2], p_bmp[3]);
        _sys_tmm_mac_isr_cs_linkstat(lchip, hss_index, p_bmp[0], p_bmp[1], p_bmp[2], p_bmp[3]);
    }
    else if (SYS_INTR_FUNC_DP0_MC_MAC3 == intr)
    {
        hss_index = 5;
        for(ft_id = TMM_FUNC_INTR_AN_COMPLETE; ft_id < TMM_FUNC_INTR_BUTT; ft_id++)
        {
            _sys_tmm_mac_isr_cs_feature_dispatch(lchip, hss_index, ft_id, p_bmp[3], p_bmp[4]);
        }
        _sys_tmm_mac_isr_cs_pcs_linkstat(lchip, hss_index, p_bmp[2], p_bmp[3]);
        _sys_tmm_mac_isr_cs_linkstat(lchip, hss_index, p_bmp[0], p_bmp[1], p_bmp[2], p_bmp[3]);
    }
    else if (SYS_INTR_FUNC_DP1_MC_MAC0 == intr)
    {
        hss_index = SYS_TMM_MAX_HSS_NUM_PER_DP;
        for(ft_id = TMM_FUNC_INTR_AN_COMPLETE; ft_id < TMM_FUNC_INTR_BUTT; ft_id++)
        {
            _sys_tmm_mac_isr_hs_feature_dispatch(lchip, hss_index, ft_id, p_bmp[2], p_bmp[3], p_bmp[4]);
        }
        _sys_tmm_mac_isr_hs_linkstat(lchip, hss_index, p_bmp[0], p_bmp[1], p_bmp[2]);
    }
    else if (SYS_INTR_FUNC_DP1_MC_MAC1 == intr)
    {
        hss_index = SYS_TMM_MAX_HSS_NUM_PER_DP + 2;
        for(ft_id = TMM_FUNC_INTR_AN_COMPLETE; ft_id < TMM_FUNC_INTR_BUTT; ft_id++)
        {
            _sys_tmm_mac_isr_hs_feature_dispatch(lchip, hss_index, ft_id, p_bmp[2], p_bmp[3], p_bmp[4]);
        }
        _sys_tmm_mac_isr_hs_linkstat(lchip, hss_index, p_bmp[0], p_bmp[1], p_bmp[2]);
    }
    else if (SYS_INTR_FUNC_DP1_MC_MAC2 == intr)
    {
        hss_index = SYS_TMM_MAX_HSS_NUM_PER_DP + 4;
        for(ft_id = TMM_FUNC_INTR_AN_COMPLETE; ft_id < TMM_FUNC_INTR_BUTT; ft_id++)
        {
            _sys_tmm_mac_isr_cs_feature_dispatch(lchip, hss_index, ft_id, p_bmp[3], p_bmp[4]);
        }
        _sys_tmm_mac_isr_cs_pcs_linkstat(lchip, hss_index, p_bmp[2], p_bmp[3]);
        _sys_tmm_mac_isr_cs_linkstat(lchip, hss_index, p_bmp[0], p_bmp[1], p_bmp[2], p_bmp[3]);
    }
    else if (SYS_INTR_FUNC_DP1_MC_MAC3 == intr)
    {
        hss_index = SYS_TMM_MAX_HSS_NUM_PER_DP + 5;
        for(ft_id = TMM_FUNC_INTR_AN_COMPLETE; ft_id < TMM_FUNC_INTR_BUTT; ft_id++)
        {
            _sys_tmm_mac_isr_cs_feature_dispatch(lchip, hss_index, ft_id, p_bmp[3], p_bmp[4]);
        }
        _sys_tmm_mac_isr_cs_pcs_linkstat(lchip, hss_index, p_bmp[2], p_bmp[3]);
        _sys_tmm_mac_isr_cs_linkstat(lchip, hss_index, p_bmp[0], p_bmp[1], p_bmp[2], p_bmp[3]);
    }
    else if (SYS_INTR_FUNC_CPU_MAC == intr)
    {
        hss_index = SYS_TMM_MAX_HSS_NUM_PER_DP + 6;
        for(ft_id = TMM_FUNC_INTR_AN_COMPLETE; ft_id < TMM_FUNC_INTR_BUTT; ft_id++)
        {
            _sys_tmm_mac_isr_cpumac_feature_dispatch(lchip, hss_index, ft_id, p_bmp[0]);
        }
        _sys_tmm_mac_isr_cpumac_linkstat(lchip, hss_index, p_bmp[0]);
    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_link_up_set_slaver_speed(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr)
{
    uint32 mac_speed     = 0;
    uint32 speed         = 0;
    uint32 remote_link   = 0;
    uint32 auto_neg_en   = 0;
    uint32 auto_neg_mode = 0;
    ctc_chip_serdes_loopback_t ilb_param = {0};
    ctc_chip_serdes_loopback_t elb_param = {0};
    
    /* if serdes loopback, do nothing */
    ilb_param.serdes_id = port_attr->multi_serdes_id[0];
    ilb_param.mode = 0;
    CTC_ERROR_RETURN(sys_tmm_datapath_get_serdes_loopback(lchip, (void*)&ilb_param));
    elb_param.serdes_id = port_attr->multi_serdes_id[0];
    elb_param.mode = 1;
    CTC_ERROR_RETURN(sys_tmm_datapath_get_serdes_loopback(lchip, (void*)&elb_param));
    if (ilb_param.enable || elb_param.enable)
    {
        return CTC_E_NONE;
    }

    MAC_LOCK;
    /*cl37 enable && slave mode*/
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_cl37_en(lchip, lport, &auto_neg_en));
    if(0 == auto_neg_en)
    {
        goto UNLOCK_RET;
    }
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_cl37_mode(lchip, lport, &auto_neg_mode));
    if(CTC_PORT_AUTO_NEG_MODE_SGMII_SLAVER != auto_neg_mode)
    {
        goto UNLOCK_RET;
    }

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_usw_mac_get_cl37_an_remote_status(lchip, lport, CTC_PORT_AUTO_NEG_MODE_SGMII_SLAVER, &speed, &remote_link));
    if(FALSE == remote_link)
    {
        goto UNLOCK_RET;
    }

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_speed(lchip, lport, &mac_speed));
    if (speed == mac_speed)
    {
        goto UNLOCK_RET;
    }

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_speed(lchip, lport, speed));

UNLOCK_RET:
    MAC_UNLOCK;
    return CTC_E_NONE;
}

int32
sys_tmm_mac_link_up_event(uint8 lchip, uint16 lport)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if ((port_attr->port_type != SYS_DMPS_NETWORK_PORT) && (port_attr->port_type != SYS_DMPS_INACTIVE_NETWORK_PORT) && (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type)))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_NONE;
    }
    if (SYS_DMPS_INACTIVE_NETWORK_PORT != port_attr->port_type)
    {
        SYS_CONDITION_RETURN(FALSE == p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en, CTC_E_NONE);
    }
    if (SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type)
    {
        CTC_ERROR_RETURN(sys_tmm_flexe_phy_link_up_event(lchip, lport, port_attr));
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(sys_tmm_mac_pcs_link_fault_reset(lchip, lport));
    
    /*set speed for sgmii/qsgmii slaver mode.*/
    /*2G5 only seen as 1000base-x, so here allowed entering but do nothing.*/
    if ((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)
        || (CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode)
        || (CTC_CHIP_SERDES_QSGMII_MODE == port_attr->pcs_mode))
    {
        CTC_ERROR_RETURN(sys_tmm_mac_link_up_set_slaver_speed(lchip, lport, port_attr));
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_link_down_event(uint8 lchip, uint16 lport)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if ((port_attr->port_type != SYS_DMPS_NETWORK_PORT) && (port_attr->port_type != SYS_DMPS_INACTIVE_NETWORK_PORT) && (!SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type)))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_NONE;
    }

    if (SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type)
    {
        CTC_ERROR_RETURN(sys_tmm_flexe_phy_link_down_event(lchip, lport, port_attr));
        return CTC_E_NONE;
    }
    /*1. set mac rx pkt disable*/
    CTC_ERROR_RETURN(_sys_tmm_mac_set_mac_rx_en(lchip, port_attr->mac_id, 0));
    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_cl73_ability(uint8 lchip, uint16 lport, uint32 type, uint32* p_ability)
{
    /* get port info from sw table */
    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_cl73_ability(lchip, lport, type, p_ability));
    MAC_UNLOCK;

    return CTC_E_NONE;
}

/*set tx force fault type by mac_id*/
int32
_sys_tmm_mac_set_tx_force_fault_by_mac_id(uint8 lchip, uint16 mac_id, uint32 fault_bmp)
{
    uint32 index       = 0;
    uint32 step        = 0;
    uint32 cmd         = 0;
    uint32 fld_id      = 0;
    uint32 value       = 0;
    uint32 txqm_id     = 0;
    McMacMiiRxCfg_m    mii_rx;

    txqm_id = mac_id / SYS_TMM_MAX_MAC_NUM_PER_TXQM;
    
    /* #1, calc index */
    index = DRV_INS(txqm_id, 0);

    /* #2, read HW table: McMacMiiRxCfg_t */
    cmd     = DRV_IOR(McMacMiiRxCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_rx));

    /* ##2.1. calc step */
    step    = McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiRxForceFault_f - 
              McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault_f;
    
    /* ##2.2. modify field value */
    fld_id  = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault_f + step * SYS_TMM_GET_MACID_PER_TXQM(mac_id);
    value   = CTC_FLAG_ISSET(fault_bmp, CTC_PORT_FAULT_FORCE) ? 1 : 0;
    DRV_IOW_FIELD_NZ(lchip, McMacMiiRxCfg_t, fld_id, &value, &mii_rx, txqm_id, 0);

    /* #3, write HW table: McMacMiiRxCfg_t*/
    cmd     = DRV_IOW(McMacMiiRxCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_rx));

    return CTC_E_NONE;
}

/*set tx force fault type*/
int32
_sys_tmm_mac_set_tx_force_fault(uint8 lchip, uint16 lport, uint32 fault_bmp)
{
    uint32 index       = 0;
    uint32 cmd         = 0;
    uint32 tbl_id      = 0;
    uint32 value       = 0;
    uint32 mii_idx     = 0;
    SharedMii0Cfg_m    mii_per_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    /*check whether port is inactive network port */
    if(SYS_DMPS_INACTIVE_NETWORK_PORT == port_attr->port_type)
    {
        return CTC_E_NONE;
    }    

    if(SYS_DMPS_NETWORK_PORT == port_attr->port_type)
    {
        CTC_ERROR_RETURN(_sys_tmm_mac_set_tx_force_fault_by_mac_id(lchip, port_attr->mac_id, fault_bmp));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        mii_idx = port_attr->mii_idx;
        tbl_id = SharedMii0Cfg_t + mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));
        DRV_IOR_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxPCHLen0_f, &value, &mii_per_cfg);

        if(CTC_FLAG_ISSET(fault_bmp, CTC_PORT_FAULT_FORCE))
        {
            value |= 0x00000002;
        }
        else
        {
            value &= 0xfffffffd;
        }
        DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxPCHLen0_f, &value, &mii_per_cfg);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is invalid \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }

    return CTC_E_NONE;
}

/*get tx force fault type*/
int32
_sys_tmm_mac_get_tx_force_fault(uint8 lchip, uint16 lport, uint32* p_fault_bmp)
{
    uint32 index       = 0;
    uint32 step        = 0;
    uint32 cmd         = 0;
    uint32 tbl_id      = 0;
    uint32 fld_id      = 0;
    uint32 value       = 0;
    uint32 txqm_id     = 0;
    McMacMiiRxCfg_m    mii_rx;
    SharedMii0Cfg_m    mii_per_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if(SYS_DMPS_NETWORK_PORT == port_attr->port_type)
    {
        step    = McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiRxForceFault_f - 
                  McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault_f;
        txqm_id = port_attr->txqm_id;
        index   = DRV_INS(txqm_id, 0);
        fld_id  = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxForceFault_f + step * SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);

        cmd     = DRV_IOR(McMacMiiRxCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_rx));
        DRV_IOR_FIELD(lchip, McMacMiiRxCfg_t, fld_id, &value, &mii_rx);
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        tbl_id = SharedMii0Cfg_t + port_attr->mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));
        DRV_IOR_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxPCHLen0_f, &value, &mii_per_cfg);
        value = CTC_FLAG_ISSET(value, 0x00000002) ? 1 : 0;
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is invalid \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }

    *p_fault_bmp &= (~((uint32)CTC_PORT_FAULT_FORCE)); /*clear bit 3 to 0*/
    if(0 != value) /*set bit 3*/
    {
        *p_fault_bmp |= CTC_PORT_FAULT_FORCE;
    }

    return CTC_E_NONE;
}


int32
_sys_tmm_mac_get_link_fault(uint8 lchip, uint16 lport, uint32 *p_value)
{
    uint8 mii_idx                    = 0;
    uint8 txqm_mac_id                = 0;
    uint32 index                     = 0;
    uint32 step                      = 0;
    uint32 cmd                       = 0;
    uint32 tbl_id                    = 0;
    uint32 fld_id                    = 0;
    uint32 value                     = 0;
    uint32 fault_bitmap              = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if(SYS_DMPS_NETWORK_PORT == port_attr->port_type)
    {
        txqm_mac_id = TXQM_INNER_MAC_ID(port_attr->mac_id);
        index = DRV_INS(port_attr->txqm_id, 0);
        tbl_id = McMacMiiRxDebugStats_t;
        step = McMacMiiRxDebugStats_dbgMcMacMiiRx_1_dbgMiiRxFaultType_f - McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxFaultType_f;
        fld_id = McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxFaultType_f + step* txqm_mac_id;

        cmd = DRV_IOR(tbl_id, fld_id);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        index = 0;
        mii_idx = port_attr->mii_idx;
        step  = SharedMii1Status_t - SharedMii0Status_t;
        tbl_id = SharedMii0Status_t + mii_idx*step;
        
        cmd = DRV_IOR(tbl_id, SharedMii0Status_dbgMiiRxFaultType0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% MAC %d is not used \n", port_attr->mac_id);
        return CTC_E_INVALID_PORT;
    }

    fault_bitmap = (value ? (0x0 | (0x1 << (value - 1))) : 0);
    *p_value = (((*p_value) & 0xfffffff8) | (fault_bitmap & 0x00000007));

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_link_fault(uint8 lchip, uint16 lport, uint32 *p_value)
{

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "lport:%u, ", lport);

    if (NULL == p_usw_mac_master[lchip])
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_fault(lchip, lport, p_value));
    MAC_UNLOCK;

    return CTC_E_NONE;
}
/**
@brief    Get port's properties according to gport id
*/

int32 
sys_tmm_mac_get_fec_cnt(uint8 lchip, uint16 lport, ctc_port_fec_cnt_t* fec_cnt)
{
    uint8  lane_id = 0;
    uint8  hss_id = 0;
    uint32 cmd = 0;
    uint32 fld_id[2] = {0,0};
    uint32 tbl_id    = 0;
    uint32 step = 0;
    uint32 correct_cnt = 0;
    uint32 uncorrect_cnt = 0;
    uint32 index = 0;
    uint32 fec_val = 0;
    uint8 serdes_num = 0;
    uint16 logical_serdes_id = 0;
    uint32 value = 0;
    uint32 value2 = 0;
    uint32 addr_c = 0;
    uint32 addr_uc = 0;
    uint8  i = 0;
    uint32 correct_cnt_i = 0;
    uint32 uncorrect_cnt_i = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    RsFec0StatusSharedFec_m cpumacrsstats;
    XgFec1StatusSharedFec_m cpumacfcstats;

    CTC_ERROR_RETURN(sys_usw_datapath_get_serdes_with_lport(lchip, lport, &logical_serdes_id, &serdes_num));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "lport:%u\n", lport);

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logical_serdes_id);
    CTC_ERROR_RETURN(_sys_tmm_mac_get_fec_en(lchip, lport, &fec_val));
    if(SYS_TMM_IS_PCS_X16(port_attr->txqm_id))
    {
        lane_id   =  logical_serdes_id % (2*SYS_TMM_LANE_NUM_PER_HSS);    
    }
    else
    {
        lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);
    }
    if(CTC_PORT_FEC_TYPE_NONE == fec_val)    /*FEC : None*/
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " lport %d FEC is not enable.\n",lport);
        return  CTC_E_INVALID_PARAM;
    }
    if(SYS_TMM_CPUMAC_HSS_ID == hss_id)
    {
        if((CTC_PORT_FEC_TYPE_RS == fec_val) || (CTC_PORT_FEC_TYPE_RS528 == fec_val) || (CTC_PORT_FEC_TYPE_RS544 == fec_val) || (CTC_PORT_FEC_TYPE_RS272 == fec_val)) 
        {
            step = RsFec1StatusSharedFec_t - RsFec0StatusSharedFec_t;
            tbl_id = RsFec0StatusSharedFec_t + lane_id * step;
            fld_id[0] = RsFec0StatusSharedFec_dbgRsFec0UnCoCwCount_f;
            fld_id[1] = RsFec0StatusSharedFec_dbgRsFec0CorrCwCount_f;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumacrsstats));
            DRV_IOR_FIELD(lchip, tbl_id, fld_id[0], &uncorrect_cnt, &cpumacrsstats);
            DRV_IOR_FIELD(lchip, tbl_id, fld_id[1], &correct_cnt, &cpumacrsstats);
        }          
        else
        {
            if(CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
            {
                step = XgFec2StatusSharedFec_t - XgFec0StatusSharedFec_t;
                for(tbl_id = XgFec0StatusSharedFec_t;tbl_id <= XgFec6StatusSharedFec_t;tbl_id += step)
                {
                    fld_id[0] = XgFec0StatusSharedFec_dbgXgFec0UncoBlkCnt_f;
                    fld_id[1] = XgFec0StatusSharedFec_dbgXgFec0CorrBlkCnt_f;
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumacfcstats));
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id[0], &value, &cpumacfcstats);
                    DRV_IOR_FIELD(lchip, tbl_id, fld_id[1], &value2, &cpumacfcstats);
                    uncorrect_cnt += value;
                    correct_cnt += value2;
                }
            }
            else if(CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
            {
                step = XgFec1StatusSharedFec_t - XgFec0StatusSharedFec_t;
                if(2 <= lane_id)
                {           
                    for(tbl_id = XgFec4StatusSharedFec_t;tbl_id <= XgFec7StatusSharedFec_t;tbl_id += step)
                    {
                        fld_id[0] = XgFec0StatusSharedFec_dbgXgFec0UncoBlkCnt_f;
                        fld_id[1] = XgFec0StatusSharedFec_dbgXgFec0CorrBlkCnt_f;
                        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumacfcstats));
                        DRV_IOR_FIELD(lchip, tbl_id, fld_id[0], &value, &cpumacfcstats);
                        DRV_IOR_FIELD(lchip, tbl_id, fld_id[1], &value2, &cpumacfcstats);
                        uncorrect_cnt += value;
                        correct_cnt += value2;
                    }
                }
                else
                {
                    for(tbl_id = XgFec0StatusSharedFec_t;tbl_id <= XgFec3StatusSharedFec_t;tbl_id += step)
                    {
                        fld_id[0] = XgFec0StatusSharedFec_dbgXgFec0UncoBlkCnt_f;
                        fld_id[1] = XgFec0StatusSharedFec_dbgXgFec0CorrBlkCnt_f;
                        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumacfcstats));
                        DRV_IOR_FIELD(lchip, tbl_id, fld_id[0], &value, &cpumacfcstats);
                        DRV_IOR_FIELD(lchip, tbl_id, fld_id[1], &value2, &cpumacfcstats);
                        uncorrect_cnt += value;
                        correct_cnt += value2;
                    }
                }
            }
            else
            {               
                step = XgFec2StatusSharedFec_t - XgFec0StatusSharedFec_t;
                tbl_id = XgFec0StatusSharedFec_t + lane_id * step;
                fld_id[0] = XgFec0StatusSharedFec_dbgXgFec0UncoBlkCnt_f;
                fld_id[1] = XgFec0StatusSharedFec_dbgXgFec0CorrBlkCnt_f;
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumacfcstats));
                DRV_IOR_FIELD(lchip, tbl_id, fld_id[0], &uncorrect_cnt, &cpumacfcstats);
                DRV_IOR_FIELD(lchip, tbl_id, fld_id[1], &correct_cnt, &cpumacfcstats);
            }
        }
    }
    else
    {
        for(i = 0; i < serdes_num; i++)
        {
            switch(hss_id)
            {
                case 0:
                case 1:
                    addr_c  = 0x62450004 + 12*(lane_id + i);
                    addr_uc = 0x62450008 + 12*(lane_id + i);
                    break;
                case 2:
                case 3:
                    addr_c  = 0x624d0004 + 12*(lane_id + i);
                    addr_uc = 0x624d0008 + 12*(lane_id + i);
                    break;
                case 6:
                case 7:
                    addr_c  = 0x6a450004 + 12*(lane_id + i);
                    addr_uc = 0x6a450008 + 12*(lane_id + i);
                    break;
                case 8:
                case 9:
                    addr_c  = 0x6a4d0004 + 12*(lane_id + i);
                    addr_uc = 0x6a4d0008 + 12*(lane_id + i);
                    break;
               
                case 4:
                    addr_c  = 0x61090400 + 12*(lane_id + i);
                    addr_uc = 0x61090408 + 12*(lane_id + i);
                    break;
                case 5:
                    addr_c  = 0x61091400 + 12*(lane_id + i);
                    addr_uc = 0x61091408 + 12*(lane_id + i);
                    break;
                case 10:
                    addr_c  = 0x69090400 + 12*(lane_id + i);
                    addr_uc = 0x69090408 + 12*(lane_id + i);
                    break;
                case 11:
                    addr_c  = 0x69091400 + 12*(lane_id + i);
                    addr_uc = 0x69091408 + 12*(lane_id + i);
                    break;
                default:
                    break;
            }
            CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_c, &correct_cnt_i));
            CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr_uc, &uncorrect_cnt_i));
            correct_cnt += correct_cnt_i;
            uncorrect_cnt += uncorrect_cnt_i;
            SYS_CONDITION_BREAK(!(((CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode) || 
                (CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)) && 
                (CTC_PORT_FEC_TYPE_FC2112 == fec_val)));
        }
    }
    fec_cnt->correct_cnt = correct_cnt;
    fec_cnt->uncorrect_cnt = uncorrect_cnt;
    return  CTC_E_NONE;
}

int32
sys_tmm_mac_get_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32* p_value)
{
    int32  ret = CTC_E_NONE;
    ctc_port_speed_t port_speed = CTC_PORT_SPEED_1G;
     /*uint32 value = 0;*/
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get port property, lport:%u, property:%d!\n", lport, port_prop);

    /*Sanity check*/
    SYS_MAC_INIT_CHECK();
    CTC_PTR_VALID_CHECK(p_value);
    /* zero value */
    *p_value = 0;

    switch (port_prop)
    {
    case CTC_PORT_PROP_MAC_EN:
        ret = sys_usw_mac_get_mac_en(lchip, lport, p_value);
        break;

    case CTC_PORT_PROP_LINK_UP:
        ret = sys_tmm_mac_get_link_up(lchip, lport, p_value, 1);
        break;

    case CTC_PORT_PROP_FEC_EN:
        ret = sys_tmm_mac_get_fec_en(lchip, lport, p_value);
        break;
    case CTC_PORT_PROP_CL73_ABILITY:
        ret = sys_tmm_mac_get_cl73_ability(lchip, lport, 0, p_value);
        break;

    case CTC_PORT_PROP_SIGNAL_DETECT:
        ret = sys_tmm_mac_get_mac_signal_detect(lchip, lport, p_value);
        break;

    case CTC_PORT_PROP_LINK_INTRRUPT_EN:
        ret = sys_tmm_mac_get_link_intr(lchip, lport, p_value);
        break;

    case CTC_PORT_PROP_AUTO_NEG_EN:
        ret = sys_tmm_mac_get_auto_neg(lchip, lport, port_prop, p_value);
        break;

    case CTC_PORT_PROP_AUTO_NEG_MODE:
        ret = sys_tmm_mac_get_auto_neg(lchip, lport, port_prop, p_value);
        break;

    case CTC_PORT_PROP_AUTO_NEG_FEC:
        ret = sys_tmm_mac_get_auto_neg(lchip, lport, port_prop, p_value);
        break;
        
    case CTC_PORT_PROP_FEC_CNT:
        ret = sys_tmm_mac_get_fec_cnt(lchip, lport, (ctc_port_fec_cnt_t*)p_value);
        break;
    case CTC_PORT_PROP_SPEED:
        ret = sys_tmm_mac_get_speed(lchip, lport, &port_speed);
        if (CTC_E_NONE == ret)
        {
            *p_value = port_speed;
        }
        break;

    case CTC_PORT_PROP_PREAMBLE:
    case CTC_PORT_PROP_PADING_EN:
    case CTC_PORT_PROP_CHK_CRC_EN:
    case CTC_PORT_PROP_STRIP_CRC_EN:
    case CTC_PORT_PROP_APPEND_CRC_EN:
    case CTC_PORT_PROP_APPEND_TOD_EN:
        ret = sys_tmm_mac_get_internal_property(lchip, lport, port_prop, p_value);
        break;

    case CTC_PORT_PROP_LINKSCAN_EN:
        *p_value = 1;
        break;

    case CTC_PORT_PROP_UNIDIR_EN:
        ret = sys_tmm_mac_get_unidir_en(lchip, lport, p_value);
        break;

    case CTC_PORT_PROP_MAC_TX_IPG:
        ret = sys_tmm_mac_get_ipg(lchip, lport, p_value);
        break;

    case CTC_PORT_PROP_XPIPE_EN:
        ret = sys_tmm_mac_get_xpipe_en(lchip, lport, p_value);
        break;

    case CTC_PORT_PROP_MAC_TS_EN:
        ret = sys_tmm_mac_get_tailts_en(lchip, lport, p_value);
        break;

    case CTC_PORT_PROP_FAULT:
        ret = sys_tmm_mac_get_link_fault(lchip, lport, p_value);
        break;

    case CTC_PORT_PROP_PAR_DET_EN:
        ret = sys_tmm_mac_get_parallel_detect_en(lchip, lport, p_value);
        break;

    case CTC_PORT_PROP_ERROR_CHECK:
    case CTC_PORT_PROP_RX_PAUSE_TYPE:
    default:
        return CTC_E_NOT_SUPPORT;
    }

    return ret;
}


#define  __TMM_MAC_THREAD__
uint8
_sys_tmm_mac_monitor_is_an_restart(uint8 lchip, uint16 lport, sys_datapath_lport_attr_t* port_attr)
{
    uint32 pcs_stat    = 0;
    uint16 an_hcd      = 0;
    uint8  an_restart  = FALSE;
    uint32 cl72_status = 0;
    uint8  cnt         = 0;
    uint8  tx_en       = 0;

    (void)_sys_tmm_mac_get_pcs_link_status(lchip, lport, &pcs_stat);
    if(0 != pcs_stat)
    {
        return FALSE;
    }

    /*skip tx disabled port*/
    for(cnt = 0; cnt < port_attr->serdes_num; cnt++)
    {
        tx_en = 0;
        (void)sys_tmm_serdes_get_tx_en(lchip, port_attr->multi_serdes_id[cnt], &tx_en);
        if(0 == tx_en) break;
    }
    if(0 == tx_en)
    {
        return FALSE;
    }

    /* old_cl73_status[1:0]:
     * bit 0 -- LT extra period flag. To give LT one more cycle.
     * bit 1 -- AN extra period flag. For some conditions HCD reaches OK slowly, and giving one more cycle.
     * bit 2 -- LT_DONE extra period flag. PAM4 training timer 3s so PCS SYNC cannot finish in this period.
     * value 0 -- extra period is not running
     * value 1 -- extra period is running
     */
    (void)_sys_usw_mac_get_3ap_training_en(lchip, lport, &cl72_status);
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_LT_STAT, (uint16)cl72_status);
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_PRV_CL73_STAT, 
        (uint16)p_usw_mac_master[lchip]->mac_prop[lport].old_cl73_status);
    switch(cl72_status)
    {
        case SYS_PORT_CL72_FAIL:
            an_restart = TRUE;
            break;
        case SYS_PORT_CL72_PROGRESS:
            if(CTC_IS_BIT_SET(p_usw_mac_master[lchip]->mac_prop[lport].old_cl73_status, 2))
            {
                an_restart = TRUE;
            }
            else
            {
                CTC_BIT_SET(p_usw_mac_master[lchip]->mac_prop[lport].old_cl73_status, 2);
            }
            break;
        case SYS_PORT_CL72_OK:
            if(CTC_IS_BIT_SET(p_usw_mac_master[lchip]->mac_prop[lport].old_cl73_status, 0))
            {
                an_restart = TRUE;
            }
            else
            {
                CTC_BIT_SET(p_usw_mac_master[lchip]->mac_prop[lport].old_cl73_status, 0);
            }
            break;
        case SYS_PORT_CL72_DISABLE:
        default:
            if(CTC_IS_BIT_SET(p_usw_mac_master[lchip]->mac_prop[lport].old_cl73_status, 1))
            {
                an_restart = TRUE;
            }
            else
            {
                for(cnt = 0; cnt < port_attr->serdes_num; cnt++)
                {
                    an_hcd = 0;
                    (void)sys_tmm_serdes_read_reg(lchip, port_attr->multi_serdes_id[cnt], 
                        AUTO_NEG_LINK_TRAINING_STATUS_ADDR, 0xfffe, &an_hcd);
                    SYS_CONDITION_BREAK(1 == an_hcd);
                }
                sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_HCD_MNT, (uint16)an_hcd);
                if(0 == an_hcd)
                {
                    CTC_BIT_SET(p_usw_mac_master[lchip]->mac_prop[lport].old_cl73_status, 1);
                }
                else
                {
                    an_restart = TRUE;
                }
            }
            break;
    }

    if(an_restart)
    {
        p_usw_mac_master[lchip]->mac_prop[lport].old_cl73_status = 0;
    }
    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_PRV_CL73_STAT, 
        (uint16)p_usw_mac_master[lchip]->mac_prop[lport].old_cl73_status);

    return an_restart;
}

int32
_sys_tmm_mac_monitor_cl37_linkdown_toggle(uint8 lchip, uint16 lport, uint32 is_up)
{
    uint32 cl37_en = 0;

    CTC_ERROR_RETURN(_sys_tmm_mac_get_cl37_en(lchip, lport, &cl37_en));
    SYS_CONDITION_RETURN(!cl37_en, CTC_E_NONE);
    
    if(cl37_en && (!is_up))
    {
        sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_CL37_RESTART, 1);
        CTC_ERROR_RETURN(_sys_tmm_mac_set_cl37_auto_neg_en(lchip, lport, FALSE));
        CTC_ERROR_RETURN(_sys_tmm_mac_set_cl37_auto_neg_en(lchip, lport, TRUE));
    }

    return CTC_E_NONE;
}

void
_sys_tmm_mac_monitor_thread(void* para)
{
    uint8  lchip       = (uintptr)para;
    uint8  gchip       = 0;
    uint16 lport       = 0;
    int32  ret         = 0;
    uint32 is_up       = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    uint8  cnt         = 0;

    (void)sys_usw_get_gchip_id(lchip, &gchip);
    SYS_LCHIP_CHECK_ACTIVE_START_THREAD(lchip);

    while(1)
    {        
        for (lport = 0; lport < SYS_USW_MAX_PORT_NUM_PER_CHIP; lport++)
        {
            SYS_LCHIP_CHECK_ACTIVE_IN_THREAD(lchip);
            SYS_CHIP_CHECK_RESET_HW_IN_THREAD(lchip);
            if(p_usw_mac_master[lchip]->polling_status == 0)
            {
                continue;
            }

            MAC_LOCK;
            /*check mac used */
            ret = sys_usw_mac_get_port_capability(lchip, lport, &port_attr);
            if((!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type)) || ret)
            {
                MAC_UNLOCK;
                continue;
            }

            /*check mac enable */
            if((FALSE == p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en) && (port_attr->port_type != SYS_DMPS_INACTIVE_NETWORK_PORT))
            {
                MAC_UNLOCK;
                continue;
            }

            if(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num)
            {
                MAC_UNLOCK;
                continue;
            }
            
            (void)_sys_tmm_mac_get_link_up_raw(lchip, lport, &is_up);

            /* restart CL73 AN */
            if(p_usw_mac_master[lchip]->mac_prop[lport].cl73_enable)
            {
                if(_sys_tmm_mac_monitor_is_an_restart(lchip, lport, port_attr))
                {
                    sys_usw_mac_link_log_record(lchip, lport, SYS_MAC_LOG_AN_RESTART, 1);
                    (void)_sys_tmm_mac_set_cl73_auto_neg_en(lchip, lport, FALSE, TRUE);
                    (void)_sys_tmm_mac_set_cl73_auto_neg_en(lchip, lport, TRUE,  TRUE);
                }
            }
            else
            {
                /*serdes fw tuning timeout/bkg error recover*/
                for (cnt = 0; cnt < port_attr->serdes_num; cnt++)
                {
                    (void)_sys_tmm_serdes_fw_tuning_recover(lchip, lport, port_attr->multi_serdes_id[cnt], port_attr->pcs_mode);
                }

                /*cpumac lane 2 & 3 pcs reset control*/
                (void)_sys_tmm_cpumac_lane3_pcs_rx_reset(lchip, lport, port_attr);

                /*link up -> down*/
                if((1 == p_usw_mac_master[lchip]->mac_prop[lport].link_status) && (0 == is_up))
                {
                    (void)_sys_tmm_mac_sgmii_hata_reset_recover(lchip, lport, port_attr);
                }

                /*cl37 linkdown toggle*/
                (void)_sys_tmm_mac_monitor_cl37_linkdown_toggle(lchip, lport, is_up);
            }

            p_usw_mac_master[lchip]->mac_prop[lport].link_status = is_up;

            MAC_UNLOCK;
            sal_task_sleep(1);
        }

        sal_task_sleep(3000);
    }
//#endif
}

STATIC int32
_sys_tmm_mac_monitor_link(uint8 lchip)
{
//#if 0
    drv_work_platform_type_t platform_type;
    int32 ret = 0;
    uintptr chip_id = lchip;
    uint64 cpu_mask = 0;
    uint32 cmd = 0;
    uint32 field_val = 0;

    if (sys_usw_chip_get_reset_hw_en(lchip))
    {
        return CTC_E_NONE;
    }
    CTC_ERROR_RETURN(drv_get_platform_type(lchip, &platform_type));
    if (platform_type != HW_PLATFORM)
    {
        return CTC_E_NONE;
    }

    sal_memset(p_usw_mac_master[lchip]->scan_log, 0, sizeof(sys_usw_scan_log_t)*SYS_PORT_MAX_LOG_NUM);

    cpu_mask = sys_usw_chip_get_affinity(lchip, 0);
    ret = sys_usw_task_create(lchip,&(p_usw_mac_master[lchip]->p_monitor_scan), "ctclnkMon",
                          SAL_DEF_TASK_STACK_SIZE, SAL_TASK_PRIO_DEF, SAL_TASK_TYPE_LINK_SCAN,cpu_mask, _sys_tmm_mac_monitor_thread, (void*)chip_id);
    if (ret < 0)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    p_usw_mac_master[lchip]->polling_status = 1;

    field_val = 1;
    cmd = DRV_IOW(OobFcReserved_t, OobFcReserved_reserved_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
//#endif

    return CTC_E_NONE;
}


#define  __TMM_MAC_INIT__



/**
 @brief initialize the port module
*/
int32
sys_tmm_mac_init(uint8 lchip)
{
    uint32 cmd = 0;
#ifdef EMULATION_ENV
    uint32 val_flt = 0x9c01;
#else
    uint32 val_flt = 0x003d0900; /*100us per cycle, 0.1ms*/
#endif
    uint8  cnt = 0;
    uint32 index = 0;
    //uint32 bitmap_cs[5] = {0xFFFFFFFE, 0xFFFFFFFF, 0x0001FFFF, 0xAAAAAAAA, 0x0};
    uint32 bitmap_cs[5] = {0xFFFFFFFE, 0xFFFFFFFF, 0xFFFFFFFF, 0xAAAAAAAB, 0x0};
    uint32 bitmap_hs[5] = {0xFFFFFFFE, 0xFFFFFFFF, 0xAAABFFFF, 0xAAAAAAAA, 0x0000AAAA};
    uint32 cpumac_bitmap = 0x055550FF;
    RefDivMcPcsLinkPulse_m rd_pcs;
    RefDivMcMacPulse_m     rd_mac;
    RefDivCpuMacPulse_m    rd_cpumac;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    /* Enlarge link Filter */
    cmd = DRV_IOR(RefDivMcPcsLinkPulse_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rd_pcs));
    DRV_IOW_FIELD(lchip, RefDivMcPcsLinkPulse_t, RefDivMcPcsLinkPulse_cfgRefDivMcMac0Dp0McPcsLinkPulse_f, &val_flt, &rd_pcs);
    DRV_IOW_FIELD(lchip, RefDivMcPcsLinkPulse_t, RefDivMcPcsLinkPulse_cfgRefDivMcMac0Dp1McPcsLinkPulse_f, &val_flt, &rd_pcs);
    DRV_IOW_FIELD(lchip, RefDivMcPcsLinkPulse_t, RefDivMcPcsLinkPulse_cfgRefDivMcMac1Dp0McPcsLinkPulse_f, &val_flt, &rd_pcs);
    DRV_IOW_FIELD(lchip, RefDivMcPcsLinkPulse_t, RefDivMcPcsLinkPulse_cfgRefDivMcMac1Dp1McPcsLinkPulse_f, &val_flt, &rd_pcs);
    DRV_IOW_FIELD(lchip, RefDivMcPcsLinkPulse_t, RefDivMcPcsLinkPulse_cfgRefDivMcMac2Dp0McPcsLinkPulse_f, &val_flt, &rd_pcs);
    DRV_IOW_FIELD(lchip, RefDivMcPcsLinkPulse_t, RefDivMcPcsLinkPulse_cfgRefDivMcMac2Dp1McPcsLinkPulse_f, &val_flt, &rd_pcs);
    DRV_IOW_FIELD(lchip, RefDivMcPcsLinkPulse_t, RefDivMcPcsLinkPulse_cfgRefDivMcMac3Dp0McPcsLinkPulse_f, &val_flt, &rd_pcs);
    DRV_IOW_FIELD(lchip, RefDivMcPcsLinkPulse_t, RefDivMcPcsLinkPulse_cfgRefDivMcMac3Dp1McPcsLinkPulse_f, &val_flt, &rd_pcs);
    cmd = DRV_IOW(RefDivMcPcsLinkPulse_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rd_pcs));

    cmd = DRV_IOR(RefDivMcMacPulse_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rd_mac));
    DRV_IOW_FIELD(lchip, RefDivMcMacPulse_t, RefDivMcMacPulse_cfgRefDivMcMac0Dp0LinkFilterPulse_f, &val_flt, &rd_mac);
    DRV_IOW_FIELD(lchip, RefDivMcMacPulse_t, RefDivMcMacPulse_cfgRefDivMcMac0Dp1LinkFilterPulse_f, &val_flt, &rd_mac);
    DRV_IOW_FIELD(lchip, RefDivMcMacPulse_t, RefDivMcMacPulse_cfgRefDivMcMac1Dp0LinkFilterPulse_f, &val_flt, &rd_mac);
    DRV_IOW_FIELD(lchip, RefDivMcMacPulse_t, RefDivMcMacPulse_cfgRefDivMcMac1Dp1LinkFilterPulse_f, &val_flt, &rd_mac);
    DRV_IOW_FIELD(lchip, RefDivMcMacPulse_t, RefDivMcMacPulse_cfgRefDivMcMac2Dp0LinkFilterPulse_f, &val_flt, &rd_mac);
    DRV_IOW_FIELD(lchip, RefDivMcMacPulse_t, RefDivMcMacPulse_cfgRefDivMcMac2Dp1LinkFilterPulse_f, &val_flt, &rd_mac);
    DRV_IOW_FIELD(lchip, RefDivMcMacPulse_t, RefDivMcMacPulse_cfgRefDivMcMac3Dp0LinkFilterPulse_f, &val_flt, &rd_mac);
    DRV_IOW_FIELD(lchip, RefDivMcMacPulse_t, RefDivMcMacPulse_cfgRefDivMcMac3Dp1LinkFilterPulse_f, &val_flt, &rd_mac);
    cmd = DRV_IOW(RefDivMcMacPulse_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rd_mac));

    cmd = DRV_IOR(RefDivCpuMacPulse_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rd_cpumac));
    DRV_IOW_FIELD(lchip, RefDivCpuMacPulse_t, RefDivCpuMacPulse_cfgRefDivCpuMacLinkPulse_f,       &val_flt, &rd_cpumac);
    DRV_IOW_FIELD(lchip, RefDivCpuMacPulse_t, RefDivCpuMacPulse_cfgRefDivCpuMacLinkFilterPulse_f, &val_flt, &rd_cpumac);
    cmd = DRV_IOW(RefDivCpuMacPulse_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &rd_cpumac));

    for (cnt = 0; cnt < 4; cnt++)
    {
        /*clear link intr*/
        index = DRV_INS(cnt, 1);
        cmd = DRV_IOW(CtcHsCtlInterruptFunc_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, bitmap_hs));
        /*unmask link intr*/
        index = DRV_INS(cnt, 3);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, bitmap_hs));

        index = DRV_INS(cnt, 1);
        cmd = DRV_IOW(CtcCsCtlInterruptFunc_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, bitmap_cs));
        index = DRV_INS(cnt, 3);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, bitmap_cs));
    }

    index = DRV_INS(0, 1);
    cmd = DRV_IOW(CpuMacProcInterruptFunc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_bitmap));
    index = DRV_INS(0, 3);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cpumac_bitmap));

    /* mac config init */
    CTC_ERROR_RETURN(_sys_tmm_mac_init_mac_config(lchip));

    CTC_ERROR_RETURN(_sys_tmm_mac_monitor_link(lchip));

    CTC_ERROR_RETURN(sys_usw_interrupt_register_isr(lchip, SYS_INTR_FUNC_DP0_MC_MAC0, sys_tmm_mac_isr_pcs_dispatch));
    CTC_ERROR_RETURN(sys_usw_interrupt_register_isr(lchip, SYS_INTR_FUNC_DP0_MC_MAC1, sys_tmm_mac_isr_pcs_dispatch));
    CTC_ERROR_RETURN(sys_usw_interrupt_register_isr(lchip, SYS_INTR_FUNC_DP0_MC_MAC2, sys_tmm_mac_isr_pcs_dispatch));
    CTC_ERROR_RETURN(sys_usw_interrupt_register_isr(lchip, SYS_INTR_FUNC_DP0_MC_MAC3, sys_tmm_mac_isr_pcs_dispatch));
    CTC_ERROR_RETURN(sys_usw_interrupt_register_isr(lchip, SYS_INTR_FUNC_DP1_MC_MAC0, sys_tmm_mac_isr_pcs_dispatch));
    CTC_ERROR_RETURN(sys_usw_interrupt_register_isr(lchip, SYS_INTR_FUNC_DP1_MC_MAC1, sys_tmm_mac_isr_pcs_dispatch));
    CTC_ERROR_RETURN(sys_usw_interrupt_register_isr(lchip, SYS_INTR_FUNC_DP1_MC_MAC2, sys_tmm_mac_isr_pcs_dispatch));
    CTC_ERROR_RETURN(sys_usw_interrupt_register_isr(lchip, SYS_INTR_FUNC_DP1_MC_MAC3, sys_tmm_mac_isr_pcs_dispatch));
    CTC_ERROR_RETURN(sys_usw_interrupt_register_isr(lchip, SYS_INTR_FUNC_CPU_MAC, sys_tmm_mac_isr_pcs_dispatch));

    if (CTC_WB_ENABLE(lchip) && (CTC_WB_STATUS(lchip) == CTC_WB_STATUS_RELOADING))
    {
        CTC_ERROR_RETURN(sys_usw_mac_wb_restore(lchip));
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_check_hiber_error_block(uint8 lchip, uint8 logical_serdes_id, uint16 lport, uint32* hiber_value, uint32* error_block)
{
    uint8  hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logical_serdes_id);
    uint8  lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);
    uint32 tbl_id    = 0;
    uint32 fld_id    = 0;
    uint32 cmd       = 0;
    uint32 index     = 0;
    uint16 factor    = 0;
    uint16 step      = 0;
    uint8  flag      = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    factor = SYS_TMM_GET_MACID_PER_TXQM(port_attr->mac_id);

    /*hiber*/
    if(SYS_TMM_CPUMAC_HSS_ID == hss_id)
    {
        if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)||(CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            flag = 1;
        }
        else
        {
            index = 0;
            tbl_id = SharedPcsXfi0Status_t + (SharedPcsXfi1Status_t - SharedPcsXfi0Status_t)*lane_id;
            fld_id = SharedPcsXfi0Status_hiBer0_f;  
        }
    }
    else
    { 
        index = DRV_INS(port_attr->txqm_id, 0);
        tbl_id = McMacPcsDebugStats_t;
        step = McMacPcsDebugStats_dbgMcMacPcs_1_dbgPcsRxHiBer_f - McMacPcsDebugStats_dbgMcMacPcs_0_dbgPcsRxHiBer_f;
        fld_id = McMacPcsDebugStats_dbgMcMacPcs_0_dbgPcsRxHiBer_f + step*factor;
    }
    if(1 == flag)
    {
        *hiber_value = SYS_TMM_USELESS_ID8;
    }
    else
    {
        cmd = DRV_IOR(tbl_id, fld_id);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, hiber_value));
    }
    /*error block*/
    if(SYS_TMM_CPUMAC_HSS_ID == hss_id)
    {
        if((CTC_CHIP_SERDES_SGMII_MODE == port_attr->pcs_mode)||(CTC_CHIP_SERDES_2DOT5G_MODE == port_attr->pcs_mode))
        {
            index = 0;
            step = SharedPcsSgmii1Status_t - SharedPcsSgmii0Status_t;
            tbl_id = SharedPcsSgmii0Status_t + step * lane_id;
            fld_id = SharedPcsSgmii0Status_codeErrCnt0_f;
        }
        else
        {
            index = 0;
            step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
            tbl_id = SharedPcsXfi0Status_t + step *lane_id;
            fld_id = SharedPcsXfi0Status_errBlockCnt0_f;    
        }
    }
    else
    {
        index = DRV_INS(port_attr->txqm_id, 0);
        tbl_id = McMacPcsDebugStats_t;
        step = McMacPcsDebugStats_dbgMcMacPcs_1_dbgPcsRxErrBlockCnt_f - McMacPcsDebugStats_dbgMcMacPcs_0_dbgPcsRxErrBlockCnt_f;
        fld_id = McMacPcsDebugStats_dbgMcMacPcs_0_dbgPcsRxErrBlockCnt_f + step*factor;
    }
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, error_block));

    return CTC_E_NONE; 
}

int32
sys_tmm_mac_check_xgfec_rx_block_lock(uint8 lchip, uint8 logical_serdes_id, uint16 lport, uint32* fec_lock)
{
    uint8  hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logical_serdes_id);
    uint8  lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);
    uint32 fec_val   = 0;
    uint8  ctcxs_id  = 0;
    uint8  is_ctchs  = 0;
    uint32 tbl_id    = 0;
    uint32 fld_id    = 0;
    uint32 cmd       = 0;
    uint32 index     = 0;
    uint16 step      = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_fec_en(lchip, lport, &fec_val));
    if(((CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val)) && 
    ((CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode)
    ||(CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode)
    ||(CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
    ||(CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)))
    {
        if(SYS_TMM_CPUMAC_HSS_ID == hss_id)
        {
            if(((CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val)) &&
            ((CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode)))
            {
                step = XgFec2StatusSharedFec_t - XgFec0StatusSharedFec_t;
                tbl_id = XgFec0StatusSharedFec_t + step * lane_id;
                fld_id = XgFec0StatusSharedFec_dbgXgFec0RxBlockLock_f;       
            }
            else if(((CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val)) &&
            (CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode))
            {
                fld_id = XgFec0StatusSharedFec_dbgXgFec0RxBlockLock_f;      
                step = XgFec2StatusSharedFec_t - XgFec0StatusSharedFec_t;
                for(tbl_id = XgFec0StatusSharedFec_t; tbl_id <= XgFec6StatusSharedFec_t; tbl_id += step)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, fec_lock));
                    if(0 == *fec_lock)
                    {
                        break;
                    }
                }
                return CTC_E_NONE;       
            }
            else if(((CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val)) &&
            (CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode))
            {
                if(2 >= lane_id)
                {
                    fld_id = XgFec0StatusSharedFec_dbgXgFec0RxBlockLock_f;
                    step = XgFec1StatusSharedFec_t - XgFec0StatusSharedFec_t;
                    for(tbl_id = XgFec0StatusSharedFec_t; tbl_id <= XgFec3StatusSharedFec_t; tbl_id += step)
                    { 
                        cmd = DRV_IOR(tbl_id, fld_id);
                        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, fec_lock));
                        if(0 == *fec_lock)
                        {
                            break;
                        }
                    }
                    return CTC_E_NONE;       
                }
                else
                {
                    fld_id = XgFec0StatusSharedFec_dbgXgFec0RxBlockLock_f;
                    step = XgFec1StatusSharedFec_t - XgFec0StatusSharedFec_t;
                    for(tbl_id = XgFec4StatusSharedFec_t; tbl_id <= XgFec7StatusSharedFec_t; tbl_id += step)
                    {
                        cmd = DRV_IOR(tbl_id, fld_id);
                        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, fec_lock));
                        if(0 == *fec_lock)
                        {
                            break;
                        }
                    }
                    return CTC_E_NONE;      
                }
            }
            else
            {
                *fec_lock = SYS_TMM_USELESS_ID8;
            }
        }
        else
        {
            SYS_TMM_GET_CTCXS_ID_BY_HSS_ID(hss_id, ctcxs_id, is_ctchs);
            index = DRV_INS(ctcxs_id, 0);
            if(is_ctchs)
            {
                    /*HS last 8 lane*/
                if((logical_serdes_id % SYS_TMM_PCS_X16_LANE_NUM) / SYS_TMM_LANE_NUM_PER_HSS)
                {           
                    tbl_id = McPcsX16LanesRxBBlockLockMon_t;
                    step = McPcsX16LanesRxBBlockLockMon_monRxBlockLockLane_1_monXgFecRxBlockLock_f - McPcsX16LanesRxBBlockLockMon_monRxBlockLockLane_0_monXgFecRxBlockLock_f;
                    fld_id = McPcsX16LanesRxBBlockLockMon_monRxBlockLockLane_0_monXgFecRxBlockLock_f + step * lane_id;
                }
                    /*HS first 8 lane*/
                else
                {
                    tbl_id = McPcsX16LanesRxABlockLockMon_t;
                    step = McPcsX16LanesRxABlockLockMon_monRxBlockLockLane_1_monXgFecRxBlockLock_f - McPcsX16LanesRxABlockLockMon_monRxBlockLockLane_0_monXgFecRxBlockLock_f;
                    fld_id = McPcsX16LanesRxABlockLockMon_monRxBlockLockLane_0_monXgFecRxBlockLock_f + step * lane_id;
                }
            }
            else
            {
                tbl_id = McPcsX8LanesRxBlockLockMon_t;
                step =  McPcsX8LanesRxBlockLockMon_monRxBlockLockLane_1_monXgFecRxBlockLock_f - McPcsX8LanesRxBlockLockMon_monRxBlockLockLane_0_monXgFecRxBlockLock_f;
                fld_id = McPcsX8LanesRxBlockLockMon_monRxBlockLockLane_0_monXgFecRxBlockLock_f + step * lane_id;
            }
        }
        cmd = DRV_IOR(tbl_id, fld_id);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, fec_lock));     
    }
    else 
    {
        *fec_lock = SYS_TMM_USELESS_ID8;
    }
    return CTC_E_NONE;
}

int32
sys_tmm_mac_check_rx_cwm_lock(uint8 lchip, uint8 logical_serdes_id, uint16 lport, uint32* rx_cwm_lock)
{
    uint8  hss_id    = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logical_serdes_id);
    uint8  lane_id   = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);
    uint32 fec_val = 0;
    uint8  ctcxs_id  = 0;
    uint8  is_ctchs  = 0;
    uint32 tbl_id    = 0;
    uint32 fld_id    = 0;
    uint32 cmd       = 0;
    uint32 index     = 0;
    uint16 step = 0;

    CTC_ERROR_RETURN(_sys_tmm_mac_get_fec_en(lchip, lport, &fec_val));
    if((CTC_PORT_FEC_TYPE_RS528 == fec_val) || (CTC_PORT_FEC_TYPE_RS544 == fec_val) || (CTC_PORT_FEC_TYPE_RS272 == fec_val))
    {
        if(SYS_TMM_CPUMAC_HSS_ID == hss_id)
        {
            *rx_cwm_lock = SYS_TMM_USELESS_ID8;
            return CTC_E_NONE;
        }
        else
        {
            SYS_TMM_GET_CTCXS_ID_BY_HSS_ID(hss_id, ctcxs_id, is_ctchs);
            index = DRV_INS(ctcxs_id, 0);
            if(is_ctchs)
            {
                /*HS last 8 lane*/
                if((logical_serdes_id % SYS_TMM_PCS_X16_LANE_NUM) / SYS_TMM_LANE_NUM_PER_HSS)
                {           
                    tbl_id = McPcsX16LanesRxBCwmLockMon_t;
                    step = McPcsX16LanesRxBCwmLockMon_monRxCwmLockLane_1_monRxCwmLock_f - McPcsX16LanesRxBCwmLockMon_monRxCwmLockLane_0_monRxCwmLock_f;
                    fld_id = McPcsX16LanesRxBCwmLockMon_monRxCwmLockLane_0_monRxCwmLock_f + step * lane_id;
                }
                /*HS first 8 lane*/
                else
                {
                    tbl_id = McPcsX16LanesRxACwmLockMon_t;
                    step = McPcsX16LanesRxACwmLockMon_monRxCwmLockLane_1_monRxCwmLock_f - McPcsX16LanesRxACwmLockMon_monRxCwmLockLane_0_monRxCwmLock_f;
                    fld_id = McPcsX16LanesRxACwmLockMon_monRxCwmLockLane_0_monRxCwmLock_f + step * lane_id;
                }
            }
            else
            {
                tbl_id = McPcsX8LanesRxCwmLockMon_t;
                step = McPcsX8LanesRxCwmLockMon_monRxCwmLockLane_1_monRxCwmLock_f - McPcsX8LanesRxCwmLockMon_monRxCwmLockLane_0_monRxCwmLock_f;
                fld_id = McPcsX8LanesRxCwmLockMon_monRxCwmLockLane_0_monRxCwmLock_f + step * lane_id;
            }
        } 
        cmd = DRV_IOR(tbl_id, fld_id);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_cwm_lock));
    }
    else
    {
        *rx_cwm_lock = SYS_TMM_USELESS_ID8;         
    }
    return CTC_E_NONE;
}

int32
sys_tmm_mac_check_rx_block_lock(uint8 lchip, uint8 logical_serdes_id, uint16 lport, uint32* rx_block_lock)
{
    uint8  hss_id       = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logical_serdes_id);
    uint8  lane_id      = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);
    uint32 index        = 0;
    uint32 fec_val      = 0;
    uint8  ctcxs_id     = 0;
    uint8  is_ctchs     = 0;
    uint32 tbl_id       = 0;
    uint32 fld_id       = 0;
    uint32 cmd          = 0;
    uint16 step         = 0;
    uint8  lane_num     = 0;
    uint32 fld_id_start = 0;
    uint32 fld_id_end   = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_fec_en(lchip, lport, &fec_val));
    if(SYS_TMM_CPUMAC_HSS_ID == hss_id)
    {
        if(((CTC_PORT_FEC_TYPE_NONE == fec_val)) &&
        ((CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode)
        ||(CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode)))
        {
            step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
            tbl_id = SharedPcsXfi0Status_t + step * lane_id;
            fld_id = SharedPcsXfi0Status_rxBlockLock0_f;        
        }
        else if(((CTC_PORT_FEC_TYPE_NONE == fec_val)) &&
        (CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode))
        {
            fld_id = SharedPcsXfi0Status_rxBlockLock0_f;        
            step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
            for(tbl_id = SharedPcsXfi0Status_t; tbl_id <= SharedPcsXfi3Status_t; tbl_id += step)
            {
                cmd = DRV_IOR(tbl_id, fld_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_block_lock));
                if(0 == *rx_block_lock)
                {
                    break;
                }
            }
            return CTC_E_NONE;       
        }
        else if((CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode) && (CTC_PORT_FEC_TYPE_NONE == fec_val))
        {
            if(2 <= lane_id)
            {
                tbl_id = SharedPcsLgStatus_t;
                for(fld_id = SharedPcsLgStatus_lgPcs1RxBlockLock0_f; fld_id <= SharedPcsLgStatus_lgPcs1RxBlockLock3_f; fld_id ++)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_block_lock));
                    if(0 == *rx_block_lock)
                    {
                        break;
                    }
                }    
                return CTC_E_NONE;    
            }
            else
            {
                fld_id = SharedPcsXfi0Status_rxBlockLock0_f;        
                step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
                for(tbl_id = SharedPcsXfi0Status_t; tbl_id <= SharedPcsXfi3Status_t; tbl_id += step)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_block_lock));
                    if(0 == *rx_block_lock)
                    {
                        break;
                    }
                }
                return CTC_E_NONE;      
            }
        }
        else if((CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode) && (CTC_PORT_FEC_TYPE_NONE == fec_val))
        {
            tbl_id = SharedPcsCgStatus_t;
            for(fld_id = SharedPcsCgStatus_cgRxBlockLock0_f; fld_id <= SharedPcsCgStatus_cgRxBlockLock19_f; fld_id ++)
            {
                cmd = DRV_IOR(tbl_id, fld_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_block_lock));
                if(0 == *rx_block_lock)
                {
                    break;
                }
            }
            return CTC_E_NONE;
        }
        else
        {
            *rx_block_lock = SYS_TMM_USELESS_ID8;
            return CTC_E_NONE;
        }
    }    
    else    
    {
        SYS_TMM_GET_CTCXS_ID_BY_HSS_ID(hss_id, ctcxs_id, is_ctchs);
        index = DRV_INS(ctcxs_id, 0);
        if(is_ctchs)
        {
            if(((CTC_PORT_FEC_TYPE_NONE == fec_val) || (CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val)) &&
            ((CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_LG_R1_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_CG_R2_MODE == port_attr->pcs_mode)))
            {
                if((CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
                ||(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode))
                {
                    lane_num = 4;
                }
                else if((CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
                ||(CTC_CHIP_SERDES_CG_R2_MODE == port_attr->pcs_mode))
                {
                    lane_num = 2;
                }
                else
                {
                    lane_num = 1;
                }
                /*LAST 8 LANE*/
                if((logical_serdes_id % SYS_TMM_PCS_X16_LANE_NUM) / SYS_TMM_LANE_NUM_PER_HSS)
                {
                    tbl_id = McPcsX16LanesRxBBlockLockMon_t;
                    step = McPcsX16LanesRxBBlockLockMon_monRxBlockLockLane_1_monRxBlockLock_f - McPcsX16LanesRxBBlockLockMon_monRxBlockLockLane_0_monRxBlockLock_f;
                    fld_id_start = McPcsX16LanesRxBBlockLockMon_monRxBlockLockLane_0_monRxBlockLock_f + step *lane_id;
                    fld_id_end = fld_id_start + lane_num * step;
                    for(fld_id = fld_id_start ; fld_id < fld_id_end ; fld_id += step)
                    {
                        cmd = DRV_IOR(tbl_id, fld_id);
                        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_block_lock));
                        if(0 == *rx_block_lock)
                        {
                            break;
                        }
                    }
                    return CTC_E_NONE;    
                }
                 /*FIRST 8 LANE*/
                else
                {
                    tbl_id = McPcsX16LanesRxABlockLockMon_t;
                    step = McPcsX16LanesRxABlockLockMon_monRxBlockLockLane_1_monRxBlockLock_f - McPcsX16LanesRxABlockLockMon_monRxBlockLockLane_0_monRxBlockLock_f;
                    fld_id_start = McPcsX16LanesRxABlockLockMon_monRxBlockLockLane_0_monRxBlockLock_f + step * lane_id;
                    fld_id_end = fld_id_start + lane_num * step;
                    for(fld_id = fld_id_start; fld_id < fld_id_end; fld_id +=step)
                    {
                        cmd = DRV_IOR(tbl_id, fld_id);
                        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_block_lock));
                        if(0 == *rx_block_lock)
                        {
                            break;
                        }
                    }
                    return CTC_E_NONE; 
                }
            }
            else
            {
                *rx_block_lock = SYS_TMM_USELESS_ID8;
                return CTC_E_NONE;
            }
        }
        else
        {
            if(((CTC_PORT_FEC_TYPE_NONE == fec_val) || (CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val)) &&
            ((CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_XFI_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_LG_R1_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_CG_R2_MODE == port_attr->pcs_mode)))
            {
                if((CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
                ||(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode))
                {
                    lane_num = 4;
                }
                else if((CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
                ||(CTC_CHIP_SERDES_CG_R2_MODE == port_attr->pcs_mode))
                {
                    lane_num = 2;
                }
                else
                {
                    lane_num = 1;
                }
                tbl_id = McPcsX8LanesRxBlockLockMon_t;
                step = McPcsX8LanesRxBlockLockMon_monRxBlockLockLane_1_monRxBlockLock_f - McPcsX8LanesRxBlockLockMon_monRxBlockLockLane_0_monRxBlockLock_f;
                fld_id_start = McPcsX8LanesRxBlockLockMon_monRxBlockLockLane_0_monRxBlockLock_f + step * lane_id;
                fld_id_end = fld_id_start + lane_num*step;
                for(fld_id = fld_id_start;fld_id < fld_id_end; fld_id +=step)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_block_lock));
                    if(0 == *rx_block_lock)
                    {
                        break;
                    }
                }
                return CTC_E_NONE;
            }
            else
            {
                *rx_block_lock = SYS_TMM_USELESS_ID8;
                return CTC_E_NONE;
            }
        }
    }
    cmd = DRV_IOR(tbl_id, fld_id);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_block_lock));
    return CTC_E_NONE;
}

int32
sys_tmm_mac_check_rx_am_lock(uint8 lchip, uint8 logical_serdes_id, uint16 lport, uint32* rx_am_lock)
{
    uint8  hss_id       = SYS_TMM_MAP_SERDES_TO_HSS_IDX(logical_serdes_id);
    uint8  lane_id      = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);
    uint32 index        = 0;
    uint32 fec_val      = 0;
    uint8  ctcxs_id     = 0;
    uint8  is_ctchs     = 0;
    uint32 tbl_id       = 0;
    uint32 fld_id       = 0;
    uint32 cmd          = 0;
    uint16 step         = 0;
    uint8  lane_num     = 0;
    uint32 fld_id_start = 0;
    uint32 fld_id_end   = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_fec_en(lchip, lport, &fec_val));
    if(SYS_TMM_CPUMAC_HSS_ID == hss_id)
    {
        if(((CTC_PORT_FEC_TYPE_NONE == fec_val)) &&
        (CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode))
        {
            tbl_id = SharedPcsXlgStatus_t;
            for(fld_id = SharedPcsXlgStatus_rxAmLock0_f; fld_id <= SharedPcsXlgStatus_rxAmLock3_f; fld_id ++)
            {
                cmd = DRV_IOR(tbl_id, fld_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                if(0 == *rx_am_lock)
                {
                    break;
                }
            }
            return CTC_E_NONE;       
        }
        else if(((CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val)) &&
        (CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode))
        {
            tbl_id =  SharedPcsXlgStatus_t;
            for(fld_id =  SharedPcsXlgStatus_rxAmLock0_f; fld_id <= SharedPcsXlgStatus_rxAmLock3_f; fld_id++)
            {
                cmd = DRV_IOR(tbl_id, fld_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                if(0 == *rx_am_lock)
                {
                    break;
                }
            }
            return CTC_E_NONE;       
        }
        else if(((CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val)) &&
        (CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode))
        {
            if(2 >= lane_id)
            {
                tbl_id = SharedPcsXlgStatus_t;
                for(fld_id =  SharedPcsXlgStatus_rxAmLock0_f; fld_id <= SharedPcsXlgStatus_rxAmLock3_f; fld_id++)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock))
                    if(0 == *rx_am_lock)
                    {
                        break;
                    }
                }
                return CTC_E_NONE;       
            }
            else
            {
                tbl_id = SharedPcsLgStatus_t;
                for(fld_id = SharedPcsLgStatus_lgPcs1RxAmLock0_f; fld_id <= SharedPcsLgStatus_lgPcs1RxAmLock3_f; fld_id ++)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                    if(0 == *rx_am_lock)
                    {
                        break;
                    }
                }    
                return CTC_E_NONE;
            }
        }
        else if(((CTC_PORT_FEC_TYPE_RS == fec_val) || (CTC_PORT_FEC_TYPE_RS528 == fec_val)) &&
        (CTC_CHIP_SERDES_XXVG_MODE == port_attr->pcs_mode))
        {
            tbl_id = GlobalStatusSharedFec_t;
            step = GlobalStatusSharedFec_dbgSharedFecAmLock1_f - GlobalStatusSharedFec_dbgSharedFecAmLock0_f;
            fld_id = GlobalStatusSharedFec_dbgSharedFecAmLock0_f + lane_id * step;
            cmd = DRV_IOR(tbl_id, fld_id);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
            return CTC_E_NONE;   
        }
        else if((CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode) && (CTC_PORT_FEC_TYPE_NONE == fec_val))
        {
            if(2 <= lane_id)
            {
                tbl_id = SharedPcsLgStatus_t;
                for(fld_id = SharedPcsLgStatus_lgPcs1RxAmLock0_f; fld_id <= SharedPcsLgStatus_lgPcs1RxAmLock3_f; fld_id ++)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                    if(0 == *rx_am_lock)
                    {
                        break;
                    }
                }    
                return CTC_E_NONE;            
            }
            else
            {
                tbl_id = SharedPcsXlgStatus_t;
                for(fld_id = SharedPcsXlgStatus_rxAmLock0_f; fld_id <= SharedPcsXlgStatus_rxAmLock3_f; fld_id ++)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                    if(0 == *rx_am_lock)
                    {
                        break;
                    }
                }
                return CTC_E_NONE;       
            }
        }
        else if((CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode) && ((CTC_PORT_FEC_TYPE_RS == fec_val)||(CTC_PORT_FEC_TYPE_RS528 == fec_val)))
        {
            if(2 <= lane_id)
            {
                tbl_id = GlobalStatusSharedFec_t;
                for(fld_id = GlobalStatusSharedFec_dbgSharedFecAmLock2_f; fld_id <= GlobalStatusSharedFec_dbgSharedFecAmLock3_f; fld_id ++)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                    if(0 == *rx_am_lock)
                    {
                        break;
                    }
                }    
            return CTC_E_NONE;            
            }
            else
            {
                tbl_id = GlobalStatusSharedFec_t;
                for(fld_id = GlobalStatusSharedFec_dbgSharedFecAmLock0_f; fld_id <= GlobalStatusSharedFec_dbgSharedFecAmLock1_f; fld_id ++)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                    if(0 == *rx_am_lock)
                    {
                        break;
                    }
                }
                return CTC_E_NONE;       
            }
        }
        else if((CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode) && (CTC_PORT_FEC_TYPE_NONE == fec_val))
        {
            tbl_id = SharedPcsCgStatus_t;
            for(fld_id = SharedPcsCgStatus_cgRxAmLock0_f; fld_id <= SharedPcsCgStatus_cgRxAmLock19_f; fld_id ++)
            {
                cmd = DRV_IOR(tbl_id, fld_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                if(0 == *rx_am_lock)
                {
                    break;
                }
            }
            return CTC_E_NONE;
        }
        else if((CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode) && ((CTC_PORT_FEC_TYPE_RS == fec_val)||(CTC_PORT_FEC_TYPE_RS528 == fec_val)))
        {
            tbl_id = GlobalStatusSharedFec_t;
            for(fld_id = GlobalStatusSharedFec_dbgSharedFecAmLock0_f; fld_id <= GlobalStatusSharedFec_dbgSharedFecAmLock3_f; fld_id ++)
            {
                cmd = DRV_IOR(tbl_id, fld_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                if(0 == *rx_am_lock)
                {
                    break;
                }
            }
            return CTC_E_NONE;
        }
        else
        {
            *rx_am_lock = SYS_TMM_USELESS_ID8;
            return CTC_E_NONE;
        }
    }    
    else    
    {
        SYS_TMM_GET_CTCXS_ID_BY_HSS_ID(hss_id, ctcxs_id, is_ctchs);
        index = DRV_INS(ctcxs_id, 0);
        if(is_ctchs)
        {
            if(((CTC_PORT_FEC_TYPE_NONE == fec_val) || (CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val)) &&
            ((CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_LG_R1_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_CG_R2_MODE == port_attr->pcs_mode)))
            {
                if((CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
                ||(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode))
                {
                    lane_num = 4;
                }
                else if((CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
                ||(CTC_CHIP_SERDES_CG_R2_MODE == port_attr->pcs_mode))
                {
                    lane_num = 2;
                }
                else
                {
                    lane_num = 1;
                }
                /*LAST 8 LANE*/
                if((logical_serdes_id % SYS_TMM_PCS_X16_LANE_NUM) / SYS_TMM_LANE_NUM_PER_HSS)
                {
                    tbl_id = McPcsX16LanesRxBAmLockMon_t;
                    step = McPcsX16LanesRxBAmLockMon_monRxAmLockLane_1_monRxAmLock_f - McPcsX16LanesRxBAmLockMon_monRxAmLockLane_0_monRxAmLock_f;
                    fld_id_start = McPcsX16LanesRxBAmLockMon_monRxAmLockLane_0_monRxAmLock_f + step * lane_id;
                    fld_id_end = fld_id_start + lane_num * step;
                    for(fld_id = fld_id_start;fld_id < fld_id_end; fld_id += step)
                    {
                        cmd = DRV_IOR(tbl_id, fld_id);
                        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                        if(0 == *rx_am_lock)
                        {
                            break;
                        }
                    }
                    return CTC_E_NONE;
                }
                 /*FIRST 8 LANE*/
                else
                {
                    tbl_id = McPcsX16LanesRxAAmLockMon_t;
                    step = McPcsX16LanesRxAAmLockMon_monRxAmLockLane_1_monRxAmLock_f - McPcsX16LanesRxAAmLockMon_monRxAmLockLane_0_monRxAmLock_f;
                    fld_id_start = McPcsX16LanesRxAAmLockMon_monRxAmLockLane_0_monRxAmLock_f + step * lane_id;
                    fld_id_end = fld_id_start + lane_num * step;
                    for(fld_id = fld_id_start; fld_id < fld_id_end; fld_id += step)
                    {
                        cmd = DRV_IOR(tbl_id, fld_id);
                        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                        if(0 == *rx_am_lock)
                        {
                            break;
                        }
                    }
                    return CTC_E_NONE;
                }
            }
            else
            {
                *rx_am_lock = SYS_TMM_USELESS_ID8;
                return CTC_E_NONE;
            }
        }
        else
        {
            if(((CTC_PORT_FEC_TYPE_NONE == fec_val) || (CTC_PORT_FEC_TYPE_BASER == fec_val) || (CTC_PORT_FEC_TYPE_FC2112 == fec_val)) &&
            ((CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_LG_R1_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode)
            ||(CTC_CHIP_SERDES_CG_R2_MODE == port_attr->pcs_mode)))
            {
                if((CTC_CHIP_SERDES_XLG_MODE == port_attr->pcs_mode)
                ||(CTC_CHIP_SERDES_CG_MODE == port_attr->pcs_mode))
                {
                    lane_num = 4;
                }
                else if((CTC_CHIP_SERDES_LG_MODE == port_attr->pcs_mode)
                ||(CTC_CHIP_SERDES_CG_R2_MODE == port_attr->pcs_mode))
                {
                    lane_num = 2;
                }
                else
                {
                    lane_num = 1;
                }
                tbl_id = McPcsX8LanesRxAmLockMon_t;
                step =  McPcsX8LanesRxAmLockMon_monRxAmLockLane_1_monRxAmLock_f - McPcsX8LanesRxAmLockMon_monRxAmLockLane_0_monRxAmLock_f ;
                fld_id = McPcsX8LanesRxAmLockMon_monRxAmLockLane_0_monRxAmLock_f + step * lane_id;
                fld_id_start = McPcsX8LanesRxAmLockMon_monRxAmLockLane_0_monRxAmLock_f + step * lane_id;
                fld_id_end = fld_id_start + step * lane_num;
                for(fld_id = fld_id_start; fld_id < fld_id_end; fld_id += step)
                {
                    cmd = DRV_IOR(tbl_id, fld_id);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, rx_am_lock));
                    if(0 == *rx_am_lock)
                    {
                        break;
                    }
                }
                return CTC_E_NONE;
            }
            else
            {
                *rx_am_lock = SYS_TMM_USELESS_ID8;
                return CTC_E_NONE;
            }
        }
    }
    return CTC_E_NONE;
}

int32
_sys_tmm_mac_set_link_filter(uint8 lchip, uint16 lport, uint8 filter_type, uint32 filter_ms)
{
    uint32 index       = 0;
    uint32 cmd         = 0;
    uint32 tbl_id      = 0;
    uint32 fld_id      = 0;
    uint32 txqm_id     = 0;
    uint32 txqm_mac_id = 0;
    uint32 value       = 0;
    uint32 en          = 0;
    uint32 step        = 0;
    McMacMiiRxCfg_m    mii_rx;
    SharedMii0Cfg_m    mii_per_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));

    if(25 < filter_ms)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% filter length %u(ms) not support, max 25ms! lport %u, filter_type %u\n", 
            filter_ms, lport, filter_type);
        return CTC_E_NOT_SUPPORT;
    }

    en    = (0 == filter_ms) ? 0 : 1;
    value = filter_ms * 10; /*TMM pulse is 0.1ms, so timer value enlarge by x10*/
    
    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        txqm_mac_id = TXQM_INNER_MAC_ID(port_attr->mac_id);
        txqm_id     = port_attr->txqm_id;
        step        = McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiRxLinkFilterEn_f - 
                      McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterEn_f;
        index       = DRV_INS(txqm_id, 0);
        cmd         = DRV_IOR(McMacMiiRxCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_rx));

        if(SYS_MAC_LINK_FILTER == filter_type)
        {
            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterEn_f + step * txqm_mac_id;
            DRV_IOW_FIELD_NZ(lchip, McMacMiiRxCfg_t, fld_id, &en, &mii_rx, txqm_id, 0);

            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterTimer_f + step * txqm_mac_id;
            DRV_IOW_FIELD_NZ(lchip, McMacMiiRxCfg_t, fld_id, &value, &mii_rx, txqm_id, 0);
        }
        else if(SYS_MAC_FAULT_FILTER == filter_type)
        {
            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterEn_f + step * txqm_mac_id;
            DRV_IOW_FIELD_NZ(lchip, McMacMiiRxCfg_t, fld_id, &en, &mii_rx, txqm_id, 0);

            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterTimer_f + step * txqm_mac_id;
            DRV_IOW_FIELD_NZ(lchip, McMacMiiRxCfg_t, fld_id, &value, &mii_rx, txqm_id, 0);
        }
        else
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% filter type %u not support! lport %u, filter_ms %u\n", 
                filter_type, lport, filter_ms);
            return CTC_E_NOT_SUPPORT;
        }

        cmd = DRV_IOW(McMacMiiRxCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_rx));
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {

        if(SYS_MAC_LINK_FILTER == filter_type)
        {
            tbl_id = SharedMii0Cfg_t + port_attr->mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

            DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f,    &en, &mii_per_cfg);
            DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f, &value, &mii_per_cfg);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));
        }
        else
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% filter type %u not support! lport %u, filter_ms %u\n", 
                filter_type, lport, filter_ms);
            return CTC_E_NOT_SUPPORT;
        }
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid lport %u! port_type %u\n", lport, port_attr->port_type);
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_link_filter(uint8 lchip, uint16 lport, uint8 filter_type, uint32* p_filter_ms)
{
    uint32 index       = 0;
    uint32 cmd         = 0;
    uint32 tbl_id      = 0;
    uint32 fld_id      = 0;
    uint32 txqm_id     = 0;
    uint32 txqm_mac_id = 0;
    uint32 value       = 0;
    uint32 en          = 0;
    uint32 step        = 0;
    McMacMiiRxCfg_m    mii_rx;
    SharedMii0Cfg_m    mii_per_cfg;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    
    if(port_attr->port_type == SYS_DMPS_NETWORK_PORT)
    {
        txqm_id     = port_attr->txqm_id;
        txqm_mac_id = TXQM_INNER_MAC_ID(port_attr->mac_id);
        step        = McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMcMacMiiRxLinkFilterEn_f - 
                      McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterEn_f;
        index       = DRV_INS(txqm_id, 0);
        cmd         = DRV_IOR(McMacMiiRxCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_rx));

        if(SYS_MAC_LINK_FILTER == filter_type)
        {
            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterEn_f + step * txqm_mac_id;
            DRV_IOR_FIELD(lchip, McMacMiiRxCfg_t, fld_id, &en, &mii_rx);

            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxLinkFilterTimer_f + step * txqm_mac_id;
            DRV_IOR_FIELD(lchip, McMacMiiRxCfg_t, fld_id, &value, &mii_rx);
        }
        else if(SYS_MAC_FAULT_FILTER == filter_type)
        {
            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterEn_f + step * txqm_mac_id;
            DRV_IOR_FIELD(lchip, McMacMiiRxCfg_t, fld_id, &en, &mii_rx);

            fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMcMacMiiRxFaultFilterTimer_f + step * txqm_mac_id;
            DRV_IOR_FIELD(lchip, McMacMiiRxCfg_t, fld_id, &value, &mii_rx);
        }
        else
        {
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% filter type %u not support! lport %u\n", filter_type, lport);
            return CTC_E_NOT_SUPPORT;
        }
    }
    else if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {

        if(SYS_MAC_LINK_FILTER == filter_type)
        {
            tbl_id = SharedMii0Cfg_t + port_attr->mii_idx*(SharedMii1Cfg_t - SharedMii0Cfg_t);
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

            DRV_IOR_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterEn0_f,    &en,    &mii_per_cfg);
            DRV_IOR_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiRxLinkFilterTimer0_f, &value, &mii_per_cfg);
        }
        else
        {
            en    = 0;
            value = 0;
        }
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Invalid lport %u! port_type %u\n", lport, port_attr->port_type);
        return CTC_E_INVALID_PARAM;
    }

    /*TMM pulse is 0.1ms, do round off to get ms*/
    if((0 == en) || (0 == value))
    {
        SYS_USW_VALID_PTR_WRITE(p_filter_ms, 0);
    }
    else
    {
        SYS_USW_VALID_PTR_WRITE(p_filter_ms, ((value + 5) / 10));
    }

    return CTC_E_NONE;
}

/*Get mac voq status*/
int32
_sys_tmm_mac_get_voq_status(uint8 lchip, uint16 lport, uint32* p_value)
{
    uint32 index     = 0;
    uint16 mac_id    = SYS_TMM_USELESS_ID16;
    uint32 txqm_id   = 0;
    uint32 inner_mac = 0;
    uint32 tbl_id    = McMacMiiRxDebugStats_t;
    uint32 fld_id    = McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxBuffEmpty_f;
    uint32 cmd       = 0;
    uint32 val32     = 0;
    McMacMiiRxDebugStats_m mii_rx;
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));
    CTC_ERROR_RETURN(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    mac_id = port_attr->mac_id;
    SYS_CONDITION_RETURN((SYS_TMM_MAX_MAC_NUM <= mac_id) || (NULL == p_value), CTC_E_NONE);

    txqm_id = mac_id / SYS_TMM_MAX_MAC_NUM_PER_TXQM;
    inner_mac = SYS_TMM_GET_MACID_PER_TXQM(mac_id);

    index  = DRV_INS(txqm_id, 0);
    fld_id += inner_mac * (McMacMiiRxDebugStats_dbgMcMacMiiRx_1_dbgMiiRxBuffEmpty_f - McMacMiiRxDebugStats_dbgMcMacMiiRx_0_dbgMiiRxBuffEmpty_f);
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mii_rx));
    DRV_IOR_FIELD(lchip, tbl_id, fld_id, &val32, &mii_rx);

    *p_value = (0 == val32) ? 1 : 0;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_self_checking_serdes_info(uint8 lchip, sys_datapath_lport_attr_t* port_attr)
{
    uint8  serdes_idx;
    uint8  serdes_num          = port_attr->serdes_num;
    uint8  logical_serdes_id   = 0;
    uint8  physicl_serdes_id   = 0;
    uint8  hss_id              = 0;
    uint8  inner_lane_id       = 0;
    uint32 factor              = 100000;
    uint8  idx;
    uint32 value               = 0;
    uint8  val_u8              = 0;
    uint16 val_u16             = 0;
    uint16 ctle[3]             = {0};
    int8   coefficient_8[CTC_CHIP_FFE_PARAM_NUM] = {0};
    ctc_chip_serdes_loopback_t loopback = {0};
    ctc_chip_serdes_prbs_t     prbs = {0};
    ctc_chip_pll_lock_status_t pll = {0};
    ctc_chip_serdes_cfg_t      opt_mode = {0};
    sys_datapath_hss_attribute_t* p_hss_vec = NULL;
    char* prbs_pat[] = {
        "PRBS7+", 
        "PRBS7-", 
        "PRBS15+", 
        "PRBS15-", 
        "PRBS23+", 
        "PRBS23-", 
        "PRBS31+", 
        "PRBS31-", 
        "PRBS9", 
        "PRBS13", 
        "PRBS9Q", 
        "PRBS13Q", 
        "PRBS15Q", 
        "PRBS31Q", 
        "PRBS9QP", 
        "PRBS13QP", 
        "PRBS15QP", 
        "PRBS31QP"
    };

    /*serdes config*/
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "SerDes Index BaudRate(G) OVCLK Loopback TX-PRBS  TX-FFE\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    hss_id = SYS_TMM_MAP_SERDES_TO_HSS_IDX(port_attr->multi_serdes_id[0]);
    p_hss_vec = ctc_vector_get(p_usw_datapath_master[lchip]->p_hss_vector, hss_id);
    for(serdes_idx = 0; serdes_idx < serdes_num; serdes_idx++)
    {
        physicl_serdes_id = port_attr->multi_serdes_id[serdes_idx];
        CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, physicl_serdes_id, &logical_serdes_id));
        inner_lane_id = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);        
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-6u %-5u ", physicl_serdes_id, logical_serdes_id);
        
        (void)sys_tmm_serdes_get_real_data_rate(p_hss_vec->serdes_info[inner_lane_id].mode, 
            (uint8)(p_hss_vec->serdes_info[inner_lane_id].overclocking_speed), &value);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%2u.%-8u ", value/factor, value - value/factor*factor);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-5u ", p_hss_vec->serdes_info[inner_lane_id].overclocking_speed);
        
        loopback.serdes_id = physicl_serdes_id;
        loopback.mode = 0;
        (void)_sys_tmm_datapath_get_serdes_loopback(lchip, &loopback);
        value = loopback.enable;
        loopback.mode = 1;
        (void)_sys_tmm_datapath_get_serdes_loopback(lchip, &loopback);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-8s ", (FALSE == value) ? 
            ((FALSE == loopback.enable) ? ("Disable") : ("Ext")) : ((FALSE == loopback.enable) ? ("Int") : ("Int&Ext")));

        prbs.serdes_id = physicl_serdes_id;
        (void)sys_tmm_serdes_get_tx_prbs(lchip, &prbs);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-8s ", 1 == prbs.value ? prbs_pat[prbs.polynome_type] : "Disable");

        (void)sys_tmm_serdes_get_tx_taps(lchip, physicl_serdes_id, coefficient_8);
        for(idx = 0; idx < CTC_CHIP_FFE_PARAM_NUM; idx++)
        {
            if(0 != idx)
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, ",");
            }
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%d", coefficient_8[idx]);
        }

        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
    }

    /*serdes status*/
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "       PLL    SigDet Ready EyeHeight TX/RX-Polarity OptMode\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    for(serdes_idx = 0; serdes_idx < serdes_num; serdes_idx++)
    {
        physicl_serdes_id = port_attr->multi_serdes_id[serdes_idx];
        CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, physicl_serdes_id, &logical_serdes_id));
        inner_lane_id = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-6u ", physicl_serdes_id);

        pll.serdes_id = physicl_serdes_id;
        pll.type      = CTC_CHIP_PLL_LOCK_TYPE_SERDES;
        (void)sys_tmm_datapath_get_pll_lock(lchip, (void*)(&pll));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-6s ", (FALSE == pll.status) ? "Unlock" : "Lock");

        (void)sys_tmm_serdes_get_signal_detect(lchip, physicl_serdes_id, NULL, &val_u8);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-6s ", (0 == val_u8) ? "No" : "Yes");

        (void)sys_tmm_serdes_get_phyready(lchip, physicl_serdes_id, &value);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-5s ", (0 == value) ? "No" : "Yes");

        (void)sys_tmm_serdes_get_eye(lchip, physicl_serdes_id, &value);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-9u ", value);

        (void)sys_tmm_serdes_get_polarity(lchip, physicl_serdes_id, 1, &val_u8);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%u/", val_u8);

        (void)sys_tmm_serdes_get_polarity(lchip, physicl_serdes_id, 0, &val_u8);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%u            ", val_u8);

        opt_mode.serdes_id = physicl_serdes_id;
        (void)sys_tmm_datapath_get_serdes_optical_mode(lchip, (void*)(&opt_mode));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-8s ", (0 == opt_mode.value) ? "Disable" : "Enable");

        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
    }

    /*FW status*/
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "       FWStat RstCnt TuneCnt TuneStat     CTLE  Gain-1 Gain-2\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    for(serdes_idx = 0; serdes_idx < serdes_num; serdes_idx++)
    {
        physicl_serdes_id = port_attr->multi_serdes_id[serdes_idx];
        CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, physicl_serdes_id, &logical_serdes_id));
        inner_lane_id = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-6u ", physicl_serdes_id);
        /*FW running status*/
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-6s ", (_sys_tmm_serdes_is_fw_running(lchip, physicl_serdes_id)) ? "Run" : "Stop");
        /*FW reset counter*/
        (void)sys_tmm_serdes_get_fw_reg(lchip, physicl_serdes_id, 4, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-6u ", val_u16);
        /*FW tuning counter*/
        (void)sys_tmm_serdes_get_fw_reg(lchip, physicl_serdes_id, 5, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-7u ", val_u16);
        /*FW tuning status*/
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, FW_TUNING_STATUS_ADDR, 0x0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x[%s] ", val_u16, (val_u16 == 0x4 ? "Done" : (val_u16 == 0x8 ? "Fail" : "Bkg?")));
        /*CTLE*/
        (void)sys_tmm_serdes_get_ctle(lchip, physicl_serdes_id, &(ctle[0]), &(ctle[1]), &(ctle[2]));
        for(idx = 0; idx < 3; idx++)
        {
            if(0 != idx)
            {
                SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, ",");
            }
            SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%u", ctle[idx]);
        }
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " ");
        /*CTLE gain 1 & 2*/
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, CTLE_GAIN1_ADDR, CTLE_GAIN1_MASK, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, CTLE_GAIN2_ADDR, CTLE_GAIN2_MASK, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);

        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
    }

    /*Key register*/
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "       0x980f 0x00a0 0x010b 0x9811 0x00f5 0x9810 0x8000 0x010d 0x9814\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    for(serdes_idx = 0; serdes_idx < serdes_num; serdes_idx++)
    {
        physicl_serdes_id = port_attr->multi_serdes_id[serdes_idx];
        CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, physicl_serdes_id, &logical_serdes_id));
        inner_lane_id = SYS_TMM_MAP_SERDES_TO_LANE_ID(logical_serdes_id);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-6u ", physicl_serdes_id);

        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, 0x980f, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, 0x00a0, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, 0x010b, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, 0x9811, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, 0x00f5, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, 0x9810, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, 0x8000, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, 0x010d, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);
        (void)sys_tmm_serdes_read_reg(lchip, physicl_serdes_id, 0x9814, 0, &val_u16);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "0x%04x ", val_u16);

        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
    }
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");

    return CTC_E_NONE;
}

int32
sys_tmm_mac_self_checking(uint8 lchip, uint16 lport)
{
    uint8  logical_serdes_id   = 0;
    uint32 hiber_value         = 0;
    uint32 error_block         = 0;
    uint32 fec_val             = 0;
    uint8  serdes_idx;
    uint32 value               = 0;
    uint8  val_u8              = 0;
    int32  ret                 = 0;
    ctc_port_fec_cnt_t fec_cnt = {0};
    sys_datapath_lport_attr_t* port_attr = NULL;
    char* speed[CTC_PORT_SPEED_MAX] = {
        "1G",   //CTC_PORT_SPEED_1G
        "100M", //CTC_PORT_SPEED_100M
        "10M",  //CTC_PORT_SPEED_10M
        "2.5G", //CTC_PORT_SPEED_2G5
        "10G",  //CTC_PORT_SPEED_10G
        "20G",  //CTC_PORT_SPEED_20G
        "40G",  //CTC_PORT_SPEED_40G
        "100G", //CTC_PORT_SPEED_100G
        "5G",   //CTC_PORT_SPEED_5G
        "25G",  //CTC_PORT_SPEED_25G
        "50G",  //CTC_PORT_SPEED_50G
        "200G", //CTC_PORT_SPEED_200G
        "400G", //CTC_PORT_SPEED_400G
    };
    char* itf[CTC_PORT_IF_MAX_TYPE] = {
        "-"           , //CTC_PORT_IF_NONE
        "SGMII"       , //CTC_PORT_IF_SGMII
        "2500X"       , //CTC_PORT_IF_2500X
        "QSGMII"      , //CTC_PORT_IF_QSGMII
        "USXGMII-S"   , //CTC_PORT_IF_USXGMII_S
        "USXGMII-M2G5", //CTC_PORT_IF_USXGMII_M2G5
        "USXGMII-M5G" , //CTC_PORT_IF_USXGMII_M5G
        "XAUI"        , //CTC_PORT_IF_XAUI
        "D-XAUI"       , //CTC_PORT_IF_DXAUI
        "XFI"         , //CTC_PORT_IF_XFI
        "KR"          , //CTC_PORT_IF_KR
        "CR"          , //CTC_PORT_IF_CR
        "KR2"         , //CTC_PORT_IF_KR2
        "CR2"         , //CTC_PORT_IF_CR2
        "KR4"         , //CTC_PORT_IF_KR4
        "CR4"         , //CTC_PORT_IF_CR4
        "FX"          , //CTC_PORT_IF_FX
        "KR8"         , //CTC_PORT_IF_KR8
        "CR8"         , //CTC_PORT_IF_CR8
        "FLEXE"       , //CTC_PORT_IF_FLEXE
    };
    char* fec[] = {
        "None"  , //CTC_PORT_FEC_TYPE_NONE
        "RS(528,514)" , //CTC_PORT_FEC_TYPE_RS
        "Base-R FEC", //CTC_PORT_FEC_TYPE_BASER
        "RS(528,514)" , //CTC_PORT_FEC_TYPE_RS528
        "RS(544,514)" , //CTC_PORT_FEC_TYPE_RS544
        "RS(272,514)" , //CTC_PORT_FEC_TYPE_RS272
        "Base-R FEC", //CTC_PORT_FEC_TYPE_FC2112
    };
    char* lt_stat[] = {
        "disable", //SYS_PORT_CL72_DISABLE
        "running", //SYS_PORT_CL72_PROGRESS
        "fail",    //SYS_PORT_CL72_FAIL
        "OK",      //SYS_PORT_CL72_OK
    };

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));
    SYS_CONDITION_RETURN(SYS_MAX_SERDES_NUM_PER_PORT < port_attr->serdes_num, CTC_E_INVALID_PARAM);
    SYS_CONDITION_RETURN(CTC_PORT_SPEED_MAX <= port_attr->speed_mode, CTC_E_INVALID_PARAM);
    SYS_CONDITION_RETURN(CTC_PORT_IF_MAX_TYPE <= port_attr->interface_type, CTC_E_INVALID_PARAM);

    CTC_ERROR_RETURN(_sys_tmm_mac_get_fec_en(lchip, lport, &fec_val));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Port Map\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "LPort", lport);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Datapath Channel", port_attr->chan_id);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "MAC ID", port_attr->mac_id);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "PCS ID", port_attr->pcs_idx);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: ", "SerDes Index");
    for(serdes_idx = 0; serdes_idx < port_attr->serdes_num; serdes_idx++)
    {
        CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, port_attr->multi_serdes_id[serdes_idx], &logical_serdes_id));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%02u ", logical_serdes_id);
    }
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: ", "SerDes");
    for(serdes_idx = 0; serdes_idx < port_attr->serdes_num; serdes_idx++)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%02u ", port_attr->multi_serdes_id[serdes_idx]);
    }
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Port Config\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Speed", speed[port_attr->speed_mode]);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Interface", itf[port_attr->interface_type]);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "FEC", fec[fec_val]);
    CTC_ERROR_RETURN(sys_tmm_mac_get_auto_neg(lchip, lport, CTC_PORT_PROP_AUTO_NEG_EN, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Auto-Neg", (0 == value ? "Disable" : "Enable"));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "MAC-EN", 
        (FALSE == p_usw_mac_master[lchip]->mac_prop[lport].port_mac_en ? "Disable" : "Enable"));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_mac_rx_en(lchip, port_attr->mac_id, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "MAC RX Packet", (0 == value ? "Disable" : "Enable"));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_mac_tx_en(lchip, port_attr->mac_id, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "MAC TX Packet", (0 == value ? "Disable" : "Enable"));
    CTC_ERROR_RETURN(sys_tmm_mac_get_internal_property(lchip, lport, CTC_PORT_PROP_PREAMBLE, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Preamble", value);
    CTC_ERROR_RETURN(sys_tmm_mac_get_ipg(lchip, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "IPG", value & 0x000000ff);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "SuperG2-EN", (value >> 8));
    CTC_ERROR_RETURN(sys_tmm_mac_get_internal_property(lchip, lport, CTC_PORT_PROP_PADING_EN, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Padding", value);
    CTC_ERROR_RETURN(sys_tmm_mac_get_internal_property(lchip, lport, CTC_PORT_PROP_CHK_CRC_EN, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Check-CRC", value);
    CTC_ERROR_RETURN(sys_tmm_mac_get_internal_property(lchip, lport, CTC_PORT_PROP_STRIP_CRC_EN, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Strip-CRC", value);
    CTC_ERROR_RETURN(sys_tmm_mac_get_internal_property(lchip, lport, CTC_PORT_PROP_APPEND_CRC_EN, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Append-CRC", value);
    ret = sys_tmm_mac_get_internal_property(lchip, lport, CTC_PORT_PROP_APPEND_TOD_EN, &value);
    if(CTC_E_NONE == ret)
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Append-TOD", value);
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Append-TOD", "-");
    }
    CTC_ERROR_RETURN(_sys_tmm_mac_get_link_filter(lchip, lport, SYS_MAC_LINK_FILTER, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %ums\n", "Link filter", value);
    CTC_ERROR_RETURN(_sys_tmm_mac_get_link_filter(lchip, lport, SYS_MAC_FAULT_FILTER, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %ums\n", "Fault filter", value);
    value = 0;
    CTC_ERROR_RETURN(_sys_tmm_mac_get_tx_force_fault(lchip, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "TX force fault", 
        SYS_BMP_IS_SET(value, CTC_PORT_FAULT_FORCE) ? "enable" : "disable");
    CTC_ERROR_RETURN(_sys_tmm_mac_get_pcs_rst(lchip, lport, DMPS_RX, &val_u8));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "PCS RX reset", val_u8);
    CTC_ERROR_RETURN(_sys_tmm_mac_get_pcs_rst(lchip, lport, DMPS_TX, &val_u8));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "PCS TX reset", val_u8);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "MAC Status\n");
    CTC_ERROR_RETURN(_sys_tmm_mac_get_link_up(lchip, lport, &value, 0));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Link status", (0 == value ? "down" : "up"));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_link_up_raw(lchip, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Link status raw", (0 == value ? "down" : "up"));
    CTC_ERROR_RETURN(_sys_tmm_mac_get_link_fault(lchip, lport, &value));
    if((CTC_PORT_IF_2500X == port_attr->interface_type) ||
       (CTC_PORT_IF_SGMII == port_attr->interface_type) ||
       (CTC_PORT_IF_QSGMII == port_attr->interface_type))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s %s\n", "RX fault status", itf[port_attr->interface_type], "dont support fault");
    }
    else
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "RX fault status", value);
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Local fault", SYS_BMP_IS_SET(value, CTC_PORT_FAULT_LOCAL));
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Remote fault", SYS_BMP_IS_SET(value, CTC_PORT_FAULT_REMOTE));
    }
    CTC_ERROR_RETURN(_sys_tmm_mac_get_voq_status(lchip, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "VOQ cell status", value);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------------------------------------\n");
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "PCS/PMD Status\n");
    CTC_ERROR_RETURN(_sys_tmm_mac_get_pcs_link_status(lchip, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "PCS sync status", value);
    CTC_ERROR_RETURN(_sys_usw_datapath_get_logical_serdes_id_by_physical(lchip, port_attr->multi_serdes_id[0], &logical_serdes_id));
    CTC_ERROR_RETURN(sys_tmm_mac_check_hiber_error_block(lchip, logical_serdes_id, lport, &hiber_value, &error_block));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "hi_ber", hiber_value);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "Error block", error_block);
    CTC_ERROR_RETURN(sys_tmm_mac_check_xgfec_rx_block_lock(lchip, logical_serdes_id, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s (%u)\n", "rx_block_lock (10/25/40GBASE-R FEC)", 
        ((SYS_TMM_USELESS_ID8 == value) ? "-" : (value ? "true" : "false")), value);
    CTC_ERROR_RETURN(sys_tmm_mac_check_rx_block_lock(lchip, logical_serdes_id, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s (%u)\n", "rx_block_lock (10/25/40/50/100GBASE-R, or FEC)", 
        ((SYS_TMM_USELESS_ID8 == value) ? "-" : (value ? "true" : "false")), value);
    CTC_ERROR_RETURN(sys_tmm_mac_check_rx_cwm_lock(lchip, logical_serdes_id, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s (%u)\n", "cwm_valid (25/50/100/200/400G RS-FEC)", 
        ((SYS_TMM_USELESS_ID8 == value) ? "-" : (value ? "true" : "false")), value);
    CTC_ERROR_RETURN(sys_tmm_mac_check_rx_am_lock(lchip, logical_serdes_id, lport, &value));
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s (%u)\n", "am_lock (40/50/100GBASE-R, FEC or RS-FEC)", 
        ((SYS_TMM_USELESS_ID8 == value) ? "-" : (value ? "true" : "false")), value);
    if(CTC_PORT_FEC_TYPE_NONE != fec_val)
    {
        CTC_ERROR_RETURN(sys_tmm_mac_get_fec_cnt(lchip, lport, &fec_cnt));
    }
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "FEC corrected count", fec_cnt.correct_cnt);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %u\n", "FEC uncorrected count", fec_cnt.uncorrect_cnt);
    CTC_ERROR_RETURN(_sys_usw_mac_get_3ap_training_en(lchip, lport, &value));
    SYS_CONDITION_RETURN(SYS_PORT_CL72_NUM <= value, CTC_E_INVALID_PARAM);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "    %-24s: %s\n", "Training status", lt_stat[value]);

    (void)sys_tmm_mac_self_checking_serdes_info(lchip, port_attr);

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_dir_en(uint8 lchip, uint16 lport, uint8 direcion, uint32 enable)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }

    if(CTC_INGRESS == direcion)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_rx_en(lchip, port_attr->mac_id, enable));
    }
    else
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_mac_tx_en(lchip, port_attr->mac_id, enable));
    }
    MAC_UNLOCK;


    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_dir_en(uint8 lchip, uint16 lport, uint8 direcion, uint32* p_enable)
{
    sys_datapath_lport_attr_t* port_attr = NULL;

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));
    if(!SYS_TMM_IS_NETWORK_PORT(port_attr->port_type))
    {
        MAC_UNLOCK;
        return CTC_E_INVALID_PORT;
    }

    if(CTC_INGRESS == direcion)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_mac_rx_en(lchip, port_attr->mac_id, p_enable));
    }
    else
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_mac_tx_en(lchip, port_attr->mac_id, p_enable));
    }
    MAC_UNLOCK;

    return CTC_E_NONE;
}

/*set directional property in dmps, moved from sys_usw_port.c*/
int32
sys_tmm_mac_set_direction_property(uint8 lchip, uint16 lport, ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32 value)
{
    uint32 egress_value = value;
    int32  ret          = CTC_E_NONE;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port property with direction, lport:%u, property:%d, dir:%d,\
        value:%d\n", lport, port_prop, dir, value);

    SYS_MAC_INIT_CHECK();
    CTC_MAX_VALUE_CHECK(dir, CTC_BOTH_DIRECTION);

    /*do write*/
    if ((CTC_INGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
    {
        switch (port_prop)
        {
            case CTC_PORT_DIR_PROP_MAC_EN:
                value = (value) ? TRUE : FALSE;
                ret = sys_tmm_mac_set_dir_en(lchip, lport, CTC_INGRESS, value);
                break;
            default:
                return CTC_E_INVALID_PARAM;
        }
    }

    value = egress_value;

    if ((CTC_EGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
    {
        switch (port_prop)
        {
            case CTC_PORT_DIR_PROP_MAC_EN:
                value = (value) ? TRUE : FALSE;
                ret = sys_tmm_mac_set_dir_en(lchip, lport, CTC_EGRESS, value);
                break;
            default:
                return CTC_E_INVALID_PARAM;
        }
    }

    CTC_ERROR_RETURN(ret);

    return CTC_E_NONE;
}

/*get directional property in dmps, moved from sys_usw_port.c*/
int32
sys_tmm_mac_get_direction_property(uint8 lchip, uint16 lport, ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32* p_value)
{
    int32  ret = CTC_E_NONE;

    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get port property with direction, lport:%u, property:%d, dir:%d\n", 
        lport, port_prop, dir);

    SYS_MAC_INIT_CHECK();
    CTC_MAX_VALUE_CHECK(dir, CTC_BOTH_DIRECTION - 1);

    /*do read, only get value by CTC_INGRESS or CTC_EGRESS, no CTC_BOTH_DIRECTION*/
    if (CTC_INGRESS == dir)
    {
        switch (port_prop)
        {
            case CTC_PORT_DIR_PROP_MAC_EN:
                ret = sys_tmm_mac_get_dir_en(lchip, lport, CTC_INGRESS, p_value);
                break;
            default:
                return CTC_E_INVALID_PARAM;

        }
    }
    else
    {
        switch (port_prop)
        {
            case CTC_PORT_DIR_PROP_MAC_EN:
                ret = sys_tmm_mac_get_dir_en(lchip, lport, CTC_EGRESS, p_value);
                break;
            default:
                return CTC_E_INVALID_PARAM;
        }
    }

    CTC_ERROR_RETURN(ret);

    return CTC_E_NONE;
}

int32
_sys_tmm_mac_get_pcs_err_cnt(uint8 lchip, uint16 lport, uint32 err_cnt[])
{
    uint32 addr_base[SYS_TMM_TXQM_NUM_PER_DP*2] = {0x6244df00, 0x624cdf00, 0x6106df00, 0x6107df00, 0x6a44df00, 0x6a4cdf00, 0x6906df00, 0x6907df00};
    uint32 addr = 0;
    uint32 ofst = 0x4;
    uint32 value = 0;
    uint8  step             = 0;
    uint32 tb_id            = 0;
    uint32 cmd              = 0;
    SharedPcsXfi0Status0_m pcs;
    SharedPcsSgmii0Status0_m sgm_pcs;
    sys_datapath_lport_attr_t* port_attr = NULL;

    sal_memset(err_cnt, 0, CTC_PORT_SERDES_MAX_NUM*sizeof(uint32));

    CTC_ERROR_RETURN(sys_tmm_datapath_get_port_attr(lchip, lport, &port_attr));

    if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        switch(port_attr->pcs_mode)
        {
            case CTC_CHIP_SERDES_SGMII_MODE:
            case CTC_CHIP_SERDES_2DOT5G_MODE:
                step = SharedPcsSgmii1Status_t - SharedPcsSgmii0Status_t;
                tb_id = SharedPcsSgmii0Status_t + port_attr->internal_mac_idx*step;
                cmd = DRV_IOR(tb_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &sgm_pcs));
                DRV_IOR_FIELD(lchip, tb_id, SharedPcsSgmii0Status_codeErrCnt0_f, &err_cnt[0], &sgm_pcs);
                break;
            case CTC_CHIP_SERDES_XXVG_MODE:
            case CTC_CHIP_SERDES_XFI_MODE:
                step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
                tb_id = SharedPcsXfi0Status_t + port_attr->internal_mac_idx*step;
                cmd = DRV_IOR(tb_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs));
                DRV_IOR_FIELD(lchip, tb_id, SharedPcsXfi0Status_errBlockCnt0_f, &err_cnt[0], &pcs);
                break;
            case CTC_CHIP_SERDES_XLG_MODE:
            case CTC_CHIP_SERDES_CG_MODE:
                tb_id = SharedPcsXfi0Status_t;
                step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
                cmd = DRV_IOR(tb_id+step*0, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs));
                DRV_IOR_FIELD(lchip, tb_id+step*0, SharedPcsXfi0Status_errBlockCnt0_f, &err_cnt[0], &pcs);
                cmd = DRV_IOR(tb_id+step*1, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs));
                DRV_IOR_FIELD(lchip, tb_id+step*1, SharedPcsXfi0Status_errBlockCnt0_f, &err_cnt[1], &pcs);
                cmd = DRV_IOR(tb_id+step*2, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs));
                DRV_IOR_FIELD(lchip, tb_id+step*2, SharedPcsXfi0Status_errBlockCnt0_f, &err_cnt[2], &pcs);
                cmd = DRV_IOR(tb_id+step*3, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs));
                DRV_IOR_FIELD(lchip, tb_id+step*3, SharedPcsXfi0Status_errBlockCnt0_f, &err_cnt[3], &pcs);
                break;
            case CTC_CHIP_SERDES_LG_MODE:
                tb_id = SharedPcsXfi0Status_t;
                step = SharedPcsXfi1Status_t - SharedPcsXfi0Status_t;
                if(port_attr->internal_mac_idx == 0)
                {
                    cmd = DRV_IOR(tb_id+step*0, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs));
                    DRV_IOR_FIELD(lchip, tb_id+step*0, SharedPcsXfi0Status_errBlockCnt0_f, &err_cnt[0], &pcs);
                    cmd = DRV_IOR(tb_id+step*1, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs));
                    DRV_IOR_FIELD(lchip, tb_id+step*1, SharedPcsXfi0Status_errBlockCnt0_f, &err_cnt[1], &pcs);
                }
                else
                {
                    cmd = DRV_IOR(tb_id+step*2, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs));
                    DRV_IOR_FIELD(lchip, tb_id+step*2, SharedPcsXfi0Status_errBlockCnt0_f, &err_cnt[0], &pcs);
                    cmd = DRV_IOR(tb_id+step*3, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pcs));
                    DRV_IOR_FIELD(lchip, tb_id+step*3, SharedPcsXfi0Status_errBlockCnt0_f, &err_cnt[1], &pcs);
                }
                break;
            default:
                break;
        }
    }
    else
    {
        addr = addr_base[port_attr->txqm_id % (SYS_TMM_TXQM_NUM_PER_DP*2)] + (ofst * TXQM_INNER_MAC_ID(port_attr->mac_id));
        CTC_ERROR_RETURN(drv_usw_chip_read(lchip, addr, &value));
        err_cnt[0] = (value & 0x0000ff00) >> 8;
    }

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_link_info(uint8 lchip, uint16 lport, void* p_value)
{
    uint32 is_link_up          = 0;
    uint32 mac_link_status     = 0;
    uint32 pcs_link_status     = 0;
    uint32 unidir_en           = 0;
    uint32 fault               = 0;
    uint32 signal_detect       = 0;
    uint32 serdes_ready        = 0;
    uint32 link_filter         = 0;
    uint32 fault_filter        = 0;
    uint32 voq                 = 0;
    ctc_port_link_info_t*      p_link_info = (ctc_port_link_info_t*)p_value;


    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    MAC_LOCK;
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_up(lchip, lport, &is_link_up, 0));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_up_raw(lchip, lport, &mac_link_status));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_voq_status(lchip, lport, &voq));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_pcs_link_status(lchip, lport, &pcs_link_status));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_unidir_en(lchip, lport, &unidir_en));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_fault(lchip, lport, &fault));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_tx_force_fault(lchip, lport, &fault));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_port_serdes_stat(lchip, lport, SYS_MAC_SERDES_SIGDET, &signal_detect));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_port_serdes_stat(lchip, lport, SYS_MAC_SERDES_READY, &serdes_ready));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_filter(lchip, lport, SYS_MAC_LINK_FILTER, &link_filter));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_filter(lchip, lport, SYS_MAC_FAULT_FILTER, &fault_filter));
    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_pcs_err_cnt(lchip, lport, p_link_info->pcs_err_cnt));
    MAC_UNLOCK;

    p_link_info->is_link_up      = (uint8)is_link_up;
    p_link_info->mac_link_status = (uint8)(voq ? 2 : mac_link_status);
    p_link_info->pcs_link_status = (uint8)pcs_link_status;
    p_link_info->unidir_en       = (uint8)unidir_en;
    p_link_info->fault           = (uint8)fault;
    p_link_info->signal_detect   = (uint8)signal_detect;
    p_link_info->serdes_ready    = (uint8)serdes_ready;
    p_link_info->link_filter     = (uint16)link_filter;
    p_link_info->fault_filter    = (uint16)fault_filter;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_link_info(uint8 lchip, uint16 lport, void* p_value)
{
    ctc_port_link_info_t*      p_link_info = (ctc_port_link_info_t*)p_value;
    uint32 unidir_en           = p_link_info->unidir_en;
    uint32 fault               = p_link_info->fault;
    uint32 link_filter         = p_link_info->link_filter;
    uint32 fault_filter        = p_link_info->fault_filter;
    uint32 cur_unidir_en       = 0;
    uint32 cur_fault           = 0;
    uint32 cur_link_filter     = 0;
    uint32 cur_fault_filter    = 0;

    CTC_ERROR_RETURN(sys_usw_mac_get_lport_by_extlport(lchip, lport, &lport));

    if((25 < link_filter) || (25 < fault_filter))
    {
        SYS_MAC_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% filter length %u %u(ms) not support, max 25ms! lport %u\n", 
            link_filter, fault_filter, lport);
        return CTC_E_NOT_SUPPORT;
    }

    MAC_LOCK;

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_unidir_en(lchip, lport, &cur_unidir_en));
    if(cur_unidir_en != unidir_en)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_unidir_en(lchip, lport, (uint8)unidir_en, FALSE));
    }

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_tx_force_fault(lchip, lport, &cur_fault));
    if(CTC_FLAG_ISSET(fault, CTC_PORT_FAULT_FORCE) != CTC_FLAG_ISSET(cur_fault, CTC_PORT_FAULT_FORCE))
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_tx_force_fault(lchip, lport, fault));
    }

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_filter(lchip, lport, SYS_MAC_LINK_FILTER, &cur_link_filter));
    if(cur_link_filter != link_filter)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_link_filter(lchip, lport, SYS_MAC_LINK_FILTER, link_filter));
    }

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_get_link_filter(lchip, lport, SYS_MAC_FAULT_FILTER, &cur_fault_filter));
    if(cur_fault_filter != fault_filter)
    {
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(_sys_tmm_mac_set_link_filter(lchip, lport, SYS_MAC_FAULT_FILTER, fault_filter));
    }

    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_get_sfd_en(uint8 lchip, uint16 lport, uint32 *enable)
{
    uint32 value       = 0;
    uint32 cmd         = 0;
    uint32 tbl_id      = 0;
    uint32 fld_id      = 0;
    uint16 step        = 0;
    uint8 txqm_id      = 0;
    uint32 index       = 0;
    uint16 txqm_mac_id = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    McMacMiiRxCfg_m           miirx_cfg;
    SharedMii0Cfg_m mii_per_cfg;

    MAC_LOCK;

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        step = SharedMii1Cfg_t - SharedMii0Cfg_t;
        tbl_id = SharedMii0Cfg_t + port_attr->mii_idx * step;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));
        DRV_IOR_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiSfdValue0_f, &value, &mii_per_cfg);
    }
    else
    {
        txqm_id = (port_attr->mac_id / 40);
        txqm_mac_id = (port_attr->mac_id % 40);
        index  = DRV_INS(txqm_id, 0);

        tbl_id = McMacMiiRxCfg_t;
        step = McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMiiSfdValue_f - McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMiiSfdValue_f;
        fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMiiSfdValue_f + step*txqm_mac_id;

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(DRV_IOCTL(lchip, index, cmd, &miirx_cfg));
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &miirx_cfg);
    }

    *enable = (0x5d == value) ? 1 : 0;

    MAC_UNLOCK;

    return CTC_E_NONE;
}

int32
sys_tmm_mac_set_sfd_en(uint8 lchip, uint16 lport, uint32 enable)
{
    uint32 value       = 0;
    uint32 cmd         = 0;
    uint32 tbl_id      = 0;
    uint32 fld_id      = 0;
    uint16 step        = 0;
    uint8 txqm_id      = 0;
    uint32 index       = 0;
    uint16 txqm_mac_id = 0;
    sys_datapath_lport_attr_t* port_attr = NULL;
    McMacMiiRxCfg_m           miirx_cfg;
    SharedMii0Cfg_m mii_per_cfg;

    MAC_LOCK;

    CTC_ERROR_RETURN_WITH_MAC_UNLOCK(sys_usw_mac_get_port_capability(lchip, lport, &port_attr));

    value = (enable ? 0x5d : 0xd5);
    if(SYS_TMM_IS_CPUMAC_PORT(port_attr->port_type))
    {
        step = SharedMii1Cfg_t - SharedMii0Cfg_t;
        tbl_id = SharedMii0Cfg_t + port_attr->mii_idx * step;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));

        DRV_IOW_FIELD(lchip, tbl_id, SharedMii0Cfg_cfgMiiSfdValue0_f, &value, &mii_per_cfg);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(DRV_IOCTL(lchip, index, cmd, &mii_per_cfg));
    }
    else
    {
        if(SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_A)
        {
            MAC_UNLOCK;
            return CTC_E_NONE;
        }
        txqm_id = (port_attr->mac_id / 40);
        txqm_mac_id = (port_attr->mac_id % 40);
        index  = DRV_INS(txqm_id, 0);

        tbl_id = McMacMiiRxCfg_t;
        step = McMacMiiRxCfg_cfgMcMacMiiRx_1_cfgMiiSfdValue_f - McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMiiSfdValue_f;
        fld_id = McMacMiiRxCfg_cfgMcMacMiiRx_0_cfgMiiSfdValue_f + step*txqm_mac_id;

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(DRV_IOCTL(lchip, index, cmd, &miirx_cfg));
        DRV_IOW_FIELD(lchip, tbl_id, fld_id, &value, &miirx_cfg);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN_WITH_MAC_UNLOCK(DRV_IOCTL(lchip, index, cmd, &miirx_cfg));
    }

    MAC_UNLOCK;

    return CTC_E_NONE;
}


